Commit Graph

91044 Commits

Author SHA1 Message Date
Rafael Espindola 1b276c5cec Remove unused method and default values.
llvm-svn: 179124
2013-04-09 20:35:08 +00:00
Eric Christopher 06c89d65d1 Update the version of dwarf we say we're emitting to at least 3.
Deals with a dwarf2 -> dwarf3 DW_FORM_ref_addr change.

llvm-svn: 179122
2013-04-09 20:22:47 +00:00
Chad Rosier e8d8288d7e Revert r179115 as it looks to have killed the ASan tests.
llvm-svn: 179120
2013-04-09 19:59:12 +00:00
Chandler Carruth 9f6b59ae9b Rationalize the formatting of these case labels. Having two sorted
columns is essentially impossible to edit.

llvm-svn: 179119
2013-04-09 19:46:46 +00:00
Reed Kotler 1595f36d6d This patch enables llvm to switch between compiling for mips32/mips64
and mips16 on a per function basis.

Because this patch is somewhat involved I have provide an overview of the
key pieces of it.

The patch is written so as to not change the behavior of the non mixed
mode. We have tested this a lot but it is something new to switch subtargets
so we don't want any chance of regression in the mainline compiler until
we have more confidence in this.

Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1.
For that reason there are derived versions of the register info, frame info, 
instruction info and instruction selection classes.

Now we register three separate passes for instruction selection.
One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then
one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and
MipsSEISelDAGToDAG.cpp).

When the ModuleISel pass runs, it determines if there is a need to switch
subtargets and if so, the owning pointers in MipsTargetMachine are
appropriately changed.

When 16Isel or SEIsel is run, they will return immediately without doing
any work if the current subtarget mode does not apply to them.

In addition, MipsAsmPrinter needs to be reset on a function basis.

The pass BasicTargetTransformInfo is substituted with a null pass since the
pass is immutable and really needs to be a function pass for it to be
used with changing subtargets. This will be fixed in a follow on patch.

llvm-svn: 179118
2013-04-09 19:46:01 +00:00
Nadav Rotem 2d9dec322e Add support for bottom-up SLP vectorization infrastructure.
This commit adds the infrastructure for performing bottom-up SLP vectorization (and other optimizations) on parallel computations.
The infrastructure has three potential users:

  1. The loop vectorizer needs to be able to vectorize AOS data structures such as (sum += A[i] + A[i+1]).

  2. The BB-vectorizer needs this infrastructure for bottom-up SLP vectorization, because bottom-up vectorization is faster to compute.

  3. A loop-roller needs to be able to analyze consecutive chains and roll them into a loop, in order to reduce code size. A loop roller does not need to create vector instructions, and this infrastructure separates the chain analysis from the vectorization.

This patch also includes a simple (100 LOC) bottom up SLP vectorizer that uses the infrastructure, and can vectorize this code:

void SAXPY(int *x, int *y, int a, int i) {
  x[i]   = a * x[i]   + y[i];
  x[i+1] = a * x[i+1] + y[i+1];
  x[i+2] = a * x[i+2] + y[i+2];
  x[i+3] = a * x[i+3] + y[i+3];
}

llvm-svn: 179117
2013-04-09 19:44:35 +00:00
Eric Christopher caeddf5a96 Make check depend on all.
llvm-svn: 179116
2013-04-09 19:42:12 +00:00
Chad Rosier a08f30f093 [ms-inline asm] Use parsePrimaryExpr in lieu of parseExpression if we need to
parse an identifier.  Otherwise, parseExpression may parse multiple tokens,
which makes it impossible to properly compute an immediate displacement.
An example of such a case is the source operand (i.e., [Symbol + ImmDisp]) in
the below example:

 __asm mov eax, [Symbol + ImmDisp]

The existing test cases exercise this patch.
rdar://13611297

llvm-svn: 179115
2013-04-09 19:34:59 +00:00
Eric Christopher 52ce7189c1 The .dwo section shouldn't contain the unrelocated values (and
therefore not at all) of the pc or statement list. We also don't
need to emit the compilation dir so save so space and time
and don't bother.

Fix up the testcase accordingly and verify that we don't emit
the attributes or the items that they use.

llvm-svn: 179114
2013-04-09 19:23:15 +00:00
Hal Finkel 21aad9a8e8 Cleanup PPCEarlyReturn
Some general cleanup and only scan the end of a BB for branches (once we're
done with the terminators and debug values, then there should not be any other
branches). These address post-commit review suggestions by Bill Schmidt.

No functionality change intended.

llvm-svn: 179112
2013-04-09 18:25:18 +00:00
Nadav Rotem abcc64fd13 Revert r176408 and r176407 to address PR15540.
llvm-svn: 179111
2013-04-09 18:16:05 +00:00
Chad Rosier e81309b3bf [ms-inline asm] Maintain a StringRef to reference a symbol in a parsed operand,
rather than deriving the StringRef from the Start and End SMLocs.

Using the Start and End SMLocs works fine for operands such as [Symbol], but
not for operands such as [Symbol + ImmDisp].  All existing test cases that
reference a variable exercise this patch.
rdar://13602265

llvm-svn: 179109
2013-04-09 17:53:49 +00:00
Benjamin Kramer bbae991db6 DAGCombiner: Fold a shuffle on CONCAT_VECTORS into a new CONCAT_VECTORS if possible.
This pattern occurs in SROA output due to the way vector arguments are lowered
on ARM.

The testcase from PR15525 now compiles into this, which is better than the code
we got with the old scalarrepl:
_Store:
	ldr.w	r9, [sp]
	vmov	d17, r3, r9
	vmov	d16, r1, r2
	vst1.8	{d16, d17}, [r0]
	bx	lr

Differential Revision: http://llvm-reviews.chandlerc.com/D647

llvm-svn: 179106
2013-04-09 17:41:43 +00:00
Hal Finkel b5899d5774 Use virtual base registers on PPC
On PowerPC, non-vector loads and stores have r+i forms; however, in functions
with large stack frames these were not being used to access slots far from the
stack pointer because such slots were out of range for the signed 16-bit
immediate offset field. This increases register pressure because we need a
separate register for each offset (when the r+r form is used). By enabling
virtual base registers, we can deal with large stack frames without unduly
increasing register pressure.

llvm-svn: 179105
2013-04-09 17:27:09 +00:00
Hal Finkel 059825b0f8 Convert test PowerPC/2007-09-07-LoadStoreIdxForms to FileCheck
llvm-svn: 179104
2013-04-09 17:26:55 +00:00
Eli Bendersky 1cc814a8e6 Rewrite test/Linker tests to use FileCheck instead of grep.
Some translations here are not 1x1 because there are grep|grep
chains that are non-trivial to implement in terms of FileCheck features. I
made an effort for the tests to remain as similar as possible; do let me know
if you notice anything fishy. The good news are that some buggy tests were
fixed (grep | not grep - a bug waiting to happen).

llvm-svn: 179102
2013-04-09 16:51:13 +00:00
Rafael Espindola c2413f59e4 Convert MachOObjectFile to a template.
For now it is templated only on being 64 or 32 bits. I will add little/big
endian next.

llvm-svn: 179097
2013-04-09 14:49:08 +00:00
Alexey Samsonov d60859b21e DWARF parser: Fix DWARF-2/3 incompatibility: size of DW_FORM_ref_addr is the same as DW_FORM_addr in DWARF2, and is 4/8 bytes on 32/64-bit DWARF starting from DWARF3. Adding a test for this is a huge pain - generating and uploading pre-built binary with DWARF3 debug info is way too ugly, and writing fine-grained unittests for DebugInfo is impossible, as it doesn't expose any headers in include/llvm. That said, I'm going to choose the second approach and submit the patch exposing DebugInfo headers for review soon enough.
llvm-svn: 179095
2013-04-09 14:09:42 +00:00
Michael Gottesman ccc93e72e1 Converted 8x tests of SimplifyCFG to use FileCheck instead of grep.
llvm-svn: 179087
2013-04-09 05:18:53 +00:00
Jakob Stoklund Olesen c910feb4a8 Extract a function.
llvm-svn: 179086
2013-04-09 05:11:52 +00:00
Nadav Rotem 757aec9507 Remove the confusing sentence.
llvm-svn: 179085
2013-04-09 04:48:40 +00:00
Nadav Rotem 7b7585d153 Revert 179071 because it is not the right way to support non standard new/new[] operators.
llvm-svn: 179084
2013-04-09 04:43:46 +00:00
Jakob Stoklund Olesen 2cfe46fd34 Compute correct frame sizes for SPARC v9 64-bit frames.
The save area is twice as big and there is no struct return slot. The
stack pointer is always 16-byte aligned (after adding the bias).

Also eliminate the stack adjustment instructions around calls when the
function has a reserved stack frame.

llvm-svn: 179083
2013-04-09 04:37:47 +00:00
Rafael Espindola eb8b211e61 More uses for SymbolTableEntryBase.
llvm-svn: 179076
2013-04-09 01:04:06 +00:00
Rafael Espindola 5d6cec9bff Add a SymbolTableEntryBase.
Use it when we don't need to know if we have a 32 or 64 bit SymbolTableEntry.

llvm-svn: 179074
2013-04-09 00:22:58 +00:00
Joe Groff 6cdbe3f6df Fix PointerIntPair to be enum class compatible.
Some parts of PointerIntPair assumed that the IntType of the pair was implicitly
convertible to intptr_t, which is not the case for enum class values. Add a
static_cast<intptr_t> to make these conversions explicit and allow
PointerIntPair to be used with an enum class IntType. While we're here, rename
some of the argument values so we don't have variables named "Int" floating
around.

llvm-svn: 179073
2013-04-09 00:01:51 +00:00
Rafael Espindola 65d601f96c Add a SectionBase struct.
Use it to share code and when we don't need to know if we have a 32 or 64
bit Section.

llvm-svn: 179072
2013-04-08 23:57:13 +00:00
Nadav Rotem 9dd90ac5b4 c++ new operators are not malloc-like functions because they do not return uninitialized memory.
Users may overide new-operators and implement any function that they like.

llvm-svn: 179071
2013-04-08 23:40:47 +00:00
NAKAMURA Takumi 065fd35268 InstructionSimplify.cpp: Fix a ligature, "fi", to get rid of utf8 in comment.
llvm-svn: 179066
2013-04-08 23:05:21 +00:00
Shuxin Yang 331f01dcb4 Redo the fix Benjamin Kramer committed in r178793 about iterator invalidation in Reassociate.
I brazenly think this change is slightly simpler than r178793 because: 
  - no "state" in functor
  - "OpndPtrs[i]" looks simpler than "&Opnds[OpndIndices[i]]" 

  While I can reproduce the probelm in Valgrind, it is rather difficult to come up
a standalone testing case. The reason is that when an iterator is invalidated,
the stale invalidated elements are not yet clobbered by nonsense data, so the
optimizer can still proceed successfully. 

  Thank Benjamin for fixing this bug and generously providing the test case.

llvm-svn: 179062
2013-04-08 22:00:43 +00:00
Nadav Rotem fe47d58cf0 Update the docs about the fact that the loop vectorizer is enabled by default for -O3.
llvm-svn: 179060
2013-04-08 21:34:49 +00:00
Rafael Espindola c0406e162c Template the MachO types over the word size.
llvm-svn: 179051
2013-04-08 20:45:01 +00:00
Rafael Espindola 29d4501774 Remove is64BitLoadCommand.
llvm-svn: 179048
2013-04-08 20:18:53 +00:00
Eli Bendersky 19654c01c1 Rewrite test/Integer tests to use FileCheck instead of grep
llvm-svn: 179047
2013-04-08 20:18:15 +00:00
Eli Bendersky ed61b06fa8 Rewrite test/ExecutionEngine tests to use FileCheck instead of grep
llvm-svn: 179043
2013-04-08 19:51:36 +00:00
Matt Arsenault 38b9e136ec Update documentation.
First feature is not CPU subtype anymore since r134127

llvm-svn: 179038
2013-04-08 18:52:58 +00:00
Eli Bendersky aa3ffafbde Rewrite test/Verifier tests to use FileCheck instead of grep
llvm-svn: 179036
2013-04-08 18:33:51 +00:00
Arnold Schwaighofer f47d2d7f6b X86 cost model: Model cost for uitofp and sitofp on SSE2
The costs are overfitted so that I can still use the legalization factor.

For example the following kernel has about half the throughput vectorized than
unvectorized when compiled with SSE2. Before this patch we would vectorize it.

unsigned short A[1024];
double B[1024];
void f() {
  int i;
  for (i = 0; i < 1024; ++i) {
    B[i] = (double) A[i];
  }
}

radar://13599001

llvm-svn: 179033
2013-04-08 18:05:48 +00:00
Chad Rosier fce4fab1a4 [ms-inline asm] Add support for ImmDisp [ Symbol ] memory operands.
rdar://13521249

llvm-svn: 179030
2013-04-08 17:43:47 +00:00
Hal Finkel b5aa7e54d9 Generate PPC early conditional returns
PowerPC has a conditional branch to the link register (return) instruction: BCLR.
This should be used any time when we'd otherwise have a conditional branch to a
return. This adds a small pass, PPCEarlyReturn, which runs just prior to the
branch selection pass (and, importantly, after block placement) to generate
these conditional returns when possible. It will also eliminate unconditional
branches to returns (these happen rarely; most of the time these have already
been tail duplicated by the time PPCEarlyReturn is invoked). This is a nice
optimization for small functions that do not maintain a stack frame.

llvm-svn: 179026
2013-04-08 16:24:03 +00:00
Alexey Samsonov c03f2ee0ae DWARF parser: remove duplicated code and fix code style in DIE extractors.
llvm-svn: 179023
2013-04-08 14:37:16 +00:00
Rafael Espindola d66c414619 Add all 4 MachO object types. Use the stored type to implement is64Bits().
llvm-svn: 179021
2013-04-08 13:25:33 +00:00
Vincent Lejeune 5f11dd390a R600: Control Flow support for pre EG gen
llvm-svn: 179020
2013-04-08 13:05:49 +00:00
Chandler Carruth a6d5e3e9a2 Simplify the quoting here. Our lit emulator doesn't deal well with the
nested quoting schemes, and they're not important here...

llvm-svn: 179014
2013-04-08 10:07:50 +00:00
Chandler Carruth 3fa99abfae Remove a global 'endl' variable from the other file as well.
llvm-svn: 179010
2013-04-08 08:55:18 +00:00
Chandler Carruth 1819289607 Clean up namespaces in obj2yaml.cpp.
llvm-svn: 179009
2013-04-08 08:55:14 +00:00
Tim Northover 85c19f5a73 Add ACLE link to ARM documentation sections
llvm-svn: 179006
2013-04-08 08:42:24 +00:00
Tim Northover 15410e98d3 AArch64: remove barriers from AArch64 atomic operations.
I've managed to convince myself that AArch64's acquire/release
instructions are sufficient to guarantee C++11's required semantics,
even in the sequentially-consistent case.

llvm-svn: 179005
2013-04-08 08:40:41 +00:00
Chandler Carruth c224e25d49 Cleanup the formatting of obj2yaml.cpp.
I couldn't touch this file and not clean it up some. These reformattings
brought to you by clang-format, with some minor adjustments by me. More
spring cleaning to follow here.

llvm-svn: 179004
2013-04-08 08:39:59 +00:00
Chandler Carruth 741c00df17 Don't define our own global 'endl' variable. While technically it had
internal linkage and so wasn't a patent bug, it doesn't make any sense
here. We can avoid even calling operator<< by just embedding the newline
in the string literals that were already being streamed out. It also
gives the impression of some line-ending agnosticisms which is not
present, and that flushing happens when it doesn't.

If we want to use std::endl, we could do that, but honestly it doesn't
seem remotely worth it. Using '\n' directly is much more clear when
working with raw_ostream.

It also happens to fix builds with old crufty GCC STL implementations
that include std::endl into the global namespace (or headers written to
be compatible with such atrocities).

llvm-svn: 179003
2013-04-08 08:30:47 +00:00
Benjamin Kramer d56a324e30 ARM: Remove unused variable.
llvm-svn: 179001
2013-04-08 08:07:35 +00:00
Hal Finkel 81f8799fe3 Cleanup and improve PPC fsel generation
First, we should not cheat: fsel-based lowering of select_cc is a
finite-math-only optimization (the ISA manual, section F.3 of v2.06, makes
this clear, as does a note in our own README).

This also adds fsel-based lowering of EQ and NE condition codes. As it turned
out, fsel generation was covered by a grand total of zero regression test
cases. I've added some test cases to cover the existing behavior (which is now
finite-math only), as well as the new EQ cases.

llvm-svn: 179000
2013-04-07 22:11:09 +00:00
Arnold Schwaighofer 995ce6c388 TargetLowering: Fix getTypeConversion handling of extended vector types
The code in getTypeConversion attempts to promote the element vector type
before it trys to split or widen the vector.
After it failed finding a legal vector type by promoting it would continue using
the promoted vector element type. Thereby missing legal splitted vector types.
For example the type v32i32 that has a legal split of 4 x v3i32 on x86/sse2
would be transformed to: v32i256 and from there on successively split to:
v16i256, v8i256, v1i256 and then finally ends up as an i64 type.
By resetting the vector element type to the original vector element type that
existed before the promotion the code will attempt to split the vector type to
smaller vector widths of the same type.

llvm-svn: 178999
2013-04-07 20:22:56 +00:00
Rafael Espindola 421305aff8 Make MachOObjectFile independent from MachOObject.
llvm-svn: 178998
2013-04-07 20:01:29 +00:00
Rafael Espindola c1f28b6a8e Implement MachOObjectFile::getData directly.
llvm-svn: 178997
2013-04-07 19:42:15 +00:00
Rafael Espindola 28814d7911 Implement MachOObjectFile::is64Bit directly.
llvm-svn: 178996
2013-04-07 19:38:15 +00:00
Rafael Espindola 774a8cec37 Implement MachOObjectFile::getHeaderSize directly.
llvm-svn: 178995
2013-04-07 19:31:49 +00:00
Rafael Espindola d665259104 Implement MachOObjectFile::getHeader directly.
llvm-svn: 178994
2013-04-07 19:26:57 +00:00
Jakob Stoklund Olesen a30f4832c9 Implement LowerCall_64 for the SPARC v9 64-bit ABI.
There is still no support for byval arguments (which I don't think are
needed) and varargs.

llvm-svn: 178993
2013-04-07 19:10:57 +00:00
Rafael Espindola 60689987ef Implement MachOObjectFile::getHeaderSize and MachOObjectFile::getData.
These were the last missing forwarding functions. Also consistently use
the forwarding functions instead of using MachOObj directly.

llvm-svn: 178992
2013-04-07 19:05:30 +00:00
Rafael Espindola 3c50f06202 Remove LoadCommandInfo now that we always have a pointer to the command.
LoadCommandInfo was needed to keep a command and its offset in the file. Now
that we always have a pointer to the command, we don't need the offset.

llvm-svn: 178991
2013-04-07 18:42:06 +00:00
Rafael Espindola 224208b868 Add MachOObjectFile::LoadCommandInfo.
This avoids using MachOObject::getLoadCommandInfo.

llvm-svn: 178990
2013-04-07 18:08:12 +00:00
Rafael Espindola 1309a448ff Use getLoadCommandInfo instead of MachOObj->getLoadCommandInfo.
llvm-svn: 178989
2013-04-07 17:41:59 +00:00
Rafael Espindola 17bece31af Construct MachOObject in MachOObjectFile's constructor.
llvm-svn: 178988
2013-04-07 16:58:48 +00:00
Rafael Espindola 717c4d44c4 Remove unused argument.
llvm-svn: 178987
2013-04-07 16:40:00 +00:00
Rafael Espindola 5ffc079c8a Remove MachOObjectFile::getObject.
llvm-svn: 178986
2013-04-07 16:07:35 +00:00
Rafael Espindola 31fce89645 Remove two uses of getObject.
llvm-svn: 178985
2013-04-07 15:46:05 +00:00
Rafael Espindola 79bb550577 Remove usage of InMemoryStruct in getSymbol.
llvm-svn: 178984
2013-04-07 15:35:18 +00:00
Hal Finkel d04bb0b8ff PPC Altivec load/store intrinsics can be marked IntrRead[Write]ArgMem
llvm-svn: 178983
2013-04-07 15:32:40 +00:00
Hal Finkel 7795e47b5e PPC rotate instructions don't have unmodeled side effcts
llvm-svn: 178982
2013-04-07 15:06:53 +00:00
Rafael Espindola 6f5d6c7e78 Remove a use of InMemoryStruct in llvm-readobj.
llvm-svn: 178981
2013-04-07 15:05:12 +00:00
Rafael Espindola 0944c13e6b Make getObject const. Remove a const_cast.
llvm-svn: 178980
2013-04-07 14:50:40 +00:00
Rafael Espindola b7b11f7bac Remove last use of InMemoryStruct in llvm-objdump.
llvm-svn: 178979
2013-04-07 14:40:18 +00:00
Hal Finkel b47a69acde Most PPC M[TF]CR instructions do not have side effects
llvm-svn: 178978
2013-04-07 14:33:13 +00:00
Rafael Espindola 7be6ead7a4 Remove dead code.
llvm-svn: 178977
2013-04-07 14:30:21 +00:00
Rafael Espindola 91e626ebd2 Remove unused argument.
llvm-svn: 178976
2013-04-07 14:25:39 +00:00
Chandler Carruth 0e8a52d18f Fix PR15674 (and PR15603): a SROA think-o.
The fix for PR14972 in r177055 introduced a real think-o in the *store*
side, likely because I was much more focused on the load side. While we
can arbitrarily widen (or narrow) a loaded value, we can't arbitrarily
widen a value to be stored, as that changes the width of memory access!
Lock down the code path in the store rewriting which would do this to
only handle the intended circumstance.

All of the existing tests continue to pass, and I've added a test from
the PR.

llvm-svn: 178974
2013-04-07 11:47:54 +00:00
Hal Finkel d71cc3a7f3 PPC pre-increment load instructions do not have side effects
A few were missed in r178972.

llvm-svn: 178973
2013-04-07 06:30:47 +00:00
Hal Finkel 6efd45e902 PPC pre-increment load instructions do not have side effects
llvm-svn: 178972
2013-04-07 05:46:58 +00:00
Hal Finkel 933e8f037d PPC MCRF instruction does not have side effects
llvm-svn: 178971
2013-04-07 05:16:57 +00:00
Hal Finkel 94072b98eb PPC FMR instruction does not have side effects
llvm-svn: 178970
2013-04-07 04:56:16 +00:00
Eric Christopher 55863befd1 DW_FORM_sec_offset should be a relocation on platforms that use
a relocation across sections. Do this for DW_AT_stmt list in the
skeleton CU and check the relocations in the debug_info section.

Add a FIXME for multiple CUs.

llvm-svn: 178969
2013-04-07 03:43:09 +00:00
Reid Kleckner c1c01d5313 [cmake] Avoid rel+asserts warnings when passing -UNDEBUG
MSVC 2012 gives warning D9025, "overriding /D NDEBUG with -UNDEBUG".
Removing the original definition of NDEBUG silences this.

llvm-svn: 178967
2013-04-07 01:45:01 +00:00
Jakob Stoklund Olesen edaf66b056 Implement LowerReturn_64 for SPARC v9.
Integer return values are sign or zero extended by the callee, and
structs up to 32 bytes in size can be returned in registers.

The CC_Sparc64 CallingConv definition is shared between
LowerFormalArguments_64 and LowerReturn_64. Function arguments and
return values are passed in the same registers.

The inreg flag is also used for return values. This is required to handle
C functions returning structs containing floats and ints:

  struct ifp {
    int i;
    float f;
  };

  struct ifp f(void);

LLVM IR:

  define inreg { i32, float } @f() {
     ...
     ret { i32, float } %retval
  }

The ABI requires that %retval.i is returned in the high bits of %i0
while %retval.f goes in %f1.

Without the inreg return value attribute, %retval.i would go in %i0 and
%retval.f would go in %f3 which is a more efficient way of returning
%multiple values, but it is not ABI compliant for returning C structs.

llvm-svn: 178966
2013-04-06 23:57:33 +00:00
Jakob Stoklund Olesen 03d9f7fda6 SPARC v9 stack pointer bias.
64-bit SPARC v9 processes use biased stack and frame pointers, so the
current function's stack frame is located at %sp+BIAS .. %fp+BIAS where
BIAS = 2047.

This makes more local variables directly accessible via [%fp+simm13]
addressing.

llvm-svn: 178965
2013-04-06 21:38:57 +00:00
Hal Finkel d61d4f80e6 Implement PPCInstrInfo::FoldImmediate
There are certain PPC instructions into which we can fold a zero immediate
operand. We can detect such cases by looking at the register class required
by the using operand (so long as it is not otherwise constrained).

llvm-svn: 178961
2013-04-06 19:30:30 +00:00
Hal Finkel 8fc33e5d95 PPC ISEL is a select and never has side effects
llvm-svn: 178960
2013-04-06 19:30:28 +00:00
Hal Finkel 537ec71775 Add a comment to TargetInstrInfo about FoldImmediate
This comment documents the current behavior of the ARM implementation of this
callback, and also the soon-to-be-committed PPC version.

llvm-svn: 178959
2013-04-06 19:30:20 +00:00
Jakob Stoklund Olesen 1c9a95ab2a Complete formal arguments for the SPARC v9 64-bit ABI.
All arguments are formally assigned to stack positions and then promoted
to floating point and integer registers. Since there are more floating
point registers than integer registers, this can cause situations where
floating point arguments are assigned to registers after integer
arguments that where assigned to the stack.

Use the inreg flag to indicate 32-bit fragments of structs containing
both float and int members.

The three-way shadowing between stack, integer, and floating point
registers requires custom argument lowering. The good news is that
return values are passed in the exact same way, and we can share the
code.

Still missing:

 - Update LowerReturn to handle structs returned in registers.
 - LowerCall.
 - Variadic functions.

llvm-svn: 178958
2013-04-06 18:32:12 +00:00
Nadav Rotem c4bd84c1d5 typo
llvm-svn: 178949
2013-04-06 04:24:12 +00:00
Rafael Espindola 91af8e84b9 Remove last use of InMemoryStruct from MachOObjectFile.cpp.
llvm-svn: 178948
2013-04-06 03:50:05 +00:00
Rafael Espindola 15e2a9cd57 Don't use InMemoryStruct<macho::SymtabLoadCommand>.
This also required not using the RegisterStringTable API, which is also a
good thing.

llvm-svn: 178947
2013-04-06 03:31:08 +00:00
Rafael Espindola a65f5de499 Don't use InMemoryStruct in getSymbol64TableEntry.
llvm-svn: 178946
2013-04-06 02:15:44 +00:00
Rafael Espindola 2a34c2d8dd Don't use InMemoryStruct in getSymbolTableEntry.
llvm-svn: 178945
2013-04-06 01:59:05 +00:00
Rafael Espindola 7caf2fbdc3 Don't use InMemoryStruct in getRelocation.
llvm-svn: 178943
2013-04-06 01:24:11 +00:00
Manman Ren 5b22f9fe18 Dwarf: use utostr on CUID to append to SmallString.
We used to do "SmallString += CUID", which is incorrect, since CUID will
be truncated to a char.

rdar://problem/13573833

llvm-svn: 178941
2013-04-06 01:02:38 +00:00
Michael Gottesman 7924997c36 Removed trailing whitespace.
llvm-svn: 178932
2013-04-05 23:46:45 +00:00
Tom Stellard 754f80ff3a R600/SI: Add support for buffer stores v2
v2:
  - Use the ADDR64 bit

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178931
2013-04-05 23:31:51 +00:00
Tom Stellard 6db08eb42f R600/SI: Use same names for corresponding MUBUF operands and encoding fields
The code emitter knows how to encode operands whose name matches one of
the encoding fields.  If there is no match, the code emitter relies on
the order of the operand and field definitions to determine how operands
should be encoding.  Matching by order makes it easy to accidentally break
the instruction encodings, so we prefer to match by name.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178930
2013-04-05 23:31:44 +00:00
Tom Stellard 60174bb9ca R600: Add RV670 processor
This is an R600 GPU with double support.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178929
2013-04-05 23:31:40 +00:00
Tom Stellard 2f21c7e551 R600/SI: Add processor types for each SI variant
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178928
2013-04-05 23:31:35 +00:00
Tom Stellard edbf1eb42b R600/SI: Avoid generating S_MOVs with 64-bit immediates v2
SITargetLowering::analyzeImmediate() was converting the 64-bit values
to 32-bit and then checking if they were an inline immediate.  Some
of these conversions caused this check to succeed and produced
S_MOV instructions with 64-bit immediates, which are illegal.

v2:
  - Clean up logic

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178927
2013-04-05 23:31:20 +00:00
Hal Finkel ed6a28597b Enable early if conversion on PPC
On cores for which we know the misprediction penalty, and we have
the isel instruction, we can profitably perform early if conversion.
This enables us to replace some small branch sequences with selects
and avoid the potential stalls from mispredicting the branches.

Enabling this feature required implementing canInsertSelect and
insertSelect in PPCInstrInfo; isel code in PPCISelLowering was
refactored to use these functions as well.

llvm-svn: 178926
2013-04-05 23:29:01 +00:00
Hal Finkel 85526f2e71 Correct the PPC A2 misprediction penalty
The manual states that there is a minimum of 13 cycles from when the
mispredicted branch is issued to when the correct branch target is
issued.

llvm-svn: 178925
2013-04-05 23:28:58 +00:00
Michael Gottesman 31ba23aa56 An objc_retain can serve as a use for a different pointer.
This is the counterpart to commit r160637, except it performs the action
in the bottomup portion of the data flow analysis.

llvm-svn: 178922
2013-04-05 22:54:32 +00:00
Michael Gottesman 1d8d25777d Properly model precise lifetime when given an incomplete dataflow sequence.
The normal dataflow sequence in the ARC optimizer consists of the following
states:

    Retain -> CanRelease -> Use -> Release

The optimizer before this patch stored the uses that determine the lifetime of
the retainable object pointer when it bottom up hits a retain or when top down
it hits a release. This is correct for an imprecise lifetime scenario since what
we are trying to do is remove retains/releases while making sure that no
``CanRelease'' (which is usually a call) deallocates the given pointer before we
get to the ``Use'' (since that would cause a segfault).

If we are considering the precise lifetime scenario though, this is not
correct. In such a situation, we *DO* care about the previous sequence, but
additionally, we wish to track the uses resulting from the following incomplete
sequences:

  Retain -> CanRelease -> Release   (TopDown)
  Retain <- Use <- Release          (BottomUp)

*NOTE* This patch looks large but the most of it consists of updating
test cases. Additionally this fix exposed an additional bug. I removed
the test case that expressed said bug and will recommit it with the fix
in a little bit.

llvm-svn: 178921
2013-04-05 22:54:28 +00:00
Hal Finkel 3005c299b5 Reapply r178845 with fix - Fix bug in PEI's virtual-register scavenging
This fixes PEI as previously described, but correctly handles the case where
the instruction defining the virtual register to be scavenged is the first in
the block. Arnold provided me with a bugpoint-reduced test case, but even that
seems too large to use as a regression test. If I'm successful in cleaning it
up then I'll commit that as well.

Original commit message:

    This change fixes a bug that I introduced in r178058. After a register is
    scavenged using one of the available spills slots the instruction defining the
    virtual register needs to be moved to after the spill code. The scavenger has
    already processed the defining instruction so that registers killed by that
    instruction are available for definition in that same instruction. Unfortunately,
    after this, the scavenger needs to iterate through the spill code and then
    visit, again, the instruction that defines the now-scavenged register. In order
    to avoid confusion, the register scavenger needs the ability to 'back up'
    through the spill code so that it can again process the instructions in the
    appropriate order. Prior to this fix, once the scavenger reached the
    just-moved instruction, it would assert if it killed any registers because,
    having already processed the instruction, it believed they were undefined.

    Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar
    for diagnosing the problem and testing this fix.

llvm-svn: 178919
2013-04-05 22:31:56 +00:00
Bill Wendling eb108bad50 Use the target options specified on a function to reset the back-end.
During LTO, the target options on functions within the same Module may
change. This would necessitate resetting some of the back-end. Do this for X86,
because it's a Friday afternoon.

llvm-svn: 178917
2013-04-05 21:52:40 +00:00
Hal Finkel 81c46d0809 Revert r178845 - Fix bug in PEI's virtual-register scavenging
Reverting because this breaks one of the LTO builders. Original commit message:

    This change fixes a bug that I introduced in r178058. After a register is
    scavenged using one of the available spills slots the instruction defining the
    virtual register needs to be moved to after the spill code. The scavenger has
    already processed the defining instruction so that registers killed by that
    instruction are available for definition in that same instruction. Unfortunately,
    after this, the scavenger needs to iterate through the spill code and then
    visit, again, the instruction that defines the now-scavenged register. In order
    to avoid confusion, the register scavenger needs the ability to 'back up'
    through the spill code so that it can again process the instructions in the
    appropriate order. Prior to this fix, once the scavenger reached the
    just-moved instruction, it would assert if it killed any registers because,
    having already processed the instruction, it believed they were undefined.

    Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar
    for diagnosing the problem and testing this fix.

llvm-svn: 178916
2013-04-05 21:30:40 +00:00
Jim Grosbach bdbd73460c Tidy up a bit. No functional change.
llvm-svn: 178915
2013-04-05 21:20:12 +00:00
Shuxin Yang 95adf5258f Disable the optimization about promoting vector-element-access with symbolic index.
This optimization is unstable at this moment; it 
  1) block us on a very important application
  2) PR15200
  3) test6 and test7 in test/Transforms/ScalarRepl/dynamic-vector-gep.ll
     (the CHECK command compare the output against wrong result)

   I personally believe this optimization should not have any impact on the
autovectorized code, as auto-vectorizer is supposed to put gather/scatter
in a "right" way.  Although in theory downstream optimizaters might reveal 
some gather/scatter optimization opportunities, the chance is quite slim.

   For the hand-crafted vectorizing code, in term of redundancy elimination,
load-CSE, copy-propagation and DSE can collectively achieve the same result,
but in much simpler way. On the other hand, these optimizers are able to 
improve the code in a incremental way; in contrast, SROA is sort of all-or-none
approach. However, SROA might slighly win in stack size, as it tries to figure 
out a stretch of memory tightenly cover the area accessed by the dynamic index.

 rdar://13174884
 PR15200

llvm-svn: 178912
2013-04-05 21:07:08 +00:00
Akira Hatanaka fac2db4a3d [mips] XFAIL test-interp-vec-loadstore.ll in an attempt to turn builder
llvm-mips-linux green.

llvm-mips-linux runs on a big endian machine. This test passes if I change 'e'
to 'E' in the target data layout string.

llvm-svn: 178910
2013-04-05 20:54:46 +00:00
Douglas Gregor 0cb6846090 <rdar://problem/13551789> Fix a race in the LockFileManager.
It's possible for the lock file to disappear and the owning process to
return before we're able to see the generated file. Spin for a little
while to see if it shows up before failing. 

llvm-svn: 178909
2013-04-05 20:53:57 +00:00
Douglas Gregor 6bd4d8cf72 <rdar://problem/13551789> Fix yet another race in unique_file.
If the directory that will contain the unique file doesn't exist when
we tried to create the file, but another process creates it before we
get a chance to try creating it, we would bail out rather than try to
create the unique file.

llvm-svn: 178908
2013-04-05 20:48:36 +00:00
Michael J. Spencer b8055cbc9d [Support][FileSystem] Fix identify_magic for big endian ELF.
llvm-svn: 178905
2013-04-05 20:10:04 +00:00
Rafael Espindola 3add3e9c4a Move yaml2obj to tools too.
llvm-svn: 178904
2013-04-05 20:00:35 +00:00
Rafael Espindola 4386fa9948 Define versions of Section that are explicitly marked as little endian.
These should really be templated like ELF, but this is a start.

llvm-svn: 178896
2013-04-05 18:45:28 +00:00
Michael Gottesman bab49e976b Added two debug logging messages to VisitInstructionsTopDown to match VisitInstructionsBottomUp.
llvm-svn: 178895
2013-04-05 18:26:08 +00:00
Rafael Espindola 8622f2c14e Don't use InMemoryStruct in getSection and getSection64.
llvm-svn: 178894
2013-04-05 18:18:19 +00:00
Michael Gottesman 89279f8383 Cleaned up whitespace and made debug logging less verbose.
llvm-svn: 178893
2013-04-05 18:10:41 +00:00
Timur Iskhodzhanov dcf44ca4f8 Make the test/CodeGen/X86/win32_sret.ll reliable on any CPU by explicitly specifying the -mcpu
llvm-svn: 178885
2013-04-05 17:05:56 +00:00
Renato Golin 91de828f46 Reverting 178851 as it broke buildbots
llvm-svn: 178883
2013-04-05 16:39:53 +00:00
Chad Rosier 4a7005e976 [ms-inline asm] Add support for numeric displacement expressions in bracketed
memory operands.

Essentially, this layers an infix calculator on top of the parsing state
machine.  The scale on the index register is still expected to be an immediate

 __asm mov eax, [eax + ebx*4]

and will not work with more complex expressions.  For example,

 __asm mov eax, [eax + ebx*(2*2)]

The plus and minus binary operators assume the numeric value of a register is
zero so as to not change the displacement.  Register operands should never
be an operand for a multiply or divide operation; the scale*indexreg
expression is always replaced with a zero on the operand stack to prevent
such a case.
rdar://13521380

llvm-svn: 178881
2013-04-05 16:28:55 +00:00
Reid Kleckner bd39f21336 [Support] Disable assertion dialogs from the MSVC debug CRT
Summary:
Sets a report hook that emulates pressing "retry" in the "abort, retry,
ignore" dialog box that _CrtDbgReport normally raises.  There are many
other ways to disable assertion reports, but this was the only way I
could find that still calls our exception handler.

Reviewers: Bigcheese

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D625

llvm-svn: 178880
2013-04-05 16:18:03 +00:00
Rafael Espindola da37835a8d Use ScalarBitSetTraits.
What was missing was were the type strong operator|.

llvm-svn: 178879
2013-04-05 16:00:31 +00:00
Rafael Espindola 601b6d4e33 Fix include guards to match new location.
llvm-svn: 178877
2013-04-05 15:31:16 +00:00
Rafael Espindola b0f76a4b75 Don't fetch pointers from a InMemoryStruct.
InMemoryStruct is extremely dangerous as it returns data from an internal
buffer when the endiannes doesn't match. This should fix the tests on big
endian hosts.

llvm-svn: 178875
2013-04-05 15:15:22 +00:00
Jyotsna Verma b1180dc6d9 Enable JIT/MCJIT unit tests for targets with JIT support.
Change unittests/ExecutionEngine/Makefile to include Makefile.config before
TARGET_HAS_JIT flag is checked.

Fixes bug: http://llvm.org/bugs/show_bug.cgi?id=15669

llvm-svn: 178871
2013-04-05 14:26:16 +00:00
Ulrich Weigand 78e9765b19 Respect Addend when processing MCJIT relocations to local/global symbols.
When the RuntimeDyldELF::processRelocationRef routine finds the target
symbol of a relocation in the local or global symbol table, it performs
a section-relative relocation:

    Value.SectionID = lsi->second.first;
    Value.Addend = lsi->second.second;

At this point, however, any Addend that might have been specified in
the original relocation record is lost.  This is somewhat difficult to
trigger for relocations within the code section since they usually
do not contain non-zero Addends (when built with the default JIT code
model, in any case).  However, the problem can be reliably triggered
by a relocation within the data section caused by code like:

 int test[2] = { -1, 0 };
 int *p = &test[1];

The initializer of "p" will need a relocation to "test + 4".  On
platforms using RelA relocations this means an Addend of 4 is required.
Current code ignores this addend when processing the relocation,
resulting in incorrect execution.

Fixed by taking the Addend into account when processing relocations
to symbols found in the local or global symbol table.

Tested on x86_64-linux and powerpc64-linux.

llvm-svn: 178869
2013-04-05 13:29:04 +00:00
Alexey Samsonov d2069321e0 llvm-symbolizer: correctly parse filenames given in quotes
llvm-svn: 178859
2013-04-05 09:22:24 +00:00
Alexey Samsonov c6ee5835d6 Add a basic test for llvm-symbolizer tool
llvm-svn: 178858
2013-04-05 08:30:13 +00:00
Stepan Dyatkovskiy 6b53a2f50a Buildbot fix for r178851: mistake was in wrong TargetRegisterInfo::getRegClass usage.
llvm-svn: 178854
2013-04-05 07:34:08 +00:00
Alexey Samsonov 3eb78ec974 Add obj2yaml to test dependencies
llvm-svn: 178852
2013-04-05 07:26:37 +00:00
Stepan Dyatkovskiy b309b3b33e Fix for PR14824: "Optimization arm_ldst_opt inserts newly generated instruction vldmia at incorrect position".
Patch introduces memory operands tracking in ARMLoadStoreOpt::LoadStoreMultipleOpti. For each register it keeps the order of load operations as it was before optimization pass.
It is kind of deep improvement of fix proposed by Hao: http://llvm.org/bugs/show_bug.cgi?id=14824#c4
But it also tracks conflicts between different register classes (e.g. D2 and S5).
For more details see:
Bug description: http://llvm.org/bugs/show_bug.cgi?id=14824
LLVM Commits discussion: 
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130311/167936.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130318/168688.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130325/169376.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130401/170238.html

llvm-svn: 178851
2013-04-05 05:52:14 +00:00
Hal Finkel 1a958cf30d Add a SchedMachineModel for the PPC G5
llvm-svn: 178850
2013-04-05 05:49:18 +00:00
Rafael Espindola 4e1e3e75b6 The ppc bots say this is the last broken line, so lets try one more :-(
llvm-svn: 178849
2013-04-05 05:36:37 +00:00
Hal Finkel 5fde1b033e Add a SchedMachineModel for the PPC A2
llvm-svn: 178848
2013-04-05 05:34:08 +00:00
Rafael Espindola 1218a40c92 One more try before I just delete the macho bits until tomorrow.
llvm-svn: 178847
2013-04-05 05:15:39 +00:00
Hal Finkel e6f48e4e2f Fix bug in PEI's virtual-register scavenging
This change fixes a bug that I introduced in r178058. After a register is
scavenged using one of the available spills slots the instruction defining the
virtual register needs to be moved to after the spill code. The scavenger has
already processed the defining instruction so that registers killed by that
instruction are available for definition in that same instruction. Unfortunately,
after this, the scavenger needs to iterate through the spill code and then
visit, again, the instruction that defines the now-scavenged register. In order
to avoid confusion, the register scavenger needs the ability to 'back up'
through the spill code so that it can again process the instructions in the
appropriate order. Prior to this fix, once the scavenger reached the
just-moved instruction, it would assert if it killed any registers because,
having already processed the instruction, it believed they were undefined.

Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar
for diagnosing the problem and testing this fix.

llvm-svn: 178845
2013-04-05 05:01:13 +00:00
Arnold Schwaighofer fb6b9f48d0 ARM scheduler model: Add scheduler info to more instructions and resource
descriptions for compares

llvm-svn: 178844
2013-04-05 05:01:06 +00:00
Rafael Espindola 531efab615 More test loosening.
Sorry for so many commits, but llvm is still building on my ppc vm.

llvm-svn: 178843
2013-04-05 04:54:42 +00:00
Arnold Schwaighofer 5dde1f39c1 ARM scheduler model: Swift has varying latencies, uops for simple ALU ops
llvm-svn: 178842
2013-04-05 04:42:00 +00:00
Rafael Espindola 61ad74938d Loosen this test too.
llvm-svn: 178841
2013-04-05 04:37:55 +00:00
Rafael Espindola b080267bff Loosen this test.
Looks like there is a big endian/little endian problem here. Loosen the
test to try to get the bots green while llvm builds on a ppc qemu vm.

The failure was in http://lab.llvm.org:8011/builders/clang-ppc64-elf-linux2/

llvm-svn: 178839
2013-04-05 04:31:09 +00:00
Rafael Espindola 87a0290941 Move obj2yaml to tools to sort out make's dependencies.
llvm-svn: 178835
2013-04-05 02:57:22 +00:00
Rafael Espindola 726c8c3bdd Build obj2yaml with configure+make.
llvm-svn: 178833
2013-04-05 02:24:51 +00:00
Rafael Espindola 599e810ae3 Add a test for obj2yaml in preparation for refactoring it.
llvm-svn: 178829
2013-04-05 02:02:05 +00:00
Jakob Stoklund Olesen 45a1157233 Clean up some confusing language, and use more realistic examples.
llvm-svn: 178828
2013-04-05 01:25:41 +00:00
Andrew Trick 80e66ce0b4 RegisterPressure heuristics currently require signed comparisons.
llvm-svn: 178823
2013-04-05 00:31:34 +00:00
Andrew Trick 96ce3848d6 Disable DFSResult for ConvergingScheduler.
For now, just save the compile time since the ConvergingScheduler
heuristics don't use this analysis. We'll probably enable it later
after compile-time investigation.

llvm-svn: 178822
2013-04-05 00:31:31 +00:00