Commit Graph

356702 Commits

Author SHA1 Message Date
Xing GUO e4344e1466 [DWARFYAML][debug_ranges] Emit an error message for invalid offset.
This patch helps make yaml2obj emit an error message when we try to assign an invalid offset to the entry of the 'debug_ranges' section.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D81357
2020-06-09 18:53:38 +08:00
Sam McCall 658af94350 [clangd] Parse std::make_unique, and emit template diagnostics at expansion.
Summary:
Parsing std::make_unique is an exception to the usual non-parsing of function
bodies in the preamble. (A hook is added to PreambleCallbacks to allow this).
This allows us to diagnose make_unique<Foo>(wrong arg list), and opens the door
to providing signature help (by detecting where the arg list is forwarded to).
This function is trivial (checked libc++ and libstdc++) and doesn't result in
any extra templates being instantiated, so this should be cheap.

This uncovered a second issue (already visible with class templates)...

Errors produced by template instantiation have primary locations within the
template, with instantiation stack reported as notes.
For templates defined in headers, these end up reported at the #include
directive, which isn't terribly helpful as the header itself is probably fine.
This patch reports them at the instantiation site (the first location in the
instantiation stack that's in the main file). This in turn required a bit of
refactoring in Diagnostics so we can delay relocating the diagnostic until all
notes are available.

https://github.com/clangd/clangd/issues/412

Reviewers: hokein, aaron.ballman

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D81351
2020-06-09 12:47:27 +02:00
Guillaume Chatelet 800e100588 Revert "[Alignment][NFC] Migrate TargetLowering::allowsMemoryAccess"
This reverts commit f21c52667e.
2020-06-09 10:43:59 +00:00
Simon Wallis 4dba59689d [ARM] prologue instructions emitted for naked function with >64 byte argument
Summary:

The naked function attribute is meant to suppress all function
prologue/epilogue instructions.

On ARM, some are still emitted if an argument greater than 64 bytes in size
(the threshold for using the byval attribute in IR) is passed partially
in registers.

Perform the check for Attribute::Naked and early exit in
SelectionDAGISel::LowerArguments().

Checking in ARMFrameLowering::determineCalleeSaves() is too late.

A test case is included.

Reviewers: llvm-commits, olista01, danielkiss

Reviewed By: danielkiss

Subscribers: kristof.beyls, hiraditya, danielkiss

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80715

Change-Id: Icedecf2a4ad31bc3c35ab0df7489a9d346e1f7cc
2020-06-09 11:33:03 +01:00
Guillaume Chatelet 3b6196c9b3 [Alignment][NFC] TargetLowering::allowsMisalignedMemoryAccesses
Summary:
Note to downstream target maintainers: this might silently change the semantics of your code if you override `TargetLowering::allowsMisalignedMemoryAccesses` without marking it override.

This patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81374
2020-06-09 10:17:42 +00:00
Guillaume Chatelet f21c52667e [Alignment][NFC] Migrate TargetLowering::allowsMemoryAccess
Summary:
Note to downstream target maintainers: this might silently change the semantics of your code if you override `TargetLowering::allowsMemoryAccess` without marking it override.

This patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81379
2020-06-09 10:11:07 +00:00
Adam Balogh 5419a31215 [Analyzer] Allow creation of stack frame for functions without definition
Retrieving the parameter location of functions was disabled because it
may causes crashes due to the fact that functions may have multiple
declarations and without definition it is difficult to ensure that
always the same declration is used. Now parameters are stored in
`ParamRegions` which are independent of the declaration of the function,
therefore the same parameters always have the same regions,
independently of the function declaration used actually. This allows us
to remove the limitation described above.

Differential Revision: https://reviews.llvm.org/D80286
2020-06-09 12:08:57 +02:00
Adam Balogh 98db1f990f [Analyzer] [NFC] Parameter Regions
Currently, parameters of functions without their definition present cannot
be represented as regions because it would be difficult to ensure that the
same declaration is used in every case. To overcome this, we split
`VarRegion` to two subclasses: `NonParamVarRegion` and `ParamVarRegion`.
The latter does not store the `Decl` of the parameter variable. Instead it
stores the index of the parameter which enables retrieving the actual
`Decl` every time using the function declaration of the stack frame. To
achieve this we also removed storing of `Decl` from `DeclRegion` and made
`getDecl()` pure virtual. The individual `Decl`s are stored in the
appropriate subclasses, such as `FieldRegion`, `ObjCIvarRegion` and the
newly introduced `NonParamVarRegion`.

Differential Revision: https://reviews.llvm.org/D80522
2020-06-09 12:08:56 +02:00
Adam Balogh 813734dad7 [Analyzer] Add `getReturnValueUnderConstruction()` to `CallEvent`
Checkers should be able to get the return value under construction for a
`CallEvenet`. This patch adds a function to achieve this which retrieves
the return value from the construction context of the call.

Differential Revision: https://reviews.llvm.org/D80366
2020-06-09 12:08:56 +02:00
Pavel Labath 17798c60bc [lldb] Fix -Wmissing-field-initializers in StackFrameList
The code is correct without these default values, but it is freaking the
compiler out.
2020-06-09 11:58:08 +02:00
Abbas Sabra 29353e69d2 [analyzer] LoopWidening: fix crash by avoiding aliased references invalidation
Summary: LoopWidening is invalidating references coming from type
aliases which lead to a crash.

Patch by Abbas Sabra!

Differential Revision: https://reviews.llvm.org/D80669
2020-06-09 12:55:54 +03:00
Jonathan Coe 7117066bd6 [clang-format] Brace breaking for C# lambdas
Reviewers: krasimir, MyDeveloperDay

Reviewed By: krasimir

Subscribers: cfe-commits

Tags: #clang-format, #clang

Differential Revision: https://reviews.llvm.org/D81394
2020-06-09 10:20:01 +01:00
Florian Hahn 3323a628ec [Matrix] Add __builtin_matrix_transpose to Clang.
This patch add __builtin_matrix_transpose to Clang, as described in
clang/docs/MatrixTypes.rst.

Reviewers: rjmccall, jfb, rsmith, Bigcheese

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D72778
2020-06-09 10:14:37 +01:00
Cullen Rhodes 91855483f3 [AArch64][AsmParser] Fix debug output in a few instructions
Summary:
In the parsing of BTIHint, PSBHint and Prefetch the identifier token
should be lexed after creating the operand, otherwise the StringRef is
moved before being copied and the debug output is incorrect.

Prefetch example:

    $ echo "prfm   pldl1keep, [x2]" | ./bin/llvm-mc \
        -triple aarch64-none-linux-gnu -show-encoding -debug

    Before:

      Matching formal operand class MCK_Prefetch against actual operand at
      index 1 (<prfop ,>): match success using generic matcher

    After:

      Matching formal operand class MCK_Prefetch against actual operand at
      index 1 (<prfop pldl1keep>): match success using generic matcher

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D80620
2020-06-09 09:02:59 +00:00
James Henderson 5777570d24 [DebugInfo] Check for errors when reading data for extended opcode
Previously, if an extended opcode was truncated, it would manifest as an
"unexpected line op length error" which wasn't quite accurate. This
change checks for errors any time data is read whilst parsing an
extended opcode, and reports any errors detected.

Reviewed by: MaskRay, labath, aprantl

Differential Revision: https://reviews.llvm.org/D80797
2020-06-09 09:56:37 +01:00
Guillaume Chatelet e26ed6bdae Fix unused variable warning 2020-06-09 08:56:05 +00:00
Cullen Rhodes b82be5db71 [AArch64][SVE] Implement structured load intrinsics
Summary:
This patch adds initial support for the following instrinsics:

    * llvm.aarch64.sve.ld2
    * llvm.aarch64.sve.ld3
    * llvm.aarch64.sve.ld4

For loading two, three and four vectors worth of data. Basic codegen is
implemented with reg+reg and reg+imm addressing modes being addressed
in a later patch.

The types returned by these intrinsics have a number of elements that is a
multiple of the elements in a 128-bit vector for a given type and N, where N is
the number of vectors being loaded, i.e. 2, 3 or 4. Thus, for 32-bit elements
the types are:

    LD2 : <vscale x 8 x i32>
    LD3 : <vscale x 12 x i32>
    LD4 : <vscale x 16 x i32>

This is implemented with target-specific intrinsics for each variant that take
the same operands as the IR intrinsic but return N values, where the type of
each value is a full vector, i.e. <vscale x 4 x i32> in the above example.
These values are then concatenated using the standard concat_vector intrinsic
to maintain type legality with the IR.

These intrinsics are intended for use in the Arm C Language
Extension (ACLE).

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D75751
2020-06-09 08:51:58 +00:00
Kazushi (Jam) Marukawa e9eafb7be9 [VE] Support Transfer Control Instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
transfer control instructions.  Add FENCEI/FENCEM/FENCEC/SVOB instructions
also.  Add new instruction format to represent FENCE* instructions too.

Differential Revision: https://reviews.llvm.org/D81440
2020-06-09 10:41:42 +02:00
hsmahesha 40a632a335 [AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size
Summary:
Make use of both the - (1) clustered bytes and (2) cluster length, to decide on
the max number of mem ops that can be clustered. On an average, when loads
are dword or smaller, consider `5` as max threshold, otherwise `4`. This heuristic
is purely based on different experimentation conducted, and there is no analytical
logic here.

Reviewers: foad, rampitec, arsenm, vpykhtin

Reviewed By: foad, rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, Anastasia, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81085
2020-06-09 14:09:14 +05:30
Kazushi (Jam) Marukawa 0d989cb6ab [VE] Support lowering to NND instruction
Summary:
Support NND instruction of Aurora VE.  Add hasAndNot function also
for optimization.

Differential Revision: https://reviews.llvm.org/D81383
2020-06-09 10:18:14 +02:00
Simon Wallis 0645c4d34f [AVR][test] Remove test for naked function containing a return.
Summary:
Remove an old test for an explicit return in a naked function from test/CodeGen/AVR/return.ll

clang no longer allows a C return in a naked function.

This test is causing failure of the patch https://reviews.llvm.org/D80715

Reviewers: llvm-commits, dylanmckay

Reviewed By: dylanmckay

Subscribers: Jim

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81099

Change-Id: Id218027e520247ae480b92e7801a660fbe0cf29b
2020-06-09 09:06:47 +01:00
Guillaume Chatelet 49dd8e7991 [Alignment] Fix deprecation message 2020-06-09 08:05:13 +00:00
Sameer Sahasrabuddhe d8f651d3e8 [AMDGPU] Enable structurizer workarounds by default
Reviewed By: nhaehnle

Differential Revision: https://reviews.llvm.org/D81211
2020-06-09 13:14:15 +05:30
Kang Zhang 1b6602275d [MachineVerifier] Add TiedOpsRewritten flag to fix verify two-address error
Summary:
Currently, MachineVerifier will attempt to verify that tied operands
satisfy register constraints as soon as the function is no longer in
SSA form. However, PHIElimination will take the function out of SSA
form while TwoAddressInstructionPass will actually rewrite tied operands
to match the constraints. PHIElimination runs first in the pipeline.
Therefore, whenever the MachineVerifier is run after PHIElimination,
it will encounter verification errors on any tied operands.

This patch adds a function property called TiedOpsRewritten that will be
set by TwoAddressInstructionPass and will control when the verifier checks
tied operands.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D80538
2020-06-09 07:39:42 +00:00
Kristof Beyls 09d098506b [AArch64] Fix branch, terminator, etc properties for BRA* instructions.
Tests relying on some of these fixes will be added for this in follow-on
patches that introduce new features that require these properties to be
correct.

Differential Revision: https://reviews.llvm.org/D81399
2020-06-09 08:19:41 +01:00
David Sherwood cc8872400c [CodeGen] Ensure callers of CreateStackTemporary use sensible alignments
In two instances of CreateStackTemporary we are sometimes promoting
alignments beyond the stack alignment. I have introduced a new function
called getReducedAlign that will return the alignment for the broken
down parts of illegal vector types. For example, on NEON a <32 x i8>
type is made up of two <16 x i8> types - in this case the sensible
alignment is 16 bytes, not 32.

In the legalization code wherever we create stack temporaries I have
started using the reduced alignments instead for illegal vector types.

I added a test to

  CodeGen/AArch64/build-one-lane.ll

that tries to insert an element into an illegal fixed vector type
that involves creating a temporary stack object.

Differential Revision: https://reviews.llvm.org/D80370
2020-06-09 08:10:17 +01:00
Sam Parker 37289615c0 [NFCI][CostModel] Unify getCmpSelInstrCost
Add cases for icmp, fcmp and select into the switch statement of the
generic getUserCost implementation with getInstructionThroughput then
calling into it. The BasicTTI and backend implementations have be set
to return a default value (1) when a cost other than throughput is
being queried.

Differential Revision: https://reviews.llvm.org/D80550
2020-06-09 07:41:22 +01:00
David Sherwood 30dfbf03a2 [CodeGen,AArch64] Fix up warnings in splitStores
The code for trying to split up stores is designed for NEON vectors,
where we support arbitrary alignments. It's an optimisation designed
to improve performance by using smaller, aligned stores. However,
we currently only support 16 byte alignments for SVE vectors anyway
so we may as well bail out early.

This change fixes up remaining warnings in a couple of tests:

  CodeGen/AArch64/sve-callbyref-notailcall.ll
  CodeGen/AArch64/sve-calling-convention-byref.ll

Differential Revision: https://reviews.llvm.org/D80720
2020-06-09 07:39:38 +01:00
Stanislav Mekhanoshin 295d1fe733 [AMDGPU] Custom lowering of i64 umulo/smulo
Differential Revision: https://reviews.llvm.org/D81430
2020-06-08 23:14:19 -07:00
Craig Topper bc2b70982b [X86] Autogenerate complete checks and add encoding information. NFC
I think we're using an inefficient CMP encoding for absolute
symbols that would fit in an 8-bit value. This is a pattern
priority issue in isel.
2020-06-08 22:27:20 -07:00
Siva Chandra Reddy 11eafdb1d9 [libc][NFC] Add few more missing entrypoints to the entrypoint list.
They were likely missed while rebasing.
2020-06-08 22:08:42 -07:00
Siva Chandra Reddy 63bbddf4cd [libc][NFC] Add bzero to list of entrypoints.
A new LLVM libc specific extension standard spec has been added.
2020-06-08 21:44:39 -07:00
Kang Zhang e3546c78ca [NFC][PowerPC] Remove the redundant InstAlias for OR instruction
Summary:
We have handle the InstAlias for OR instructions, but we handle it
agagin in PPCInstPrinter.cpp.
This patch is to Remove the redundant InstAlias for OR instruction.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D80502
2020-06-09 03:32:27 +00:00
Saleem Abdulrasool 5fda192fed test: repair lld builder
Add the explicit `-arch x86_64` to the invocation.
2020-06-08 20:13:54 -07:00
Chen Zheng 8aa52b19a7 [APInt] set all bits for getBitsSetWithWrap if loBit == hiBit
differentiate getBitsSetWithWrap & getBitsSet when loBit == hiBit
getBitsSetWithWrap sets all bits;
getBitsSet does nothing.

Reviewed By: lkail, RKSimon, lebedev.ri

Differential Revision: https://reviews.llvm.org/D81325
2020-06-08 22:55:24 -04:00
Anil Mahmud 246d106094 [PowerPC] Fix pattern for DCBFL/DCBFLP instrinsics.
The previous implementation used "asm parser only" pseudo-instructions in their
output patterns. Those are not meant to emit code and will caused crashes when
built with -filetype=obj.

Differential Revision: https://reviews.llvm.org/D80151
2020-06-08 20:54:59 -05:00
Anil Mahmud c9790d54f8 [PowerPC] Remove extra instruction left by emitRLDICWhenLoweringJumpTables
The function emitRLDICWhenLoweringJumpTables in PPCMIPeephole.cpp
was supposed to convert a pair of RLDICL and RLDICR to a single RLDIC,
but it was leaving out the RLDICL instruction. This PR fixes the bug.

Differential Revision: https://reviews.llvm.org/D78063
2020-06-08 20:43:56 -05:00
Stefan Pintilie b4036329f1 [PowerPC] Fix incorrect PC Relative relocations for Big Endian
Fix the incorrect PC Relative relocations for Big Endian for 34 bit offsets.
The offset should be zero for both BE and LE in this situation.

Differential Revision: https://reviews.llvm.org/D81033
2020-06-08 20:29:43 -05:00
Matt Arsenault 3c67b9516a Make myself code owner of InferAddressSpaces
The original author isn't active, and I've made most of the commits to
it.
2020-06-08 21:26:01 -04:00
Saleem Abdulrasool 6fe27b5fed lld: initial pass at supporting TBD
Add support to lld to use Text Based API stubs for linking.  This is
support is incomplete not filtering out platforms.  It also does not
account for architecture specific API handling and potentially does not
correctly handle trees of re-exports with inlined libraries being
treated as direct children of the top level library.
2020-06-08 18:15:40 -07:00
Jacques Pienaar 48c28d58c6 [mlir] Unranked memref type has no rank
Summary:
UnrankedMemRefType doesn't have a rank but previously this was just
checking for unranked tensor. Avoids failure later if one queries the shape
post checking if ranked.

Differential Revision: https://reviews.llvm.org/D81441
2020-06-08 18:08:14 -07:00
Jian Cai 0e1accd0f7 [AArch64] Support expression results as immediate values in mov
Summary:
This patch adds support of using the result of an expression as an
immediate value. For example,

0:
.skip 4
 1:
mov x0, 1b - 0b

is assembled to

mov x0, #4

Currently it does not support expressions requiring relocation unless
explicitly specified. This fixes PR#45781.

Reviewers: peter.smith, ostannard, efriedma

Reviewed By: efriedma

Subscribers: nickdesaulniers, llozano, manojgupta, efriedma, ostannard, kristof.beyls, hiraditya, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80028
2020-06-08 17:57:20 -07:00
dfukalov 6a31a9a543 [AMDGPU][NFC] Skip processing intrinsics that do not become real instructions
Reviewers: rampitec

Reviewed By: rampitec

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81260
2020-06-09 03:45:33 +03:00
Siva Chandra Reddy e9de9e3368 [libc][NFC][Obvious] Add names to various string entrypoints. 2020-06-08 17:13:53 -07:00
Eli Friedman 7e58d0ded0 Revert "[arm][darwin] Don't generate libcalls for wide shifts on Darwin"
This reverts commit 2ba016cd5c.

This is causing a failure on the clang-cmake-armv7-full bot, and there
are outstanding review comments.
2020-06-08 16:37:29 -07:00
Petr Hosek 69c5ff4668 [InstrProfiling] Use -fuse-ld=lld in instrprof-gc-sections test
This was accidentally omitted in 603d58b leading to a test failure
on some of the bots that don't use lld as the default linker.
2020-06-08 16:36:14 -07:00
George Mitenkov fda5192d4f [MLIR][SPIRVToLLVM] Add skeleton for SPIR-V to LLVM dialect conversion
These commits set up the skeleton for SPIR-V to LLVM dialect conversion.
I created SPIR-V to LLVM pass, registered it in Passes.td, InitAllPasses.h.
Added a pattern for `spv.BitwiseAndOp` and tests for it. Integer, float
and vector types are converted through LLVMTypeConverter.

Differential Revision: https://reviews.llvm.org/D81100
2020-06-08 18:22:42 -04:00
KareemErgawy a6d6b0ac93 [MLIR][Toy] Fix a few typos in the comments/docs.
Fixes a few typos and errors in MLIR's Toy tutorial docs and comments.

Differential Revision: https://reviews.llvm.org/D81406
2020-06-08 18:18:47 -04:00
Petr Hosek 603d58b5e4 [InstrProfiling] Use !associated metadata for counters, data and values
The !associated metadata may be attached to a global object declaration
with a single argument that references another global object. This
metadata prevents discarding of the global object in linker GC unless
the referenced object is also discarded.

Furthermore, when a function symbol is discarded by the linker, setting
up !associated metadata allows linker to discard counters, data and
values associated with that function symbol. This is not possible today
because there's metadata to guide the linker. This approach is also used
by other instrumentations like sanitizers.

Note that !associated metadata is only supported by ELF, it does not have
any effect on non-ELF targets.

Differential Revision: https://reviews.llvm.org/D76802
2020-06-08 15:07:43 -07:00
Petr Hosek ba10bedf56 Revert "[InstrProfiling] Use !associated metadata for counters, data and values"
This reverts commit 39b3c41b65 due to
a failing associated.ll test.
2020-06-08 14:38:15 -07:00