0cd0fbd8c5
[X86] Remove system/control schedule itineraries (PR37093)
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llvm-svn: 329903
2018-04-12 12:09:24 +00:00
a13271bcba
[X86][VMX] Tag VMX instructions scheduler classes
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Tagged all as system instructions
llvm-svn: 320053
2017-12-07 15:57:32 +00:00
8d5a246ebe
[X86] Change VMPTRST to use PS instead of TB to match VMPTRLD.
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llvm-svn: 316340
2017-10-23 16:22:40 +00:00
62d1c71676
[X86] Added missing mayLoad/mayStore attributes to some X86 instructions.
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Throughout the effort of automatically generating the X86 memory folding tables these missing information were encountered.
This is a preparation work for a future patch including the automation of these tables.
Differential Revision: https://reviews.llvm.org/D31714
llvm-svn: 300190
2017-04-13 10:03:45 +00:00
c494718050
[X86] Change instructions names to keep consistency with the naming convention. NFC
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Differential Revision: https://reviews.llvm.org/D31743
llvm-svn: 300184
2017-04-13 09:12:32 +00:00
955308fbee
[X86] Remove many operands that represent memory stores from outs to ins. These operands are the registers and immediates that specify the memory address not the memory itself thus they are inputs.
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llvm-svn: 263354
2016-03-13 02:56:31 +00:00
5ccb61781f
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler.
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llvm-svn: 201538
2014-02-18 00:21:49 +00:00
ae11aed9d7
Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode.
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This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.
llvm-svn: 199193
2014-01-14 07:41:20 +00:00
c0a5aaeab0
[x86] Rename In32BitMode predicate to Not64BitMode
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That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)
Patch by David Woodhouse
llvm-svn: 197768
2013-12-20 02:04:49 +00:00
3d8fc90f96
*fixed to separate mnemonic from operands with tab
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llvm-svn: 158543
2012-06-15 21:04:21 +00:00
66a3597a4a
Add vmfunc instruction to X86 assembler and disassembler.
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llvm-svn: 150899
2012-02-19 01:39:49 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
29ba4f97e6
Fix asm string wrt variants.
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llvm-svn: 147805
2012-01-09 21:32:02 +00:00
0ae8d4d738
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
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llvm-svn: 142117
2011-10-16 07:05:40 +00:00
d07a59f288
Fix disassembling of INVEPT and INVVPID to take operands
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llvm-svn: 140955
2011-10-01 21:20:14 +00:00
52d3935dfe
move VMX instructions out to their own file.
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llvm-svn: 115597
2010-10-05 06:06:53 +00:00
Simon Pilgrim