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34 Commits

Author SHA1 Message Date
Jim Grosbach a3fcb962eb Consolidate ARM NOP encoding test. 
llvm-svn: 135600
 2011-07-20 18:39:38 +00:00
Jim Grosbach 614e90a126 ARM parsing and encoding tests for MVN 
llvm-svn: 135599
 2011-07-20 18:37:08 +00:00
Jim Grosbach 8d11490771 ARM assembly parsing of MUL instruction. 
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.

llvm-svn: 135596
 2011-07-20 18:20:31 +00:00
Jim Grosbach d25c2cdad7 Tweak ARM assembly parsing and printing of MSR instruction. 
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.

llvm-svn: 135532
 2011-07-19 22:45:10 +00:00
Jim Grosbach 97094d8f06 ARM assembly parsing of MRS instruction. 
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.

llvm-svn: 135527
 2011-07-19 21:59:29 +00:00
Jim Grosbach b17d9b12a6 Move mr[r]c[2] ARM tests and tidy up a bit. 
llvm-svn: 135517
 2011-07-19 20:28:56 +00:00
Jim Grosbach 69721dce67 ARM testcases for MOVT. 
llvm-svn: 135516
 2011-07-19 20:23:25 +00:00
Jim Grosbach 5cc3b4cd9a ARM assembly parsing for MOV (register). 
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.

llvm-svn: 135513
 2011-07-19 20:10:31 +00:00
Jim Grosbach 7c09e3c3f3 ARM assembly parsing for MOV (immediate). 
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.

llvm-svn: 135500
 2011-07-19 19:13:28 +00:00
Jim Grosbach 51849920f1 Add some testcases for ARM MLA/MLS instructions. 
llvm-svn: 135196
 2011-07-14 21:43:05 +00:00
Jim Grosbach 26e7449443 ARM MCRR/MCRR2 immediate operand range checking. 
llvm-svn: 135192
 2011-07-14 21:26:42 +00:00
Jim Grosbach d37d2025e9 ARM MCR/MCR2 assembly parsing operand constraints. 
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.

llvm-svn: 135189
 2011-07-14 21:19:17 +00:00
Jim Grosbach 2f9aeeef3b Update ARM Assembly of LDM/STM. 
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.

llvm-svn: 135168
 2011-07-14 18:35:38 +00:00
Jim Grosbach d616cf3497 ARM ISB assembly parsing tests. 
llvm-svn: 135158
 2011-07-14 18:02:25 +00:00
Jim Grosbach e6f8b1fac6 ARM tests for EOR instruction parsing and encoding. 
llvm-svn: 135119
 2011-07-14 00:22:21 +00:00
Jim Grosbach a0958d7abf ARM Assembler support for DSB instruction. 
Add instalias for default 'sy' option. Add tests.

llvm-svn: 135116
 2011-07-14 00:18:13 +00:00
Jim Grosbach 44c3f08e85 ARM Assembler support for DMB instruction. 
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

llvm-svn: 135109
 2011-07-13 23:40:38 +00:00
Jim Grosbach 507ba77465 ARM Assembler support for DBG instruction. 
Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102
 2011-07-13 22:59:38 +00:00
Jim Grosbach 307de01867 ARM parsing and encoding tests for CMN/CMP. 
llvm-svn: 135098
 2011-07-13 22:26:58 +00:00
Jim Grosbach 9559d360e5 Shuffle ARM assembly tests a bit. 
llvm-svn: 135095
 2011-07-13 22:19:10 +00:00
Jim Grosbach 31756c2283 Range checking for CDP[2] immediates. 
llvm-svn: 135092
 2011-07-13 22:01:08 +00:00
Jim Grosbach ec8989115d Testcases for ARM assembly BX/BXJ instructions. 
llvm-svn: 135078
 2011-07-13 20:25:46 +00:00
Jim Grosbach 2371a3f14a Testcases for ARM assembly BLX/BL instructions. 
llvm-svn: 135072
 2011-07-13 20:11:04 +00:00
Jim Grosbach 975b641ee8 Range checking for 16-bit immediates in ARM assembly. 
llvm-svn: 135071
 2011-07-13 20:10:10 +00:00
Jim Grosbach c845e55374 Add tests for ARM parsing of 'BKPT' instruction. 
llvm-svn: 135063
 2011-07-13 19:17:36 +00:00
Jim Grosbach 43b45e2790 Fix copy-pasto. 
llvm-svn: 135062
 2011-07-13 19:16:30 +00:00
Jim Grosbach 4f0f2ac757 Add tests for ARM parsing of 'BIC' instruction. 
llvm-svn: 135061
 2011-07-13 19:12:32 +00:00
Jim Grosbach 6cfb1573bf Add some FIXMEs. 
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.

llvm-svn: 135060
 2011-07-13 19:10:23 +00:00
Jim Grosbach b7cdd8772c Add tests for ARM parsing of 'AND' instruction. 
llvm-svn: 135056
 2011-07-13 18:55:14 +00:00
Jim Grosbach 61a9f2af9e Add tests for ARM parsing of 'ADD' instruction 
llvm-svn: 135053
 2011-07-13 18:12:46 +00:00
Jim Grosbach 04afb071e1 Destination register operand is optional for ADC and SBC ARM. 
llvm-svn: 135052
 2011-07-13 17:57:17 +00:00
Jim Grosbach 7dcd1354f1 Flesh out ARM Parser support for shifted-register operands. 
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.

llvm-svn: 135049
 2011-07-13 17:50:29 +00:00
Jim Grosbach 992a2856f5 Add check for predicate w/o S bit. 
llvm-svn: 134987
 2011-07-12 16:25:04 +00:00
Jim Grosbach a9a3f0a414 Fix recognition of ARM 'adcs' mnemonic. 
The 'CS' is not a predication suffix in this case.

llvm-svn: 134903
 2011-07-11 17:09:57 +00:00