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77 Commits

Author SHA1 Message Date
Richard Osborne f1b800998a Add intrinsics for the zext / sext instructions. 
llvm-svn: 135476
 2011-07-19 13:28:50 +00:00
Richard Osborne 252c43ee88 Add intrinsics for the testct, testwct instructions. 
llvm-svn: 135475
 2011-07-19 13:00:40 +00:00
Richard Osborne 707f0beae1 Add intrinsics for the peek and endin instructions. 
llvm-svn: 135474
 2011-07-19 12:50:25 +00:00
Chris Lattner 5756c16cdf make the asmparser reject function and type redefinitions. 'Merging' hasn't been 
needed since llvm-gcc 3.4 days.

llvm-svn: 133248
 2011-06-17 07:06:44 +00:00
Richard Osborne 2f14b0bb1d Add XCore intrinsic for crc8. 
llvm-svn: 132340
 2011-05-31 16:24:49 +00:00
Richard Osborne 542f9a2bcf Add XCore intrinsic for crc32. 
llvm-svn: 132336
 2011-05-31 14:47:36 +00:00
Richard Osborne 36d027f7f6 Convert test to FileCheck. 
llvm-svn: 132335
 2011-05-31 14:00:05 +00:00
Jakob Stoklund Olesen d3b2f44c9d Fix register-dependent XCore tests 
llvm-svn: 130816
 2011-05-04 01:01:41 +00:00
Jakob Stoklund Olesen f4c9754d5c Fix Mips, Sparc, and XCore tests that were dependent on register allocation. 
Add an extra run with -regalloc=basic to keep them honest.

llvm-svn: 128654
 2011-03-31 18:42:43 +00:00
Richard Osborne 9a827b30ab Add XCore intrinsics for initializing / starting / synchronizing threads. 
llvm-svn: 128633
 2011-03-31 15:13:13 +00:00
Richard Osborne 6120962d7d Add XCore intrinsic for setpsc. 
llvm-svn: 127821
 2011-03-17 18:42:05 +00:00
Richard Osborne c871eff3f5 Add XCore intrinsics for setclk, setrdy. 
llvm-svn: 127761
 2011-03-16 21:56:00 +00:00
Richard Osborne d4346f2388 Add checkevent intrinsic to check if any resources owned by the current thread 
can event.

llvm-svn: 127741
 2011-03-16 18:34:00 +00:00
Richard Osborne 5f1a26ea39 On the XCore the scavenging slot should be closest to the SP. 
llvm-svn: 127680
 2011-03-15 15:10:11 +00:00
Richard Osborne 3a68eb150b Add XCore intrinsics for getps, setps, setsr and clrsr. 
llvm-svn: 127678
 2011-03-15 13:45:47 +00:00
Benjamin Kramer 1885d21700 Fix mistyped CHECK lines. 
llvm-svn: 127366
 2011-03-09 22:07:31 +00:00
Joerg Sonnenberger 62f759791a Be nice to Xcore and the XMOS assembler and avoid quoting section names 
that contain only letters, digits and the characters "_" and ".".

llvm-svn: 127028
 2011-03-04 20:03:14 +00:00
Joerg Sonnenberger 852ab890b5 Bug#9033: For the ELF assembler output, always quote the section name. 
llvm-svn: 126963
 2011-03-03 22:31:08 +00:00
Richard Osborne 42f52e737e Add XCore intrinsic for eeu instruction. 
llvm-svn: 126384
 2011-02-24 13:39:18 +00:00
Richard Osborne bfa5cc0e08 Add XCore intrinsic for clre instruction. 
llvm-svn: 126322
 2011-02-23 18:52:05 +00:00
Richard Osborne 4995b05f56 Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable 
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.

llvm-svn: 126320
 2011-02-23 18:35:59 +00:00
Richard Osborne 2c610aa3ed Add XCore intrinsic for the setv instruction. 
llvm-svn: 126315
 2011-02-23 16:46:37 +00:00
Richard Osborne aab96995f6 Add XCore intrinsic for settw instruction. 
llvm-svn: 126313
 2011-02-23 14:45:03 +00:00
Richard Osborne 1ae65c7cb8 Add XCore intrinsics for various instructions on ports. 
llvm-svn: 126132
 2011-02-21 18:23:30 +00:00
Richard Osborne d9dde78c27 Add intrinsic for setc instruction on the XCore. 
llvm-svn: 125186
 2011-02-09 13:22:12 +00:00
Richard Osborne a31b9c2f7c Add XCore intrinsics for resource instructions. 
llvm-svn: 124794
 2011-02-03 13:14:25 +00:00
Richard Osborne 8607a67d37 Add support for trampolines on the XCore. 
llvm-svn: 124722
 2011-02-02 14:57:41 +00:00
Richard Osborne 272e084bca Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions. 
llvm-svn: 124587
 2011-01-31 17:41:44 +00:00
Rafael Espindola ec517cdf24 Update tests. 
llvm-svn: 123591
 2011-01-16 18:02:57 +00:00
Devang Patel c24048a718 If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0. 
llvm-svn: 121059
 2010-12-06 22:39:26 +00:00
Evan Cheng f3e9a48584 Enable machine sinking critical edge splitting. e.g. 
define double @foo(double %x, double %y, i1 %c) nounwind {
  %a = fdiv double %x, 3.2
  %z = select i1 %c, double %a, double %y
  ret double %z
}

Was:
_foo:
        divsd   LCPI0_0(%rip), %xmm0
        testb   $1, %dil
        jne     LBB0_2
        movaps  %xmm1, %xmm0
LBB0_2:
        ret

Now:
_foo:
        testb   $1, %dil
        je      LBB0_2
        divsd   LCPI0_0(%rip), %xmm0
        ret
LBB0_2:
        movaps  %xmm1, %xmm0
        ret

This avoids the divsd when early exit is taken.
rdar://8454886

llvm-svn: 114372
 2010-09-20 22:52:00 +00:00
Dan Gohman 4fee6f3bdd Start function numbering at 0. 
llvm-svn: 101638
 2010-04-17 16:29:15 +00:00
Dale Johannesen f118f9788b Split big test into multiple directories to cater to 
those who don't build all targets.

llvm-svn: 100688
 2010-04-07 20:43:35 +00:00
Chris Lattner 9efbbcbe45 fix AsmPrinter::GetBlockAddressSymbol to always return a unique 
label instead of trying to form one based on the BB name (which
causes collisions if the name is empty).  This fixes PR6608

llvm-svn: 98495
 2010-03-14 17:53:23 +00:00
Richard Osborne 4780109254 Add dag combine to simplify lmul(x, 0, a, b) 
llvm-svn: 98258
 2010-03-11 16:26:35 +00:00
Richard Osborne 54a2c32670 Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit 
expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.

llvm-svn: 98168
 2010-03-10 18:12:27 +00:00
Richard Osborne 1a396d53ed Fold add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if the intermediate 
results are unused elsewhere.

llvm-svn: 98157
 2010-03-10 16:19:31 +00:00
Richard Osborne f57aea3d38 Prefer LMUL to MACCU as LMUL has no tied operands. 
llvm-svn: 98153
 2010-03-10 13:27:10 +00:00
Richard Osborne 0012bc1e41 Custom lower (S|U)MUL_LOHI -> MACC(S|U) 
llvm-svn: 98152
 2010-03-10 13:20:07 +00:00
Richard Osborne 54dfa01adc Lower add (mul a, b), c into MACCU / MACCS nodes which translate 
directly to the maccu / maccs instructions. We handle this in
ExpandADDSUB since after type legalisation it is messy to
recognise these operations.

llvm-svn: 98150
 2010-03-10 11:41:08 +00:00
Richard Osborne e35eabdd69 Convert test to FileCheck. 
llvm-svn: 98148
 2010-03-10 11:24:03 +00:00
Richard Osborne c420c4cb4e In cases where the carry / borrow unused converted ladd / lsub 
to an add or a sub.

llvm-svn: 98059
 2010-03-09 16:34:25 +00:00
Richard Osborne f4e76cf44d Add DAG combine for ladd / lsub. 
llvm-svn: 98057
 2010-03-09 16:07:47 +00:00
Richard Osborne 333300e0df Fix XCoreTargetLowering::isLegalAddressingMode() to handle VoidTy. 
Previously LoopStrengthReduce would sometimes be unable to find
a legal formula, causing an assertion failure.

llvm-svn: 97226
 2010-02-26 16:44:51 +00:00
Richard Osborne f578196968 Lower BR_JT on the XCore to a jump into a series of jump instructions. 
llvm-svn: 96942
 2010-02-23 13:25:07 +00:00
Chris Lattner cc9a6f0580 convert the last 3 targets to use EmitFunctionBody() now that 
it has before/end body hooks.

 lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp |   49 ++-----------
 lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp   |   87 ++++++------------------
 lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp |   56 +++------------
 test/CodeGen/XCore/ashr.ll                      |    2 
 4 files changed, 48 insertions(+), 146 deletions(-)

llvm-svn: 94741
 2010-01-28 06:22:43 +00:00
Dan Gohman fb4193625a Delete useless trailing semicolons. 
llvm-svn: 92740
 2010-01-05 17:55:26 +00:00
Richard Osborne 3bd09434a6 Add XCore support for indirectbr / blockaddress. 
llvm-svn: 89273
 2009-11-18 23:20:42 +00:00
Richard Osborne d5f2745965 Add XCore support for arbitrary-sized aggregate returns. 
llvm-svn: 88802
 2009-11-14 19:33:35 +00:00
Richard Osborne 4e13316bf9 Add some peepholes for signed comparisons using ashr X, X, 32. 
llvm-svn: 83549
 2009-10-08 15:38:17 +00:00