b389f2a04d
Revert previous change to a comment. The BlockAddresses go in the
...
constant pool so they don't get wrapped separately.
llvm-svn: 85844
2009-11-03 00:02:05 +00:00
1c66e8a6b7
Put BlockAddresses into ARM constant pools.
...
llvm-svn: 85824
2009-11-02 20:59:23 +00:00
d9dfc2e752
Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should
...
have been passed as a reference.
llvm-svn: 85823
2009-11-02 20:14:39 +00:00
5ac6f244fd
Fix schedule model for BFC.
...
llvm-svn: 85809
2009-11-02 17:28:36 +00:00
4c00a524eb
Hyphenate some comments.
...
llvm-svn: 85808
2009-11-02 17:10:37 +00:00
433ab09ca3
Add support for BlockAddress values in ARM constant pools.
...
llvm-svn: 85806
2009-11-02 16:59:06 +00:00
e90a4aa703
Prune unnecessary include.
...
llvm-svn: 85805
2009-11-02 16:58:31 +00:00
115cfc07d5
These are done / no longer care.
...
llvm-svn: 85798
2009-11-02 07:58:25 +00:00
f6f1b37f9f
Add an entry.
...
llvm-svn: 85797
2009-11-02 07:51:19 +00:00
1708b06c0e
Unbreak ARMBaseRegisterInfo::copyRegToReg.
...
llvm-svn: 85787
2009-11-02 04:44:55 +00:00
4d23754b14
Handle splats of undefs properly. This includes the testcase for PR5364 as well.
...
llvm-svn: 85767
2009-11-02 00:12:06 +00:00
0f38d989bd
Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
...
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
2009-11-02 00:11:39 +00:00
8cce1eb6aa
64-bit FP loads & stores operate on both NEON and VFP pipelines.
...
llvm-svn: 85765
2009-11-02 00:11:06 +00:00
14635da94b
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
...
llvm-svn: 85764
2009-11-02 00:10:38 +00:00
1a4492be97
Fix a couple more places where we are creating ld / st instructions without memoperands.
...
llvm-svn: 85746
2009-11-01 22:04:35 +00:00
43219997b6
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
...
llvm-svn: 85743
2009-11-01 21:12:51 +00:00
50ba5c3dc2
improve x86 codegen support for blockaddress. We now compile
...
the testcase into:
_test1: ## @test1
## BB#0: ## %entry
leaq L_test1_bb6(%rip), %rax
jmpq *%rax
L_test1_bb: ## Address Taken
LBB1_1: ## %bb
movb $1, %al
ret
L_test1_bb6: ## Address Taken
LBB1_2: ## %bb6
movb $2, %al
ret
Note, it is very very strange that BlockAddressSDNode doesn't carry
around TargetFlags. Dan, please fix this.
llvm-svn: 85703
2009-11-01 03:25:03 +00:00
6f29ad9170
Use cbz and cbnz instructions.
...
llvm-svn: 85698
2009-10-31 23:46:45 +00:00
5cba8de2c8
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
...
them for scalar floating point operations for now.
llvm-svn: 85697
2009-10-31 22:57:36 +00:00
8fe6fd702d
Expand 64-bit logical shift right inline
...
llvm-svn: 85687
2009-10-31 21:42:19 +00:00
624fcb286e
Expand 64-bit arithmetic shift right inline
...
llvm-svn: 85685
2009-10-31 21:00:56 +00:00
5d994048dd
Expand 64 bit left shift inline rather than using the libcall. For now, this
...
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.
llvm-svn: 85675
2009-10-31 19:38:01 +00:00
cdbb70c065
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
...
llvm-svn: 85643
2009-10-31 03:39:36 +00:00
8be42bd09f
Updates to the ARM target assembler for llvm-mc per review comments from
...
Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand. And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.
llvm-svn: 85632
2009-10-30 22:55:57 +00:00
c7415bf536
Add a note about Robert Muth's alternate jump table implementation.
...
llvm-svn: 85624
2009-10-30 22:22:46 +00:00
49fa51d936
Fix MachineLICM to use the correct virtual register class when
...
unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.
llvm-svn: 85622
2009-10-30 22:18:41 +00:00
6b00f4b7a8
Fix a comment.
...
llvm-svn: 85610
2009-10-30 20:13:25 +00:00
ab7c709f43
This fixes functions like
...
void f (int a1, int a2, int a3, int a4, int a5,...)
In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.
llvm-svn: 85590
2009-10-30 14:33:14 +00:00
1cf0b03064
Add ARM codegen for indirect branches.
...
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
f7c4299312
Initial x86 support for BlockAddresses.
...
llvm-svn: 85557
2009-10-30 01:28:02 +00:00
8578068302
Dial back the realignment a bit.
...
llvm-svn: 85546
2009-10-30 00:08:40 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
...
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
b352d76480
To get more thorough testing from llc-beta nightly runs, do dynamic stack
...
realignment regardless of whether it's strictly necessary.
llvm-svn: 85476
2009-10-29 02:41:21 +00:00
97b9312663
Revert r85346 change to control tail merging by CodeGenOpt::Level.
...
I'm going to redo this using the OptimizeForSize function attribute.
llvm-svn: 85426
2009-10-28 20:46:46 +00:00
73789b848d
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
...
opcode and operand with a tab. Check for these instructions in the usual
places.
llvm-svn: 85411
2009-10-28 18:26:41 +00:00
6203c6868f
fconsts and fconstd are obviously re-materializable.
...
llvm-svn: 85410
2009-10-28 18:19:56 +00:00
294aea709e
Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.
...
llvm-svn: 85406
2009-10-28 17:33:28 +00:00
ec6d7c945d
Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.
...
llvm-svn: 85381
2009-10-28 06:55:03 +00:00
f64db3e1d0
X86 palignr intrinsics immediate field is in bits. ISel must transform it into bytes.
...
llvm-svn: 85379
2009-10-28 06:30:34 +00:00
a91a563530
Previously, all operands to Constant were themselves constant.
...
In the new world order, BlockAddress can have a BasicBlock operand.
This doesn't permute much, because if you have a ConstantExpr (or
anything more specific than Constant) we still know the operand has
to be a Constant.
llvm-svn: 85375
2009-10-28 05:14:34 +00:00
4a609f3cef
Use fconsts and fconstd to materialize small fp constants.
...
llvm-svn: 85362
2009-10-28 01:44:26 +00:00
83896a59e1
Add a second ValueType argument to isFPImmLegal.
...
llvm-svn: 85361
2009-10-28 01:43:28 +00:00
9c6bc1f563
Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides
...
eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.
This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.
llvm-svn: 85357
2009-10-28 00:55:57 +00:00
e4b80c9bee
Add an indirect branch pattern for ARM. Testcase will be coming soon.
...
llvm-svn: 85355
2009-10-28 00:37:03 +00:00
d04cb6d0fa
rename indbr -> indirectbr to appease the residents of #llvm.
...
llvm-svn: 85351
2009-10-28 00:19:10 +00:00
9693f9d465
Record CodeGen optimization level in the BranchFolding pass so that we can
...
use it to control tail merging when there is a tradeoff between performance
and code size. When there is only 1 instruction in the common tail, we have
been merging. That can be good for code size but is a definite loss for
performance. Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3". Radar 7338114.
Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level. Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor. If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.
llvm-svn: 85346
2009-10-27 23:49:38 +00:00
2e5198ff09
Add new note.
...
llvm-svn: 85341
2009-10-27 23:30:07 +00:00
5607d2cb54
Enable virtual register based frame index scavenging by default for ARM & T2.
...
llvm-svn: 85335
2009-10-27 22:52:29 +00:00
fd2730ee8c
Move and clarify note.
...
llvm-svn: 85334
2009-10-27 22:48:31 +00:00
c1403a0024
Infrastructure for dynamic stack realignment on ARM. For now, this is off by
...
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.
llvm-svn: 85333
2009-10-27 22:45:39 +00:00
2974f63cb5
Note corrected.
...
llvm-svn: 85332
2009-10-27 22:43:24 +00:00
cd4d148040
Modify note.
...
llvm-svn: 85331
2009-10-27 22:40:45 +00:00
a205402c16
Add a note.
...
llvm-svn: 85329
2009-10-27 22:34:43 +00:00
e8628a0206
cppbackend support for indbr
...
llvm-svn: 85312
2009-10-27 21:24:48 +00:00
42c979e8d3
CBE support for indbr.
...
llvm-svn: 85311
2009-10-27 21:21:06 +00:00
cde65ec581
Similar to r85280, do not clear the "S" bit for RSBri and RSBrs.
...
llvm-svn: 85299
2009-10-27 20:51:49 +00:00
4f36affe5f
Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between
...
BL_pred and BLr9_pred.
llvm-svn: 85297
2009-10-27 20:45:15 +00:00
16993aa30b
Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.
...
llvm-svn: 85281
2009-10-27 19:56:55 +00:00
b5044ce5a9
Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI"
...
instruction format that already takes care of setting this.
llvm-svn: 85280
2009-10-27 19:52:03 +00:00
df5dcdaa10
Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10})
...
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.
llvm-svn: 85271
2009-10-27 18:44:24 +00:00
a789f17ffc
Remove unnecessary gotos to fall-thru successors.
...
llvm-svn: 85257
2009-10-27 17:40:24 +00:00
b678a56fef
Test commit. Added '.' to the comment line.
...
llvm-svn: 85255
2009-10-27 17:25:15 +00:00
fb22a85baf
apparently the X86 JIT isn't fully contextized, it is still using getGlobalContext() :(
...
llvm-svn: 85252
2009-10-27 17:01:03 +00:00
d90d169f9d
Correctly align double arguments in the stack.
...
llvm-svn: 85235
2009-10-27 14:09:44 +00:00
538984c1c3
Now VFP instructions.
...
llvm-svn: 85186
2009-10-27 00:20:49 +00:00
b02bdb4552
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
...
llvm-svn: 85184
2009-10-27 00:08:59 +00:00
13edef55b6
Change ARM asm strings to separate opcode from operands with a tab instead of a space.
...
llvm-svn: 85178
2009-10-26 23:45:59 +00:00
de5ad42aa1
Remove FreeInst.
...
Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.
llvm-svn: 85176
2009-10-26 23:43:48 +00:00
a33fa47141
Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding
...
bits. Johnny, please review -- I do not have a good track record of getting
these right.
llvm-svn: 85173
2009-10-26 22:59:12 +00:00
1de6a1f7d2
Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class.
...
Patch by Johnny Chen.
llvm-svn: 85169
2009-10-26 22:42:13 +00:00
a6aba77e0a
Add more ARM instruction encodings for 's' bit set and "rs" register encoding
...
bits. Patch by Johnny Chen.
llvm-svn: 85167
2009-10-26 22:34:44 +00:00
ce8f626f82
Update CMake files.
...
llvm-svn: 85161
2009-10-26 22:06:01 +00:00
0ae1b2961d
Revert r85134, it breaks mingw build
...
llvm-svn: 85138
2009-10-26 18:40:24 +00:00
752aea6513
Make PIC16 overlay a loadable pass.
...
llvm-svn: 85134
2009-10-26 18:22:59 +00:00
8370485db9
Break anti-dependence breaking out into its own class.
...
llvm-svn: 85127
2009-10-26 16:59:04 +00:00
56869f22c4
Move DataTypes.h to include/llvm/System, update all users. This breaks the last
...
direct inclusion edge from System to Support.
llvm-svn: 85086
2009-10-26 01:35:46 +00:00
5bde1cbd93
of -> or
...
llvm-svn: 85065
2009-10-25 19:14:48 +00:00
5a9788b979
80-column cleanup
...
llvm-svn: 85064
2009-10-25 18:55:46 +00:00
b18a46806b
Reapply 85006 with a minor fix.
...
llvm-svn: 85052
2009-10-25 08:14:11 +00:00
2e7dee5f23
Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.
...
llvm-svn: 85049
2009-10-25 07:53:28 +00:00
5d1b849658
Don't forget subreg indices when folding load / store.
...
llvm-svn: 85048
2009-10-25 07:52:27 +00:00
974e12b2d3
Remove includes of Support/Compiler.h that are no longer needed after the
...
VISIBILITY_HIDDEN removal.
llvm-svn: 85043
2009-10-25 06:57:41 +00:00
02d5f77d26
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
...
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
llvm-svn: 85042
2009-10-25 06:33:48 +00:00
13b8b56dd4
this is done.
...
llvm-svn: 85041
2009-10-25 06:17:51 +00:00
54d7179a25
Remove ICmpInst::isSignedPredicate which was a reimplementation
...
CmpInst::isSigned.
llvm-svn: 85037
2009-10-25 05:20:17 +00:00
9e8d42f295
Revert back 85006 for now as it breaks PIC16 tests.
...
llvm-svn: 85008
2009-10-24 18:19:41 +00:00
055c3305a1
Adding support for placing global objects in shared data memory.
...
llvm-svn: 85006
2009-10-24 18:02:44 +00:00
46ed1f8341
80 col violation.
...
llvm-svn: 84986
2009-10-24 02:07:42 +00:00
e2871d69db
Restrict Thumb1 register allocation to low registers, even for instructions that
...
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.
llvm-svn: 84982
2009-10-24 00:19:24 +00:00
22b2c011f9
FIXME no longer applies. R12 and R3 are available for allocation
...
llvm-svn: 84977
2009-10-23 23:07:42 +00:00
851193b873
some stuff is done, we still have constantexpr simplification to do.
...
llvm-svn: 84943
2009-10-23 07:00:55 +00:00
8b86efefec
X86 needs critical path anti-dependency breaking.
...
llvm-svn: 84931
2009-10-23 05:57:35 +00:00
02ad4cb32e
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
...
llvm-svn: 84911
2009-10-22 23:19:17 +00:00
9d763cc3f8
Revert 84843. Evan, this was breaking some of the if-conversion tests.
...
llvm-svn: 84868
2009-10-22 16:52:21 +00:00
c77f8634e5
Shift art to the right to keep GCC from complaining about multi-line comments.
...
llvm-svn: 84849
2009-10-22 09:28:49 +00:00
3615b9bef3
Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.
...
llvm-svn: 84843
2009-10-22 06:48:32 +00:00
943f4f41f2
Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.
...
llvm-svn: 84842
2009-10-22 06:47:35 +00:00
5457a96b63
Trim more includes.
...
llvm-svn: 84832
2009-10-22 05:11:00 +00:00
344fcd9d61
Trim include.
...
llvm-svn: 84831
2009-10-22 05:08:49 +00:00
1448799377
fix warning.
...
llvm-svn: 84826
2009-10-22 03:42:27 +00:00
0f55e9ce2e
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
...
llvm-svn: 84813
2009-10-22 00:40:00 +00:00
f1ad2c618a
Use special DAG-to-DAG preprocessing to allow mem-mem instructions to be selected.
...
Yay for ASCII graphics!
llvm-svn: 84808
2009-10-22 00:16:00 +00:00
f2e74df12e
Missing piece of the ARM frame index post-scavenging conditionalization
...
llvm-svn: 84798
2009-10-21 23:40:56 +00:00
05536f50dc
Conditionalize ARM/T2 frame index post-scavenging while working out fixes
...
for a few bugs.
llvm-svn: 84791
2009-10-21 22:59:24 +00:00
854530a7dd
Most of the NEON shuffle instructions do not support 64-bit element types.
...
llvm-svn: 84785
2009-10-21 21:36:27 +00:00
b45d621ab1
Revert r84764, it breaks mingw build
...
llvm-svn: 84783
2009-10-21 21:15:18 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
...
immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
9e92857b38
Add DAG printing for RMW stuff debugging
...
llvm-svn: 84776
2009-10-21 19:18:28 +00:00
ccfa3e31f7
RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them.
...
llvm-svn: 84775
2009-10-21 19:17:55 +00:00
5399c2d05e
Implement branch folding
...
llvm-svn: 84774
2009-10-21 19:17:18 +00:00
2983dcb1f2
Cosmetic changes, no functionality changes
...
llvm-svn: 84773
2009-10-21 19:16:49 +00:00
0db964a3a0
Fix NEON VST2LN instruction encoding.
...
Patch by Johnny Chen.
llvm-svn: 84767
2009-10-21 17:54:01 +00:00
87671da29a
Revert 84732. It was the wrong fix.
...
llvm-svn: 84766
2009-10-21 17:52:34 +00:00
c5804f3cb6
Build shared lib instead of an archive.
...
llvm-svn: 84764
2009-10-21 17:27:23 +00:00
47ea743618
Add a pass to overlay pic16 data sections for function frame and automatic
...
variables. This pass can be invoked by llvm-ld or opt to traverse over the call graph
to detect what function frames and their automatic variables can be overlaid.
Currently this builds an archive , but needs to be changed to a loadable module.
llvm-svn: 84753
2009-10-21 10:42:44 +00:00
786b15fe12
Match more patterns to movt.
...
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
175d04c90f
tidy
...
llvm-svn: 84738
2009-10-21 04:10:24 +00:00
5b5cb92816
Fix some more NEON instruction encoding problems.
...
Thanks to Johnny Chen for discovering the problem.
llvm-svn: 84732
2009-10-21 02:27:20 +00:00
bd3650cc84
Leave some NEON instruction encoding bits unspecified instead of setting
...
a default value of zero. This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.
llvm-svn: 84730
2009-10-21 02:15:46 +00:00
bc69313909
IPSCCP is missing stuff.
...
llvm-svn: 84725
2009-10-21 01:10:37 +00:00
7099d0c19c
Add note
...
llvm-svn: 84713
2009-10-21 00:14:15 +00:00
e43af4a085
Be crazy and assert in case of unsupported modifier passed.
...
llvm-svn: 84712
2009-10-21 00:13:58 +00:00
11074fa73e
Handle external symbols
...
llvm-svn: 84711
2009-10-21 00:13:42 +00:00
cc55b9086d
Distinguish between pcrel imm operands and 'normal' ones. Fix fixes gross weirdness of asmprinting.
...
llvm-svn: 84710
2009-10-21 00:13:25 +00:00
94ba9c27b0
Add basic block operands & jump kinds
...
llvm-svn: 84709
2009-10-21 00:13:05 +00:00
8a06a4e5c8
Ignore all implicit reg operands
...
llvm-svn: 84708
2009-10-21 00:12:44 +00:00
196b0e5431
Add a workaround for different memops prefixes
...
llvm-svn: 84707
2009-10-21 00:12:27 +00:00
4e32bff382
Checkpoint MCInst printer. We (almostly) able to print global / JT / constpool entries
...
llvm-svn: 84706
2009-10-21 00:12:08 +00:00
7fbc0a50d5
Add simple operand printing stuff
...
llvm-svn: 84704
2009-10-21 00:11:27 +00:00
6e78029d82
Add experimental MSP430 MCInstLowering stuff
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llvm-svn: 84703
2009-10-21 00:11:08 +00:00
daaa2f0c31
Wire up MSP430 printMCInst() method
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llvm-svn: 84702
2009-10-21 00:10:47 +00:00
b6e2e4fd50
Add MSP430 InstPrinter stub
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llvm-svn: 84701
2009-10-21 00:10:30 +00:00
13de81ac40
Use proper target data
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llvm-svn: 84700
2009-10-21 00:10:00 +00:00
a470eac6a1
Fix -Asserts warning.
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llvm-svn: 84687
2009-10-20 22:10:05 +00:00
cccf5084a3
Disable by default while debugging
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llvm-svn: 84669
2009-10-20 20:31:31 +00:00
f3a2b6499e
add cmd line opt to disable frame index reuse for ARM and T2. debug aid.
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llvm-svn: 84664
2009-10-20 20:19:50 +00:00
3d9d78463c
Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too.
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llvm-svn: 84652
2009-10-20 18:14:49 +00:00
4a43e3068d
Make TranslateX86CC return COND_INVALID instead of aborting when it
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encounters an OEQ or UNE comparison, and update its callers to check
for this return status and recover. This fixes a problem resulting from
the LowerOperation hooks being called from LegalizeVectorOps, because
LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may
still be at large. This fixes PR5092.
llvm-svn: 84640
2009-10-20 16:22:37 +00:00
3301207a15
Random #include pruning.
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llvm-svn: 84632
2009-10-20 11:44:38 +00:00
8296e62244
This file is replaeced by PIC16Section.h.
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llvm-svn: 84628
2009-10-20 09:16:32 +00:00
9351e4f4b2
implement some more easy hooks.
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llvm-svn: 84614
2009-10-20 06:22:33 +00:00
60d5131653
Implement some hooks, make printOperand abort if unknown modifiers are
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present.
llvm-svn: 84613
2009-10-20 06:15:28 +00:00
227767b4e5
t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass.
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llvm-svn: 84611
2009-10-20 05:58:02 +00:00
f0b3d15cfe
Wire up the ARM MCInst printer, for llvm-mc.
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llvm-svn: 84600
2009-10-20 05:15:36 +00:00
34f040a575
Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*
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functions are not needed.
llvm-svn: 84587
2009-10-20 01:32:47 +00:00
84f6235b6f
Enable post-pass frame index register scavenging for ARM and Thumb2
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llvm-svn: 84585
2009-10-20 01:26:58 +00:00
484d2e9491
lower ARM::MOVi32imm properly.
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llvm-svn: 84583
2009-10-20 01:11:37 +00:00
43c5589a7e
add support for external symbols. The mc instprinter can now handle
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reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing
identical output except for superior formatting of constant pool entries.
llvm-svn: 84582
2009-10-20 00:56:16 +00:00
1b06acbd70
get fancy: support basic block operands. Yay for jumps.
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llvm-svn: 84579
2009-10-20 00:52:47 +00:00
85ab670644
add supprort for the 'sbit' operand, MOVi apparently has one.
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llvm-svn: 84577
2009-10-20 00:46:11 +00:00
Bob Wilson