4 Commits

Author	SHA1	Message	Date
Justin Holewinski	3e037d98e6	[NVPTX] Rename registers %fl -> %fd and %rl -> %rd ... This matches the internal behavior of NVIDIA tools like libnvvm. llvm-svn: 213168	2014-07-16 16:26:58 +00:00
Justin Holewinski	dbb3b2f4b6	[NVPTX] Re-enable support for virtual registers in the final output ... Now that 3.3 is branched, we are re-enabling virtual registers to help iron out bugs before the next release. Some of the post-RA passes do not play well with virtual registers, so we disable them for now. The needed functionality of the PrologEpilogInserter pass is copied to a new backend-specific NVPTXPrologEpilog pass. The test for this commit is not breaking the existing tests. llvm-svn: 182998	2013-05-31 12:14:49 +00:00
Justin Holewinski	59fd8ba5f5	[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway. ... llvm-svn: 178417	2013-03-30 14:29:30 +00:00
Justin Holewinski	ae556d3ef7	This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it. ... The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB llvm-svn: 156196	2012-05-04 20:18:50 +00:00