Commit Graph

15 Commits

Author SHA1 Message Date
Sushma Unnibhavi 086370faee [M68k][GloballSel] Lower outgoing return values in IRTranslator
Implementation of lowerReturn in the IRTranslator for the M68k backend.

Differential Revision: https://reviews.llvm.org/D105332
2021-07-05 11:39:09 -07:00
Min-Yih Hsu 557bed31e4 Reapply "[M68k][GloballSel] Formal arguments lowering in IRTranslator"
Implementation of formal arguments lowering in the IRTranslator for the
M68k backend

Differential Revision: https://reviews.llvm.org/D104542
2021-06-30 17:13:45 -07:00
Min-Yih Hsu 04242bdca9 Revert "[M68k][GloballSel] Formal arguments lowering in IRTranslator"
This reverts commit 8f43407a07 due to
failure on its associated test.
2021-06-27 23:22:40 -07:00
Sushma Unnibhavi 8f43407a07 [M68k][GloballSel] Formal arguments lowering in IRTranslator
Implementation of formal arguments lowering in the IRTranslator for the
M68k backend

Differential Revision: https://reviews.llvm.org/D104542
2021-06-27 16:13:05 -07:00
Jim Lin 0365af1a87 [M68k] Add testcases for shift and rotate instructions
Add codegen testcases for lsl, lsr, asr, rol and ror instructions.

Reviewed By: myhsu

Differential Revision: https://reviews.llvm.org/D104685
2021-06-23 13:26:58 +08:00
Jim Lin 5cb5225cf5 [M68k] Refactor codegen patterns for logic operations and add tests for it
Refactor pat for and, or and xor operation and add missing tests for it

Reviewed By: myhsu

Differential Revision: https://reviews.llvm.org/D104626
2021-06-23 13:25:24 +08:00
Sushma Unnibhavi 2193347e72 [M68k][GloballSel] Adding initial GlobalISel infrastructure
Wiring up GlobalISel for the M68k backend

Differential Revision: https://reviews.llvm.org/D101819
2021-06-16 10:48:38 -06:00
Min-Yih Hsu dccf5c7dfb [M68k] Support for inline asm operands w/ simple constraints
This patch adds supports for inline assembly operands and some simple
operand constraints, including register and constant operands.

Differential Revision: https://reviews.llvm.org/D102585
2021-05-20 14:00:09 -07:00
Min-Yih Hsu e620bea211 [M68k] Allow user to preserve certain registers
Add `-ffixed-a[0-6]` and `-ffixed-d[0-7]` and the corresponding
subtarget features to prevent certain register from being allocated.

Differential Revision: https://reviews.llvm.org/D102805
2021-05-20 13:57:22 -07:00
Min-Yih Hsu 5b3dd2a490 [M68k][AsmParser] Fix invalid register name parsing logics
Adjust sanity check in register parsing function to allow register
name with more than 2 characters (e.g. ccr).

Differential Revision: https://reviews.llvm.org/D101733
2021-05-05 17:13:02 -07:00
Min-Yih Hsu abac6023bb [M68k][AsmParser] Support negative integer constants
Parsing negative integer constants as expressions.

Differential Revision: https://reviews.llvm.org/D101732
2021-05-05 17:11:59 -07:00
Min-Yih Hsu 34da083a8c [M68k][test] Initial migration of MC tests
As the context depicted by bug 49865[1], we are migrating tests under
`test/CodeGen/M68k/Encoding`, which was originally used to test
instruction encoding using MIR file as input, into `test/MC/M68k`. We
are also adding test directives for AsmParser using the same set of
inputs.

Currently we are converting the original MIR test files into assembly
code as well as translating the original LIT "RUN" statement into one
that only uses built-in LLVM tools (i.e. Get rid of `extract-section`).

However, since AsmParser has not completely finished, many of these
original test cases fail. Thus, this patch only migrate test files
that are passed by the current implementation of AsmParser (and
MCCodeEmitter). The remaining tests (under test/CodeGen/M68k/Encoding)
will be ported alone with the patch that fixes the related issues.

[1]: https://bugs.llvm.org/show_bug.cgi?id=49865

Differential Revision: https://reviews.llvm.org/D101410
2021-05-05 17:11:35 -07:00
Simon Pilgrim 9d2df96407 [DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling
Reuse the existing KnownBits multiplication code to handle the 'extend + multiply + extract high bits' pattern for multiply-high ops.

Noticed while looking at the codegen for D88785 / D98587 - the patch helps division-by-constant expansion code in particular, which suggests that we might have some further KnownBits div/rem cases we could handle - but this was far easier to implement.

Differential Revision: https://reviews.llvm.org/D98857
2021-03-19 16:02:31 +00:00
Min-Yih Hsu 340d558c77 [M68k] Fixed incorrect `extract-section` command substitution
Fix Bug 49485 (https://bugs.llvm.org/show_bug.cgi?id=49485). Which was
caused by incorrect invocation of `extract-section.py` on Windows.
Replacing it with more general python script invocation.

Differential Revision: https://reviews.llvm.org/D98661
2021-03-16 13:37:50 -07:00
Min-Yih Hsu c23a780c30 [M68k][test](6/8) Add all of the tests
And a small utilities -- extract-section.py -- that helps extracting
specific object file section and printing in textual format. This
utility is just a workaround for tests inside `Encoding`. Hopefully in
the future we can replace dependencies in those tests with existing tools
(e.g. llvm-readobj). Please refer to this bug for more context:
https://bugs.llvm.org/show_bug.cgi?id=49245

Note that since we don't have AsmParser for now, we are testing the MC
part using MIR as input and put those tests under the `Encoding` folder.
In the future when AsmParser (and disassembler) is finished, those tests
will be moved to `test/MC/M68k`.

Authors: myhsu, m4yers, glaubitz

Differential Revision: https://reviews.llvm.org/D88392
2021-03-08 12:30:57 -08:00