Commit Graph

19564 Commits

Author SHA1 Message Date
Stephen Lin e31f2d2d54 SelectionDAG: Fix incorrect condition checks in some cases of folding FADD/FMUL combinations; also improve accuracy of comments
llvm-svn: 183993
2013-06-14 18:17:35 +00:00
Derek Schuff 1804b5795a Make PrologEpilogInserter save/restore all callee saved registers
in functions which call __builtin_unwind_init()

__builtin_unwind_init() is an undocumented gcc intrinsic which has this effect,
and is used in libgcc_eh.

Goes part of the way toward fixing PR8541.

llvm-svn: 183984
2013-06-14 16:15:29 +00:00
Amaury de la Vieuville e804ae1188 ARM: fix thumb coprocessor instruction with pre-writeback disassembly
was        stc2 p0, c0, [r0]!
instead of stc2 p0, c0, [r0,#0]!

llvm-svn: 183975
2013-06-14 11:21:35 +00:00
Benjamin Kramer b289319fb8 X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX equivalent.
Give it the right register format so we can also emit it when AVX is enabled.

llvm-svn: 183971
2013-06-14 09:31:41 +00:00
JF Bastien 18db1f2f1a Enable FastISel on ARM for Linux and NaCl, not MCJIT
This is a resubmit of r182877, which was reverted because it broken
MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only
enabled for iOS. I've CC'ed people from the original review and revert.

FastISel was only enabled for iOS ARM and Thumb2, this patch enables it
for ARM (not Thumb2) on Linux and NaCl, but not MCJIT.

Thumb2 support needs a bit more work, mainly around register class
restrictions.

The patch punts to SelectionDAG when doing TLS relocation on non-Darwin
targets. I will fix this and other FastISel-to-SelectionDAG failures in
a separate patch.

The patch also forces FastISel to retain frame pointers: iOS always
keeps them for backtracking (so emitted code won't change because of
this), but Linux was getting much worse code that was incorrect when
using big frames (such as test-suite's lencod). I'll also fix this in a
later patch, it will probably require a peephole so that FastISel
doesn't rematerialize frame pointers back-to-back.

The test changes are straightforward, similar to:
  http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html
They also add a vararg test that got dropped in that change.

I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0
and all the tests pass. All the tests also pass on x86 make check-all. I
also re-ran the check-all tests that failed on ARM, and they all seem to
pass.

llvm-svn: 183966
2013-06-14 02:49:43 +00:00
Sean Silva 0a409cf04a [yaml2obj] Add support for sh_addralign via `AddressAlign` key.
For consistency, change the address in the test case from 0xDEADBEEF to
0xCAFEBABE since 0xCAFEBABE that actually has a 2-byte alignment.

llvm-svn: 183962
2013-06-14 00:38:02 +00:00
Sean Silva 46dffffb39 [yaml2obj] Add support for specifying raw section content.
llvm-svn: 183955
2013-06-13 22:20:01 +00:00
Sean Silva f4bfcedfe5 [yaml2obj] Add sh_addr via `Address` key.
llvm-svn: 183954
2013-06-13 22:19:54 +00:00
Sean Silva 3820593160 [yaml2obj] Initial ELF section support.
The current functionality is extremely basic and a bit rough around the
edges, but it will flesh out in future commits.

llvm-svn: 183953
2013-06-13 22:19:48 +00:00
Bill Schmidt 4a28e82743 [PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.
This is a preliminary patch for fast instruction selection on
PowerPC.  Code generation can differ between DAG isel and fast isel.
Existing tests that specify -O0 were written to expect DAG isel.  Make
this explicit by adding -fast-isel=false to the tests.

In some cases specifying -fast-isel=false produces different code even
when there isn't a fast instruction selector specified.  This is
because TM.Options.EnableFastISel = 1 at -O0 whether or not a FastISel
object exists.  Thus disabling fast isel can actually produce less
conservative code.  Because of this, some of the expected code
generation in the -O0 tests needs to be adjusted.

In particular, handling of function arguments is less conservative
with -fast-isel=false (see isOnlyUsedInEntryBlock() in
SelectionDAGBuilder.cpp).  This results in fewer stack accesses and,
in some cases, reduced stack size as uselessly loaded values are no
longer stored back to spill locations in the stack.

No functional change with this patch; test case adjustments only.

llvm-svn: 183939
2013-06-13 20:23:34 +00:00
Derek Schuff ec9dc01b33 Fix DeleteDeadVarargs not to crash on functions referenced by BlockAddresses
This pass was assuming that if hasAddressTaken() returns false for a
function, the function's only uses are call sites.  That's not true
because there can be references by BlockAddresses too.

Fix the pass to handle this case.  Fix
BlockAddress::replaceUsesOfWithOnConstant() to allow a function's type
to be changed by RAUW'ing the function with a bitcast of the recreated
function.

Patch by Mark Seaborn.

llvm-svn: 183933
2013-06-13 19:51:17 +00:00
Amaury de la Vieuville bd2b610eba ARM: fix B decoding
llvm-svn: 183914
2013-06-13 16:41:55 +00:00
Amaury de la Vieuville 231ca2bdc3 ARM: fix t2am_imm8_offset operand printing for imm=#-0
llvm-svn: 183913
2013-06-13 16:40:51 +00:00
Benjamin Kramer af6c3b7002 X86: Make the cmov aliases work with intel syntax too.
llvm-svn: 183907
2013-06-13 15:45:24 +00:00
Rui Ueyama 82ebd8e36d readobj: Dump PE/COFF optional records.
These records are mandatory for executables and are used by the loader.

Reviewers: rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D939

llvm-svn: 183852
2013-06-12 19:10:33 +00:00
Rafael Espindola 8d30480344 Always remove an alias when we rename the target.
Should fix the dragonegg build bots.

llvm-svn: 183845
2013-06-12 16:45:47 +00:00
Rafael Espindola fb3fc0bf34 Convert test to FileCheck.
llvm-svn: 183843
2013-06-12 16:35:53 +00:00
Ulrich Weigand 32d725b80a [MC/DWARF] Support .debug_frame / .debug_line code alignment factors
I've been comparing the object file output of LLVM's integrated
assembler against the external assembler on PowerPC, and one
area where differences still remain are in DWARF sections.

In particular, the GNU assembler generates .debug_frame and
.debug_line sections using a code alignment factor of 4, since
all PowerPC instructions have size 4 and must be aligned to a
multiple of 4.  However, current MC code hard-codes a code
alignment factor of 1.

This patch changes this by adding a "minimum instruction alignment"
data element to MCAsmInfo and using this as code alignment factor.

This requires passing a MCContext into MCDwarfLineAddr::Encode
and MCDwarfLineAddr::EncodeAdvanceLoc.  Note that one caller,
MCDwarfLineAddr::Write, didn't actually have that information
available.  However, it turns out that this routine is in fact
never used in the whole code base, so the patch simply removes
it.  If it turns out to be needed again at a later time, it
could be re-added with an updated interface.

llvm-svn: 183834
2013-06-12 14:46:54 +00:00
Ulrich Weigand d45c68cb9c [PowerPC] Use assembler source in MC tests
A couple of old test cases in test/MC/PowerPC were still using
LLVM IR.  Now that we have a working assembler, we can move
them to assembler tests instead:
  ppc64-initial-cfa.ll
  ppc64-relocs-01.ll
  ppc64-tls-relocs-01.ll

llvm-svn: 183829
2013-06-12 14:14:18 +00:00
Sean Silva 81db71ff07 [yaml2obj] Remove fragile test case.
This test case was a "sanity check"/"breathing" test case at first, but
is really fragile, which impairs changes to yaml2obj.

`test/Object/yaml2obj-elf-bits-endian.test` is much more robust and
serves as an adequate sanity check.

llvm-svn: 183811
2013-06-12 00:01:26 +00:00
Akira Hatanaka 5c50a16ee0 [mips] Add an IR transformation pass that optimizes calls to sqrt.
The pass emits a call to sqrt that has attribute "read-none". This call will be
converted to an ISD::FSQRT node during DAG construction, which will turn into
a mips native sqrt instruction.
 

llvm-svn: 183802
2013-06-11 22:21:44 +00:00
Rafael Espindola a82555c0f8 Change how globalopt handles aliases in llvm.used.
Instead of a custom implementation of replaceAllUsesWith, we just call
replaceAllUsesWith and recreate llvm.used and llvm.compiler-used.

This change is particularity interesting because it makes llvm see
through what clang is doing with static used functions in extern "C"
contexts. With this change, running clang -O2 in

extern "C" {
  __attribute__((used)) static void foo() {}
}

produces

@llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @foo to
i8*)], section "llvm.metadata"
define internal void @foo() #0 {
entry:
  ret void
}

llvm-svn: 183756
2013-06-11 17:48:06 +00:00
NAKAMURA Takumi 4d5ee8046f Rework r183728, suppress assert(0) for now. Its behavior depends on assertions on win32 hosts.
FIXME: Introduce yet another checker but assert(0).
llvm-svn: 183736
2013-06-11 10:01:42 +00:00
Mihai Popa c1d119ed6e It adds support for negative zero offsets for loads and stores.
Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value.
Behavior already present for Thumb2.

llvm-svn: 183734
2013-06-11 09:48:35 +00:00
Mihai Popa 1c7be576c5 This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.
llvm-svn: 183733
2013-06-11 09:39:51 +00:00
Amaury de la Vieuville 064546cbfe ARM: Enforce decoding rules for VLDn instructions
llvm-svn: 183731
2013-06-11 08:14:14 +00:00
Amaury de la Vieuville 53ff029d62 ARM: Fix STREX/LDREX reecoding
The decoded MCInst wasn't reencoded as the same instruction

llvm-svn: 183729
2013-06-11 08:03:20 +00:00
NAKAMURA Takumi 1ab3650ec0 Tweak a couple of tests on win32 hosts with +Asserts.
- Don't use assert(0), or tests may pass or fail according to assertions.
  - For now, The tests are marked as XFAIL for win32 hosts.

FIXME: Could we avoid XFAIL to specify triple in the RUN lines?
llvm-svn: 183728
2013-06-11 06:52:58 +00:00
Sean Silva 864dd75093 Fix dubious type name similar to member name.
Should bring bots back to life.

llvm-svn: 183715
2013-06-11 00:13:52 +00:00
Sean Silva f99309cb08 [yaml2obj] Initial ELF support.
Currently, only emitting the ELF header is supported (no sections or
segments).

The ELFYAML code organization is broadly similar to the COFFYAML code.

llvm-svn: 183711
2013-06-10 23:44:15 +00:00
Tim Northover a2292d0b8f ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.
Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some
only support Thumb mode (M-class ones currently). This makes sure such CPUs
default to the correct mode and makes the AsmParser diagnose an attempt to
switch modes incorrectly.

rdar://14024354

llvm-svn: 183710
2013-06-10 23:20:58 +00:00
Tim Northover 6833e3fd75 X86: Stop LEA64_32r doing unspeakable things to its arguments.
Previously LEA64_32r went through virtually the entire backend thinking it was
using 32-bit registers until its blissful illusions were cruelly snatched away
by MCInstLower and 64-bit equivalents were substituted at the last minute.

This patch makes it behave normally, and take 64-bit registers as sources all
the way through. Previous uses (for 32-bit arithmetic) are accommodated via
SUBREG_TO_REG instructions which make the types and classes agree properly.

llvm-svn: 183693
2013-06-10 20:43:49 +00:00
Ulrich Weigand 4c44032aa1 [PowerPC] Support extended sc mnemonic
A plain "sc" without argument is supposed to be treated like "sc 0"
by the assembler.  This patch adds a corresponding alias.

Problem reported by Joerg Sonnenberger.

llvm-svn: 183687
2013-06-10 17:19:43 +00:00
Ulrich Weigand aa4a2d71aa [PowerPC] Support branch mnemonics with implied CR0
The extended branch mnemonics are supposed to use an implied CR0
if there is no explicit condition register specified.  This patch
adds extra variants of the mnemonics to this effect.

Problem reported by Joerg Sonnenberger.

llvm-svn: 183686
2013-06-10 17:19:15 +00:00
Amaury de la Vieuville 43cb13a5c9 ARM: ISB cannot be passed the same options as DMB
ISB should only accepts full system sync, other options are reserved

llvm-svn: 183656
2013-06-10 14:17:08 +00:00
Justin Holewinski b96d1395f6 [NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore and causes constants to be emitted in the global address space
llvm-svn: 183652
2013-06-10 13:29:47 +00:00
JF Bastien c04341bb34 Add test for ARM FastISel load/store register classes
r183624 fixed an issue that was tested indirectly. Test it directly with this new test.

llvm-svn: 183634
2013-06-10 00:35:57 +00:00
Reed Kotler ce510830c5 Fix a regression I introduced when I expanded the complex pseudos in
the Mips16 port. A few of the psuedos could either take signed
or unsigned arguments and I did not distinguish the case and improperly
rejected some valid cases that the assembler had previously accepted
when they were pure pseudos that expanded as assembly instructions.

llvm-svn: 183633
2013-06-09 23:23:46 +00:00
Logan Chien 1bd6e13b70 Refine the ARM EHABI test cases.
Since we have ARM unwind directive parser and assembler, we
can check the correctness in two stages:

1. From LLVM assembly (.ll) to ARM assembly (.s)
2. From ARM assembly (.s) to ELF object file (.o)

We already have several "*.s to *.o" test cases.  This CL adds
some "*.ll to *.s" test cases and removes the redundant "*.ll to *.o"
test cases.

New test cases to check "*.ll to *.s" code generator:

- ehabi.ll: Check the correctness of the generated unwind directives.
- section-name.ll: Check the section name of functions.

Removed test cases:

- ehabi-mc-cantunwind.ll
  (Covered by ehabi-cantunwind.ll, and eh-directive-cantunwind.s)
- ehabi-mc-compact-pr0.ll
  (Covered by ehabi.ll, eh-compact-pr0.s, eh-directive-save.s, and
   eh-directive-setfp.s)
- ehabi-mc-compact-pr1.ll
  (Covered by ehabi.ll, eh-compact-pr1.s, eh-directive-save.s, and
   eh-directive-setfp.s)
- ehabi-mc.ll
  (Covered by ehabi.ll, and eh-directive-integrated-test.s)
- ehabi-mc-section-group.ll
  (Covered by section-name.ll, and eh-directive-section-comdat.s)
- ehabi-mc-section.ll
  (Covered by section-name.ll, and eh-directive-section.s)
- ehabi-mc-sh_link.ll
  (Covered by eh-directive-text-section.s, and eh-directive-section.s)

llvm-svn: 183628
2013-06-09 12:36:57 +00:00
Logan Chien 325823a189 Fix ARM unwind opcode assembler in several cases.
Changes to ARM unwind opcode assembler:

* Fix multiple .save or .vsave directives.  Besides, the
  order is preserved now.

* For the directives which will generate multiple opcodes,
  such as ".save {r0-r11}", the order of the unwind opcode
  is fixed now, i.e. the registers with less encoding value
  are popped first.

* Fix the $sp offset calculation.  Now, we can use the
  .setfp, .pad, .save, and .vsave directives at any order.

Changes to test cases:

* Add test cases to check the order of multiple opcodes
  for the .save directive.

* Fix the incorrect $sp offset in the test case.  The
  stack pointer offset specified in the test case was
  incorrect.  (Changed test cases: ehabi-mc-section.ll and
  ehabi-mc.ll)

* The opcode to restore $sp are slightly reordered.  The
  behavior are not changed, and the new output is same
  as the output of GNU as.  (Changed test cases:
  eh-directive-pad.s and eh-directive-setfp.s)

llvm-svn: 183627
2013-06-09 12:22:30 +00:00
Elena Demikhovsky 89703c06f2 Removed PackedDouble domain from scalar instructions. Added more formats for the scalar stuff.
llvm-svn: 183626
2013-06-09 07:37:10 +00:00
Tim Northover 64280fbba1 Make DeadArgumentElimination more conservative on variadic functions
Variadic functions are particularly fragile in the face of ABI changes, so this
limits how much the pass changes them

llvm-svn: 183625
2013-06-09 02:17:27 +00:00
Venkatraman Govindaraju 7dae9ce021 [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend.
llvm-svn: 183613
2013-06-08 15:32:59 +00:00
Amaury de la Vieuville f4ec0c8510 ARM: fix VMOVvnf32 decoding when ambiguous with VCVT
Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF

llvm-svn: 183612
2013-06-08 13:54:05 +00:00
Amaury de la Vieuville 68bcd021fd ARM: enforce SRS decoding constraints
llvm-svn: 183611
2013-06-08 13:43:59 +00:00
Amaury de la Vieuville 631df63e54 ARM: fix CPS decoding when ambiguous with QADD
Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.

Add some necessary safe guards in CPS decoding as well.

llvm-svn: 183610
2013-06-08 13:38:52 +00:00
Amaury de la Vieuville ea7bb57058 ARM: fix VCVT decoding
UNPRED was reported instead of UNDEF

llvm-svn: 183608
2013-06-08 13:29:11 +00:00
Shuxin Yang 140d592d84 Fix a potential bug in r183584.
r183584 tries to derive some info from the code *AFTER* a call and apply
these derived info to the code *BEFORE* the call, which is not always safe
as the call in question may never return, and in this case, the derived
info is invalid.
  
  Thank Duncan for pointing out this potential bug.

rdar://14073661 

llvm-svn: 183606
2013-06-08 04:56:05 +00:00
Quentin Colombet 249cb6756c Reapply r183552. This time, use a standard type for the option to avoid template
instantiation issue with non-standard type.

Add a backend option to warn on a given stack size limit.
Option: -mllvm -warn-stack-size=<limit>
Output (if limit is exceeded):
warning: Stack size limit exceeded (<actual size>) in <functionName>.

The longer term plan is to hook that to a clang warning.
PR:4072
<rdar://problem/13987214>.

llvm-svn: 183595
2013-06-08 00:07:54 +00:00
Vincent Lejeune 4d143328df R600: Anti dep better handled in tex clause
llvm-svn: 183592
2013-06-07 23:30:26 +00:00