ed721e32cd
[AArch64] Adjust the cost model for Exynos M1 and M2
...
Fix the modeling of some loads and stores.
llvm-svn: 318884
2017-11-22 22:48:50 +00:00
46f672b759
[AArch64] Adjust the cost model for Exynos M1 and M2
...
Fix the modeling of test and branch.
llvm-svn: 318685
2017-11-20 19:11:56 +00:00
4b964f2b95
[AArch64] Adjust the cost model for Exynos M1 and M2
...
Improve the accuracy of the model by specifying the proper number of uops.
llvm-svn: 318531
2017-11-17 16:42:15 +00:00
82665b1ec4
[AArch64] Adjust the cost model for Exynos M1 and M2
...
Fix the modeling of FP stores.
llvm-svn: 318351
2017-11-15 23:49:58 +00:00
cbf70486bc
[AArch64] Adjust the cost model for Exynos M1 and M2
...
Fix the modeling of loads and stores using the pre or post indexed
addressing modes.
llvm-svn: 318312
2017-11-15 17:39:37 +00:00
1c94538693
[AArch64] Adjust the cost model for Exynos M1 and M2
...
Fix the modeling of loads and stores of registers pairs.
llvm-svn: 318186
2017-11-14 19:59:43 +00:00
d825bbdc41
[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.
...
Patch [4/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions.
We add SVE as unsupported feature for CPUs that don't have SVE to prevent errors from scheduler models saying it lacks information for these instructions.
Patch by Sander De Smalen.
Reviewed by: rengolin
Differential Revision: https://reviews.llvm.org/D39090
llvm-svn: 317582
2017-11-07 15:03:11 +00:00
307e039d8c
[AArch64] Adjust the cost model for Exynos M1 and M2
...
Refine the model of FP loads and stores.
llvm-svn: 313555
2017-09-18 19:00:38 +00:00
91650ef061
[AArch64] Adjust the cost model for Exynos M1 and M2
...
Refine the model of loads and stores using the register offset addressing
modes.
llvm-svn: 313554
2017-09-18 19:00:36 +00:00
4976d6a0c6
[AArch64] Adjust the cost model for Exynos M1 and M2
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Add new predicate to more accurately model the scheduling around branches
and function calls and of loads and stores of pairs and integer
multiplications.
llvm-svn: 311944
2017-08-28 22:51:52 +00:00
509516d200
[AArch64] Adjust the cost model for Exynos M1 and M2
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Add new predicate to more accurately model the cost of arithmetic and
logical operations shifted left.
Differential revision: https://reviews.llvm.org/D37151
llvm-svn: 311943
2017-08-28 22:51:32 +00:00
d192a8ae7d
[AArch64] Adjust the cost model for Exynos M1 and M2
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Add the information for the scalar reciprocal square root approximation.
llvm-svn: 309183
2017-07-26 21:28:15 +00:00
29ffb0e66a
[AArch64] Adjust the cost model for Exynos M1 and M2
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Fine tune the resources in a couple of ASIMD loads.
llvm-svn: 308904
2017-07-24 18:06:16 +00:00
55459609c8
[AArch64] Adjust the cost model for Exynos M1 and M2
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Add the cost for the EXT instructions and explicitly add the cost for a few
instructions that were implied by the coarse model.
llvm-svn: 308697
2017-07-20 23:41:50 +00:00
855411566b
Add latency info for Exynos interleaved Load/Store instructions.
...
llvm-svn: 304259
2017-05-31 00:20:55 +00:00
b21fb29c26
[AArch64] Add new subtarget feature to fuse AES crypto operations
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This feature enables the fusion of such operations on Cortex A57, as
recommended in its Software Optimisation Guide, section 4.13, and on Exynos
M1.
Differential revision: https://reviews.llvm.org/D28491
llvm-svn: 293738
2017-02-01 02:54:39 +00:00
405c90e6cc
[AArch64] Adjust the scheduling model for Exynos M1.
...
Further refine the model for branches.
llvm-svn: 280736
2016-09-06 19:22:29 +00:00
77e6b5d4e0
[AArch64] Adjust the scheduling model for Exynos M1.
...
Further refine the model for stores.
llvm-svn: 280735
2016-09-06 19:22:27 +00:00
199cad4f17
[AArch64] Adjust the scheduling model for Exynos M1.
...
Further refine the model for loads.
llvm-svn: 280734
2016-09-06 19:22:19 +00:00
a8a25ca905
[AArch64] Adjust the scheduling model for Exynos M1.
...
Further refine the model for loads.
llvm-svn: 279976
2016-08-29 16:04:37 +00:00
5a5b8dcd32
[AArch64] Adjust the scheduling model for Exynos M1.
...
Refine the model for the FP division unit.
llvm-svn: 278846
2016-08-16 20:35:01 +00:00
d03aff2e11
[AArch64] Adjust the scheduling model for Exynos M1.
...
Refine the model for the integer division unit.
llvm-svn: 278845
2016-08-16 20:34:58 +00:00
3830479f41
[AArch64] Adjust the model for the vector by element FP multiplies on Exynos M1. (NFC)
...
llvm-svn: 273708
2016-06-24 18:58:54 +00:00
62c70101c3
[AArch64] Model the cost of vector by element FP multiplies on Exynos M1. (NFC)
...
llvm-svn: 273630
2016-06-23 23:43:23 +00:00
8057265cc2
[AArch64] Adjust the loop buffer size for Exynos M1 (NFC)
...
llvm-svn: 273185
2016-06-20 18:39:41 +00:00
3c65acf87e
Remove MinLatency in SchedMachineModel. NFC.
...
Summary:
We don't use MinLatency any more since r184032.
Reviewers: atrick, hfinkel, mcrosier
Differential Revision: http://reviews.llvm.org/D19474
llvm-svn: 267502
2016-04-26 00:37:46 +00:00
551af44e31
[AArch64] Fuse AES{D,E}/AESMC for Exynos M1. (NFC)
...
llvm-svn: 266144
2016-04-12 22:42:36 +00:00
669aaccb89
[AArch64] Minor reformatting (NFC).
...
llvm-svn: 263054
2016-03-09 19:56:38 +00:00
a6cfb6f682
AArch64: Add missing schedinfo, check completeness for cyclone
...
This adds some missing generic schedule info definitions, enables
completeness checking for cyclone and fixes a typo uncovered by that.
Differential Revision: http://reviews.llvm.org/D17748
llvm-svn: 262393
2016-03-01 21:20:31 +00:00
d761ca2308
[AArch64] Add the scheduling model for Exynos-M1
...
Summary:
Add the core scheduling model for the Samsung Exynos-M1 (ARMv8-A).
Reviewers: jmolloy, rengolin, christof, MinSeongKIM, t.p.northover
Subscribers: aemerson, rengolin, MatzeB
Differential Revision: http://reviews.llvm.org/D16644
llvm-svn: 259958
2016-02-06 00:01:41 +00:00
Evandro Menezes