c2c2eb7d01
AMDGPU: Add D16 instructions preserve unused bits feature
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- Predicate D16 patterns on this new feature
- Added this new feature to gfx900/2/4
Differential Revision: https://reviews.llvm.org/D46366
llvm-svn: 331551
2018-05-04 20:06:57 +00:00
2a22c5deff
[AMDGPU] Switch to the new addr space mapping by default
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This requires corresponding clang change.
Differential Revision: https://reviews.llvm.org/D40955
llvm-svn: 324101
2018-02-02 16:07:16 +00:00
9a7e29ae91
AMDGPU: Use stricter regexes for add instructions
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Match the entire _co as one optional piece rather than
a set of characters to match multiple times.
llvm-svn: 319275
2017-11-29 02:25:14 +00:00
a0342dc9eb
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
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See bug 34765: https://bugs.llvm.org//show_bug.cgi?id=34765
Reviewers: tamazov, SamWot, arsenm, vpykhtin
Differential Revision: https://reviews.llvm.org/D40088
llvm-svn: 318675
2017-11-20 18:24:21 +00:00
45b98189bd
AMDGPU: Don't use MUBUF vaddr if address may overflow
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Effectively revert r263964. Before we would not
allow this if vaddr was not known to be positive.
llvm-svn: 318240
2017-11-15 00:45:43 +00:00
4b7938c658
AMDGPU: Fix not converting d16 load/stores to offset
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Fixes missed optimization with new MUBUF instructions.
llvm-svn: 318106
2017-11-13 23:24:26 +00:00
fcc213fab7
AMDGPU: Match store d16_hi instructions
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llvm-svn: 313712
2017-09-20 03:20:09 +00:00
Konstantin Zhuravlyov