Commit Graph

423026 Commits

Author SHA1 Message Date
Matthias Springer 5f60c4825b [mlir][linalg][bufferize][NFC] Make init_tensor elimination a separate pre-processing pass
This commit decouples init_tensor elimination from the rest of the bufferization.

Differential Revision: https://reviews.llvm.org/D124853
2022-05-04 17:17:27 +09:00
Fangrui Song 5a44980f0a [ELF] Support custom sections between DATA_SEGMENT_ALIGN and DATA_SEGMENT_RELRO_END
We currently hard code RELRO sections. When a custom section is between
DATA_SEGMENT_ALIGN and DATA_SEGMENT_RELRO_END, we may report a spurious
`error: section: ... is not contiguous with other relro sections`. GNU ld
makes such sections RELRO.

glibc recently switched to default --with-default-link=no. This configuration
places `__libc_atexit` and others between DATA_SEGMENT_ALIGN and
DATA_SEGMENT_RELRO_END. This patch allows such a ld.bfd --verbose
linker script to be fed into lld.

Reviewed By: peter.smith

Differential Revision: https://reviews.llvm.org/D124656
2022-05-04 01:10:46 -07:00
Matthias Springer 37a1473524 [mlir][bufferize] Allow in-place bufferization for writes to init_tensors in loops
This commit relaxes the rules around ops that define a value but do not specify the tensor's contents. (The only such op at the moment is init_tensor.)

When such a tensor is written in a loop, it should not cause out-of-place bufferization.

Differential Revision: https://reviews.llvm.org/D124849
2022-05-04 16:43:43 +09:00
serge-sans-paille 7030654296 [iwyu] Handle regressions in libLLVM header include
Running iwyu-diff on LLVM codebase since fa5a4e1b95 detected a few
regressions, fixing them.

Differential Revision: https://reviews.llvm.org/D124847
2022-05-04 08:32:38 +02:00
Marius Brehler 63aaf9a6e7 [mlir] Add missing CMake deps to mlir-pdll
Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D124851
2022-05-04 06:17:13 +00:00
Luboš Luňák 9c34a16c7c [ThreadPool] delete debug global variable if not needed
https://lab.llvm.org/buildbot/#/builders/5/builds/23099
2022-05-04 08:12:45 +02:00
Douglas Yung 0cb59607dc Mark test icf-safe.s as requiring aarch64 to fix buildbots which don't build that target. 2022-05-03 22:45:43 -07:00
Luboš Luňák 20048f3150 [lldb] use one shared ThreadPool and task groups
As a preparation for parallelizing loading of symbols (D122975),
it is necessary to use just one thread pool to avoid using
a thread pool from inside a task of another thread pool.

Differential Revision: https://reviews.llvm.org/D123226
2022-05-04 06:18:20 +02:00
Luboš Luňák 8ef5710e63 [ThreadPool] add ability to group tasks into separate groups
This is needed for parallelizing of loading modules symbols in LLDB
(D122975). Currently LLDB can parallelize indexing symbols
when loading a module, but modules are loaded sequentially. If LLDB
index cache is enabled, this means that the cache loading is not
parallelized, even though it could. However doing that creates
a threadpool-within-threadpool situation, so the number of threads
would not be properly limited.

This change adds ThreadPoolTaskGroup as a simple type that can be
used with ThreadPool calls to put tasks into groups that can be
independently waited for (even recursively from within a task)
but still run in the same thread pool.

Differential Revision: https://reviews.llvm.org/D123225
2022-05-04 06:16:55 +02:00
Luo, Yuanke 764676b737 [fastregalloc] Fix bug when undef value is tied to def.
If the tied use is undef value, fastregalloc should free the def
register. There is no reload needed for the undef value.

Reviewed By: MatzeB

Differential Revision: https://reviews.llvm.org/D124834
2022-05-04 12:12:55 +08:00
Craig Topper 1d6430b9e2 [RISCV] Update isLegalAddressingMode for RVV.
RVV instructions only support base register addressing.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D124820
2022-05-03 19:49:11 -07:00
Craig Topper 9cce9a126c [RISCV] Make use of SHXADD instructions in RVV spill/reload code.
We can use SH1ADD, SH2ADD, SH3ADD to multipy by 3, 5, and 9 respectively.

We could extend this to 3, 5, or 9 multiplied by a power 2 by also
emitting a SLLI.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D124824
2022-05-03 19:35:21 -07:00
Craig Topper 0971819740 [RISCV] Don't lookup TII in RISCVInstrInfo::getVLENFactoredAmount. NFCI
We're already inside of our implementation of TII.
2022-05-03 19:35:21 -07:00
Amir Ayupov 60957a5a08 [BOLT] Fix ICPJumpTablesTopN option use
Fix non-sensical `opts::ICPJumpTablesTopN != 0 ? opts::ICPTopN : opts::ICPTopN`.
Refactor/simplify another similar assignment.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D124880
2022-05-03 19:34:10 -07:00
Amir Ayupov c3d5372093 [BOLT][NFC] Make ICP options naming uniform
Rename `opts::IndirectCallPromotion*` to `opts::ICP*`, making option naming
uniform and easier to follow.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D124879
2022-05-03 19:32:45 -07:00
Amir Ayupov d0b1c98c96 [BOLT][NFC] ICP: simplify findTargetsIndex
Unnest lambda and use `llvm::is_contained`.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D124877
2022-05-03 19:31:20 -07:00
Amir Ayupov ec02227bf7 [BOLT][NFC] Refactor ICP::findCallTargetSymbols
Reduce nesting making it easier to read.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D124876
2022-05-03 19:29:22 -07:00
Amir Ayupov f9db6d2d5b [BOLT][CMAKE] Fix llvm-bolt-fuzzer build
Add X86/AArch64 targets to resolve missing dependencies, e.g.:
`undefined reference to `LLVMInitializeX86AsmParser'`

Follow-up to D124206

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D124886
2022-05-03 19:25:48 -07:00
Weverything 5afd20806d [riscv] Mark function as used to avoid unused warning. 2022-05-03 18:51:23 -07:00
Hongtao Yu 3113e5bb52 [CSSPGO] Relax size limitation for priority inlining with preinlined profile
As a follow-up to D124632, I'm turning on unlimited size caps for inlining with preinlined profile. It should be safe as a preinlined profile has "bounded" inline contexts.

No noticeable size or perf delta was seen with two of our internal large services, but I think this is still a good change to be consistent with the other case.

Reviewed By: wenlei

Differential Revision: https://reviews.llvm.org/D124793
2022-05-03 18:43:07 -07:00
Hongtao Yu e95ae395aa [CSSPGO][NFC] Replace SampleProfileLoader::ProfileIsCS with FunctionSamples::ProfileIsCS.
The two fields have the same meaning. Their values come from the reader. Therefore I'm removing one.

Reviewed By: wenlei

Differential Revision: https://reviews.llvm.org/D124788
2022-05-03 18:32:37 -07:00
Alex Borcan e29dc0c6fd [lld] Implement safe icf for MachO
This change implements --icf=safe for MachO based on addrsig section that is implemented in D123751.

Reviewed By: int3, #lld-macho

Differential Revision: https://reviews.llvm.org/D123752
2022-05-03 21:01:03 -04:00
Joseph Huber 46a5a8029e [OpenMP] Fix save-temps name in linker wrapper
Summary:
The wrapped registration code had a typo in the save-temps version of
the name.
2022-05-03 20:51:05 -04:00
Philip Reames dbe716e874 [riscv] Add vsetvli tests involving moves to/from scalar regs 2022-05-03 17:25:35 -07:00
Philip Reames dbbbc9e2ca [riscv] Add a couple more vsetvli tests 2022-05-03 16:49:52 -07:00
Weverything 0e86cddf98 [psuedo] Fix for unused warning by moving code into debug macro. 2022-05-03 16:07:59 -07:00
Weverything 3dd00461f9 [trace][intelpt] Fix out-of-bounds access.
The StringRef single argument constructor expects a null-terminated
string.  Explicitly pass the size to prevent reading pass the end
of the array.
2022-05-03 16:07:58 -07:00
Matt Arsenault c4e5a24dd6 ARM: Fix using undefined virtual registers in test
The verifier apparently doesn't work correctly and should have
caught this.
2022-05-04 00:05:49 +01:00
Matt Arsenault 994c96aef6 ARM: Cleanup MIR test
Drop IR section, renumber registers, regenerate to use -NEXT
2022-05-04 00:05:15 +01:00
Matt Arsenault 574ca03ef3 AMDGPU: Remove some invalid kill flags in tests
These killed registers need to be live out of the block but the
verifier wasn't catching it.
2022-05-04 00:05:15 +01:00
Matt Arsenault 5dfe4b7cf2 AMDGPU: Regenerate test checks 2022-05-04 00:05:15 +01:00
Matt Arsenault 241ca47db5 llvm-reduce: Reduce includes 2022-05-04 00:05:15 +01:00
Amir Ayupov 1d5263c554 [BOLT][TEST] Fix test failures on AArch64 builder
Address X86 tests failures on AArch64 builder:
https://lab.llvm.org/staging/#/builders/211/builds/82

Inputs fail to cross-compile due to a missing header:
```
/usr/include/stdio.h:27:10: fatal error: 'bits/libc-header-start.h' file not found
#include <bits/libc-header-start.h>
```

As inputs are linked with `-nostdlib` anyway, don't include stdio.h.

Reviewed By: yota9

Differential Revision: https://reviews.llvm.org/D124863
2022-05-03 15:39:43 -07:00
Alex Borcan afaa56df7a Implement support for __llvm_addrsig for MachO in llvm-mc
The __llvm_addrsig section is a section that the linker needs for safe icf.
This was not yet implemented for MachO - this is the implementation.
It has been tested with a safe deduplication implementation inside lld.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D123751
2022-05-03 18:19:18 -04:00
Jonas Devlieghere b945b62cf3
[lldb] Add a function to check if lldb is running in an interactive session
This patch adds a function to check if lldb is running in an interactive
debug session. Currently this API only works on macOS. It's expected to
be used in combination with Host::OpenFileInExternalEditor.

Differential revision: https://reviews.llvm.org/D124872
2022-05-03 15:11:57 -07:00
Jonas Devlieghere 3d08c778c0
[lldb] Session transcript should use the async debugger streams
When writing out the session transcript, print output to the
asynchronous debugger stream to prevent it from potentially interleaving
with other output.

Differential revision: https://reviews.llvm.org/D124873
2022-05-03 15:11:57 -07:00
Aart Bik 2617f2f708 [mlir][sparse] fix build issue with unused local under opt builds
Reviewed By: rdzhabarov

Differential Revision: https://reviews.llvm.org/D124883
2022-05-03 14:55:32 -07:00
Jon Roelofs e1c808b36e Fix zero-width bitfield extracts to emit 0
Fixes #55129
2022-05-03 14:46:42 -07:00
Chris Bieneman 15d20b9764 Fix DXBC magic parsing
This gets identify_magic working correctly for DXContainer files
2022-05-03 14:41:48 -07:00
Philip Reames 2982d0032b Fix a buildbot warning [nfc] 2022-05-03 14:40:27 -07:00
Aart Bik 1abcdc677c [mlir][sparse] add missing types to from/to-MLIR conversion routines
This will enable our usual set of element types in external
environments, such as PyTACO support.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D124875
2022-05-03 14:36:37 -07:00
Yangguang Li 3a8266902b [SCEV] Removed an unnecessary assertion
The assertion is to check we always get backedge taken count
(`BECount`) of zero when the exit condition is in select form
(`isa<BinaryOperation>(ExitCond)`) and the exit limit for the
first operand is zero `EL0.ExactNotTaken->isZero()`). However
the assertion is checking that the exit condition is NOT in
select form. Removing the the whole assertion since we now handle
select form in ScalarEvolution::getSequentialMinMaxExpr.

Reviewed By: reames, nikic

Differential Revision: https://reviews.llvm.org/D122835
2022-05-03 17:26:27 -04:00
Stella Stamenova 5f14aee3bb [mlir] Fix Visual Studio warnings
There are only a couple of warnings when compiling with VS on Windows. This fixes the last remaining warnings so that we can enable LLVM_ENABLE_WERROR on the mlir windows bot.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D124862
2022-05-03 14:12:15 -07:00
Benjamin Kramer 9eccc7357e [bazel] Fix the build after 2c33266084 2022-05-03 23:04:10 +02:00
Philip Reames be50b8c185 [riscv] Add debug printing support for VSETVLIInfo class [nfc] 2022-05-03 14:00:17 -07:00
Jim Kitchen 2c33266084 [mlir][sparse] Add lowering for unary and binary ops
Adding lowering for Unary and Binary required several changes due to
their unique nature of containing custom code for different "regions"
of the sparse structure being operated on. Along with a Kind, a pointer
to the Operation is passed along to be merged once the lattice
structure is figured out.

The original operation is maintained, as it is required for subsequent
lattice decisions. However, sparse_tensor.binary has some branches
are considered as fully handled and therefore are marked with as
kBinaryBranch to distinguish them.

A unique aspect of the custom code is that sometimes the desired result
is no result at all -- i.e. a user wants overlapping sparse entries to
become empty in the output. The solution to this is to return an
uninitialized Value(), which is checked and handled elsewhere in the
code and results in nothing being written to the output tensor for that
case.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D123057
2022-05-03 15:50:26 -05:00
Haojian Wu c4546091ed [pseudo] Use a real language option in the parser.
Differential Revision: https://reviews.llvm.org/D124831
2022-05-03 22:24:56 +02:00
Sanjay Patel 432c199e84 [InstCombine] move shuffle after min/max with same-shuffled operands
This is an intrinsic version of the existing fold for binops.
As a first step, I only allowed min/max, but the code is set
up to make adding more intrinsics easy (with more or less than
2 arguments).

This (and possible follow-ups) are discussed in issue #46238.
2022-05-03 16:23:11 -04:00
Sanjay Patel a47e03685b [InstCombine] add tests for min/max with shuffled operands; NFC
Issue #46238
2022-05-03 16:23:11 -04:00
David Pagan 37471cf2c3 [clang][OpenMP] Local variable alignment incorrect with align clause
If alignment specified with align clause is less than natural alignment for
list item type, the alignment should be set to the natural alignment.

See OMP5.1 specification, page 185, lines 7-10

Differential Revision: https://reviews.llvm.org/D124676
2022-05-03 13:10:01 -07:00