Commit Graph

65 Commits

Author SHA1 Message Date
Dan Gohman 072e52f170 Use isTerminator() instead of isBranch()||isReturn() in
several places. isTerminator() returns true for a superset
of cases, and includes things like FP_REG_KILL, which are
nither return or branch but aren't safe to move/remat/etc.

llvm-svn: 61373
2008-12-23 17:28:50 +00:00
Dan Gohman b9a012156b Add initial support for back-scheduling address computations,
especially in the case of addresses computed from loop induction
variables.

llvm-svn: 61075
2008-12-16 03:35:01 +00:00
Dan Gohman dddc1ac7ea Fix some register-alias-related bugs in the post-RA scheduler liveness
computation code. Also, avoid adding output-depenency edges when both
defs are dead, which frequently happens with EFLAGS defs.

Compute Depth and Height lazily, and always in terms of edge latency
values. For the schedulers that don't care about latency, edge latencies
are set to 1.

Eliminate Cycle and CycleBound, and LatencyPriorityQueue's Latencies array.
These are all subsumed by the Depth and Height fields.

llvm-svn: 61073
2008-12-16 03:25:46 +00:00
Dan Gohman 8f782bbb28 Add a simple target-independent heuristic to allow targets with no
instruction itinerary data to back-schedule loads.

llvm-svn: 61070
2008-12-16 02:38:22 +00:00
Dan Gohman 2d170896ee Rewrite the SDep class, and simplify some of the related code.
The Cost field is removed. It was only being used in a very limited way,
to indicate when the scheduler should attempt to protect a live register,
and it isn't really needed to do that. If we ever want the scheduler to
start inserting copies in non-prohibitive situations, we'll have to
rethink some things anyway.

A Latency field is added. Instead of giving each node a single
fixed latency, each edge can have its own latency. This will eventually
be used to model various micro-architecture properties more accurately.

The PointerIntPair class and an internal union are now used, which
reduce the overall size.

llvm-svn: 60806
2008-12-09 22:54:47 +00:00
Dan Gohman f90d3b096a Fix the top-level comments, and fix some 80-column violations.
llvm-svn: 60707
2008-12-08 17:50:35 +00:00
Dan Gohman 3aab10b932 Add minimal support for disambiguating memory references. Currently
the main thing this covers is spills to distinct spill slots.

llvm-svn: 60517
2008-12-04 01:35:46 +00:00
Dan Gohman d2b10368ed Pass the isAntiDep argument.
llvm-svn: 59968
2008-11-24 17:24:27 +00:00
Dan Gohman 57d0b88830 Correctly set the isCtrl flag for chain dependencies.
llvm-svn: 59837
2008-11-21 19:17:25 +00:00
Dan Gohman 546bcfe8d6 Update comments.
llvm-svn: 59836
2008-11-21 19:16:58 +00:00
Dan Gohman d7d1fd7eb7 Set the isAntiDep flag in the MachineInstr scheduler.
llvm-svn: 59787
2008-11-21 02:38:21 +00:00
Dan Gohman d1f33e2397 Use ComputeLatency in the MachineInstr scheduler.
llvm-svn: 59777
2008-11-21 01:44:51 +00:00
Dan Gohman 7b7ca502fa Implement ComputeLatency for MachineInstr ScheduleDAGs. Factor
some of the latency computation logic out of the SDNode
ScheduleDAG code into a TargetInstrItineraries helper method
to help with this.

llvm-svn: 59761
2008-11-21 00:12:10 +00:00
Dan Gohman 22e9677a5e Treat mid-block labels the same as terminators when building the
MachineInstr scheduling DAG, meaning they implicitly depend on all
preceding defs. This fixes Benchmarks/Shootout-C++/except and
Regression/C++/EH/simple_rethrow in
  -relocation-model=pic -disable-post-RA-scheduler=false
mode.

llvm-svn: 59747
2008-11-20 19:58:35 +00:00
Dan Gohman 60cb69e665 Experimental post-pass scheduling support. Post-pass scheduling
is currently off by default, and can be enabled with
-disable-post-RA-scheduler=false.

This doesn't have a significant impact on most code yet because it doesn't
yet do anything to address anti-dependencies and it doesn't attempt to
disambiguate memory references. Also, several popular targets
don't have pipeline descriptions yet.

The majority of the changes here are splitting the SelectionDAG-specific
code out of ScheduleDAG, so that ScheduleDAG can be moved to
libLLVMCodeGen.a. The interface between ScheduleDAG-using code and
the rest of the scheduling code is somewhat rough and will evolve.

llvm-svn: 59676
2008-11-19 23:18:57 +00:00