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Author SHA1 Message Date
Evan Cheng e9c46c25a1 - Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. 
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).

llvm-svn: 97628
 2010-03-03 01:44:33 +00:00
Evan Cheng d8c50c67dc Eliminate unused instruction classes. 
llvm-svn: 97617
 2010-03-03 00:43:15 +00:00
Johnny Chen 334af68052 Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy for 
disassembly only.

llvm-svn: 97614
 2010-03-03 00:16:28 +00:00
Chris Lattner 8d63704021 merge two loops over all nodes in the graph into one. 
llvm-svn: 97606
 2010-03-02 23:12:51 +00:00
Chris Lattner 1eb6eb059c eliminate PreprocessForRMW now that isel handles it. 
We still preprocess calls and fp return stuff.

llvm-svn: 97598
 2010-03-02 22:33:56 +00:00
Chris Lattner 71ddd8e2aa remove 300 lines of code that is now dead in the MSP430 backend 
now that isel handles chains more aggressively.  This also
allows us to make isLegalToFold non-virtual.

llvm-svn: 97597
 2010-03-02 22:30:08 +00:00
Chris Lattner dd030701bd Fix some issues in WalkChainUsers dealing with 
CopyToReg/CopyFromReg/INLINEASM.  These are annoying because
they have the same opcode before an after isel.  Fix this by
setting their NodeID to -1 to indicate that they are selected,
just like what automatically happens when selecting things that
end up being machine nodes.

With that done, give IsLegalToFold a new flag that causes it to
ignore chains.  This lets the HandleMergeInputChains routine be
the one place that validates chains after a match is successful,
enabling the new hotness in chain processing.  This smarter
chain processing eliminates the need for "PreprocessRMW" in the
X86 and MSP430 backends and enables MSP to start matching it's
multiple mem operand instructions more aggressively.

I currently #if out the dead code in the X86 backend and MSP 
backend, I'll remove it for real in a follow-on patch.

The testcase changes are:
  test/CodeGen/X86/sse3.ll: we generate better code
  test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was 
      miscompiling this before, we now generate correct code
      Convert it to filecheck while I'm at it.
  test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem
      folding to make anton happy. :)

llvm-svn: 97596
 2010-03-02 22:20:06 +00:00
Johnny Chen 7041f2cef6 Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only. 
llvm-svn: 97595
 2010-03-02 22:11:06 +00:00
Johnny Chen 9dc2105478 Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as from 
the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.

llvm-svn: 97582
 2010-03-02 19:38:59 +00:00
Johnny Chen 44908a5e17 Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL, 
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.

llvm-svn: 97573
 2010-03-02 18:14:57 +00:00
Johnny Chen 0dae1cbf1c AL is an optional mnemonic extension for always, except in IT instructions. 
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.

Ref: A8.3 Conditional execution
llvm-svn: 97571
 2010-03-02 17:57:15 +00:00
Johnny Chen d520eabcb9 Change some asm shift opcode strings to lowercase. 
llvm-svn: 97567
 2010-03-02 17:03:18 +00:00
Xerxes Ranby 09d9a690d2 fix typo add missing ( 
llvm-svn: 97565
 2010-03-02 13:42:03 +00:00
Xerxes Ranby b1baf6583e Unbreak llvm-arm-linux buildbot and fix PR5309. 
llvm-svn: 97564
 2010-03-02 13:26:18 +00:00
Chris Lattner f98f124a73 Sink InstructionSelect() out of each target into SDISel, and rename it 
DoInstructionSelection.  Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.

Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.

 17 files changed, 114 insertions(+), 430 deletions(-)

llvm-svn: 97555
 2010-03-02 06:34:30 +00:00
Eric Christopher 118dc6a645 Only save vector registers if we've defined for the vector registers. 
Fixes PR5309.

llvm-svn: 97554
 2010-03-02 06:25:00 +00:00
Bill Wendling 78c5b7a76d Remove dead parameter passing. 
llvm-svn: 97536
 2010-03-02 01:55:18 +00:00
Dan Gohman 6f34abd092 Floating-point add, sub, and mul are now spelled fadd, fsub, and fmul, 
respectively.

llvm-svn: 97531
 2010-03-02 01:11:08 +00:00
Chris Lattner bd6e193f54 remove a little hack I did for the old isel, not needed 
now that it is gone.

llvm-svn: 97516
 2010-03-01 22:51:11 +00:00
Evan Cheng 87d50aa18a Remove the optimize for code size limitation on r67917. Optimize 64-bit imul by constants into leas + shl regardless if optimizing for code size. The size saving from using imulq isn't worth it. Also, the lea and shl instructions may expose further optimization. 
llvm-svn: 97507
 2010-03-01 22:00:11 +00:00
Chris Lattner 55ef1ebe52 remove a terrible hack that disabled assertions from this file because of build time 
problems.  rdar://7697850.

llvm-svn: 97500
 2010-03-01 21:20:46 +00:00
Chris Lattner 3780ca6ef2 stop using generated sdnodexforms. 
llvm-svn: 97485
 2010-03-01 19:38:53 +00:00
Johnny Chen 718ed8a6d5 Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the W 
bit should be set to 0 instead of 1.

llvm-svn: 97481
 2010-03-01 19:22:00 +00:00
Dan Gohman b0e07d53c1 Add explicit keywords. 
llvm-svn: 97460
 2010-03-01 17:56:46 +00:00
Dan Gohman 312d604ee2 This is now done. 
llvm-svn: 97450
 2010-03-01 17:43:57 +00:00
Nathan Keynes 42a5be5121 Add JIT support to the TODO list (test commit) 
llvm-svn: 97443
 2010-03-01 10:40:41 +00:00
Mikhail Glushenkov abd56bde0e 80-col violations/trailing whitespace. 
llvm-svn: 97427
 2010-02-28 22:54:30 +00:00
Chris Lattner 56c50da3f6 remove redundant instruction. 
llvm-svn: 97374
 2010-02-28 07:23:21 +00:00
Dan Gohman 0d8a9af7b8 Add a flag to addPassesToEmit* to disable the Verifier pass run 
after LSR, so that clients can opt in.

llvm-svn: 97357
 2010-02-28 00:41:59 +00:00
Dan Gohman bdd6405f29 Implement XMM subregs. 
Extracting the low element of a vector is now done with EXTRACT_SUBREG,
and the zero-extension performed by load movss is now modeled with
SUBREG_TO_REG, and so on.

Register-to-register movss and movsd are no longer considered copies;
they are two-address instructions which insert a scalar into a vector.

llvm-svn: 97354
 2010-02-28 00:17:42 +00:00
Dan Gohman 8c5d683aa9 The mayHaveSideEffects flag is no longer used. 
llvm-svn: 97348
 2010-02-27 23:47:46 +00:00
Chris Lattner f159afc951 remove a bogus pattern, which had the same pattern as STDU 
but codegen'd differently.  This really wanted to use some
sort of subreg to get the low 4 bytes of the G8RC register
or something.  However, it's invalid and nothing is testing
it, so I'm just zapping the bogosity.

llvm-svn: 97345
 2010-02-27 21:15:32 +00:00
Chris Lattner a2075d44ad fix an incorrect (overly conservative) predicate. 
llvm-svn: 97316
 2010-02-27 08:18:55 +00:00
Evan Cheng 228c31f045 Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap. 
llvm-svn: 97310
 2010-02-27 07:36:59 +00:00
Johnny Chen 38e7bb6f34 Added the follwoing 32-bit Thumb instructions for disassembly only: 
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]

llvm-svn: 97276
 2010-02-26 22:04:29 +00:00
Jakob Stoklund Olesen 17d54920d7 Merge PPC instructions FMRS and FMRD into a single FMR instruction. 
This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so
fextend has a pattern.

Also allow folding of memory operands on FMRSD.

llvm-svn: 97275
 2010-02-26 21:53:24 +00:00
Jakob Stoklund Olesen ddbf7a858e Use the right floating point load/store instructions in PPCInstrInfo::foldMemoryOperandImpl(). 
The PowerPC floating point registers can represent both f32 and f64 via the
two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to
allow cross-class coalescing. This coalescing only affects whether registers
are spilled as f32 or f64.

Spill slots must be accessed with load/store instructions corresponding to the
class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking
at the instruction opcode which is wrong.

X86 has similar floating point register classes, but doesn't try to fold
memory operands, so there is no problem there.

llvm-svn: 97262
 2010-02-26 21:09:24 +00:00
Dale Johannesen dd33104203 Move dbg_value generation to target-independent FastISel, 
as X86 is currently the only FastISel target.  Per review.

llvm-svn: 97255
 2010-02-26 20:01:55 +00:00
Sanjiv Gupta ef686dc38d The cloner has nothing to do if any of the main or ISR entrypoints are not 
present in the module.

llvm-svn: 97232
 2010-02-26 18:32:18 +00:00
Sanjiv Gupta 2bdbb3c167 Reapply things reverted back in 97220, with the fixed test case. 
llvm-svn: 97228
 2010-02-26 17:59:28 +00:00
Dan Gohman 952f6f98bb movl is a cheaper way to materialize 0 without clobbering EFLAGS than movabsq. 
llvm-svn: 97227
 2010-02-26 16:49:27 +00:00
Richard Osborne 333300e0df Fix XCoreTargetLowering::isLegalAddressingMode() to handle VoidTy. 
Previously LoopStrengthReduce would sometimes be unable to find
a legal formula, causing an assertion failure.

llvm-svn: 97226
 2010-02-26 16:44:51 +00:00
Chandler Carruth 663f658d87 Revert r97211 and r97213 to get the build green again. 
llvm-svn: 97220
 2010-02-26 08:43:09 +00:00
Sanjiv Gupta 7828ff9535 Currently in LLVM, names of libcalls are assigned during TargetLowering 
object construction. There is no provision to change them when the 
code for a function generated. 
So we have to change these names while printing assembly.

llvm-svn: 97213
 2010-02-26 07:31:15 +00:00
Sanjiv Gupta 528b1465e5 Before converting an operand to mem, check if it is legal to do so. 
llvm-svn: 97211
 2010-02-26 07:27:35 +00:00
Dan Gohman 9300486d68 Delete a bunch of redundant predicates. 
llvm-svn: 97201
 2010-02-26 01:14:30 +00:00
Johnny Chen 3adff378cc Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE, 
and SRS.

llvm-svn: 97164
 2010-02-25 20:25:24 +00:00
Johnny Chen 871e5b0926 Added the 32-bit Thumb instructions (BXJ) for disassembly only. 
llvm-svn: 97163
 2010-02-25 19:05:29 +00:00
Johnny Chen e285f70a42 Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only. 
llvm-svn: 97159
 2010-02-25 18:46:43 +00:00
Daniel Dunbar 68e22cb5a0 Fix TextAlignFillValue in a few places 
llvm-svn: 97151
 2010-02-25 18:07:10 +00:00
Johnny Chen 74cca5a989 Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE, 
WFI, SEV, SETEND.

llvm-svn: 97149
 2010-02-25 17:51:03 +00:00
Dan Gohman 9b80f86e5b Revert r97064. Duncan pointed out that bitcasts are defined in 
terms of store and load, which means bitcasting between scalar
integer and vector has endian-specific results, which undermines
this whole approach.

llvm-svn: 97137
 2010-02-25 15:20:39 +00:00
Sanjiv Gupta ad117dac4b Each field of auxiliary debug entry is only 1 byte long. 
llvm-svn: 97108
 2010-02-25 03:54:49 +00:00
Johnny Chen 90adefcf7e Added tNOP for disassembly only. 
llvm-svn: 97105
 2010-02-25 03:28:51 +00:00
Dan Gohman ec4e1b67bf Truncate from i64 to i32 is "free" on x86-32, because it involves 
just discarding one of the registers.

llvm-svn: 97100
 2010-02-25 03:04:36 +00:00
Scott Michel 4a99c34873 Revert this patch for the time being. Needs more testing. 
llvm-svn: 97099
 2010-02-25 02:32:54 +00:00
Johnny Chen 57656da73f Added tSVC and tTRAP for disassembly only. 
llvm-svn: 97098
 2010-02-25 02:21:11 +00:00
Scott Michel 0ab0ad93bd Large stack frame patch for the CellSPU: handle stack frames that exceed 8176 
(511*16) bytes register displacement (D-form).

NOTE: This is a potential headache, given the SPU's local core limitations,
allowing the software developer to commit stack overrun suicide unknowingly.
Also, large SPU stack frames will cause code size explosion. But, one presumes
that the software developer knows what they're doing...

Contributed by Kalle.Raiskila@nokia.com, edited slightly before commit.

llvm-svn: 97091
 2010-02-25 01:53:17 +00:00
Jakob Stoklund Olesen 63af51c1c8 Create a stack frame on ARM when 
- Function uses all scratch registers AND
- Function does not use any callee saved registers AND
- Stack size is too big to address with immediate offsets.

In this case a register must be scavenged to calculate the address of a stack
object, and the scavenger needs a spare register or emergency spill slot.

llvm-svn: 97071
 2010-02-24 22:43:17 +00:00
Bob Wilson ba8ac74fd9 Check for comparisons of +/- zero when optimizing less-than-or-equal and 
greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions.  This is
only allowed when UnsafeFPMath is set or when at least one of the operands
is known to be nonzero.

llvm-svn: 97065
 2010-02-24 22:15:53 +00:00
Dan Gohman 4b2b48daba Make getTypeSizeInBits work correctly for array types; it should return 
the number of value bits, not the number of bits of allocation for in-memory
storage.

Make getTypeStoreSize and getTypeAllocSize work consistently for arrays and
vectors.

Fix several places in CodeGen which compute offsets into in-memory vectors
to use TargetData information.

This fixes PR1784.

llvm-svn: 97064
 2010-02-24 22:05:23 +00:00
Wesley Peck 05d9124625 Adding function "lookupGCCName" to MBlazeIntrinsicInfo 
Adding the function "lookupGCCName" to the MBlazeIntrinsicInfo
class to support the Clang MicroBlaze target.

Additionally, minor fixes which remove some unused PIC code 
(PIC is not supported yet in the MicroBlaze backend) and
removed some unused variables.

llvm-svn: 97054
 2010-02-24 20:16:27 +00:00
Johnny Chen 86ba44a4c7 Added Vector Swap (VSWPd and VSWPq) instructions for disassembly only. 
A8.6.405

llvm-svn: 97052
 2010-02-24 20:06:07 +00:00
Jakob Stoklund Olesen 0b94eb19e4 Stay away from str <undef> in ARMLoadStoreOpt. This pass does not understand 
<undef> operands, and can cause scavenger failures when it translates
<kill,undef> to <kill>.

llvm-svn: 97046
 2010-02-24 18:57:08 +00:00
Johnny Chen 03ac201ad9 Fixed typo of opcodestr, should be "vst1", not "vld1". 
llvm-svn: 97044
 2010-02-24 18:00:40 +00:00
Daniel Dunbar 4811d004be Speculatively revert r97011, "Re-apply 96540 and 96556 with fixes.", again in 
the hopes of fixing PPC bootstrap.

llvm-svn: 97040
 2010-02-24 17:05:47 +00:00
Dan Gohman 3860521406 When forming SSE min and max nodes for UGE and ULE comparisons, it's 
necessary to swap the operands to handle NaN and negative zero properly.

Also, reintroduce logic for checking for NaN conditions when forming
SSE min and max instructions, fixed to take into consideration NaNs and
negative zeros. This allows forming min and max instructions in more
cases.

llvm-svn: 97025
 2010-02-24 06:52:40 +00:00
Chandler Carruth f0485ed9ac Remove an unused variable. Was this intentional? 
llvm-svn: 97022
 2010-02-24 06:09:03 +00:00
Johnny Chen d5c472d811 Added for disassembly VST1 (multiple single elements) which stores elements to 
memory from three or four registers and VST2 (multiple two-element structures)
which stores to memory from two double-spaced registers.

A8.6.391 & A8.6.393

llvm-svn: 97018
 2010-02-24 02:57:20 +00:00
Jim Grosbach 2921550485 handle very large call frames when require SPAdj != 0 for Thumb1 
llvm-svn: 97013
 2010-02-24 02:15:43 +00:00
Jim Grosbach 6ad4bcb0da LowerCall() should always do getCopyFromReg() to reference the stack pointer. 
Machine instruction selection is much happier when operands are in virtual
registers.

llvm-svn: 97012
 2010-02-24 01:43:03 +00:00
Evan Cheng 328a607490 Re-apply 96540 and 96556 with fixes. 
llvm-svn: 97011
 2010-02-24 01:42:31 +00:00
Jakob Stoklund Olesen a2d8c97b65 DIV8r must define %AX since X86DAGToDAGISel::Select() sometimes uses it 
instead of %AL/%AH.

llvm-svn: 97006
 2010-02-24 00:39:35 +00:00
Evan Cheng da52f449a0 Fix rev 96389 by restricting the xform to mask that's either signbit or max signed value. 
llvm-svn: 96990
 2010-02-23 21:51:54 +00:00
Richard Osborne 00fb2ce233 Don't mark call instruction as a barrier. 
llvm-svn: 96983
 2010-02-23 21:08:11 +00:00
Johnny Chen b14a5c52bc Added for disassembly VLD1 (multiple single elements) which loads memory into 
three or four registers and VLD2 (multiple two-element structures) which loads
memory into two double-spaced registers.

A8.6.307 & A8.6.310

llvm-svn: 96980
 2010-02-23 20:51:23 +00:00
Nicolas Geoffray 3cc6673fd0 Use the module's context instead of the global context. 
llvm-svn: 96977
 2010-02-23 19:42:44 +00:00
Chris Lattner 8d7b4393d2 no need to override IsLegalToFold, the base implementation 
disables load folding at -O0.

llvm-svn: 96973
 2010-02-23 19:33:11 +00:00
Wesley Peck e4801e49c9 Adding the MicroBlaze backend. 
The MicroBlaze is a highly configurable 32-bit soft-microprocessor for
use on Xilinx FPGAs. For more information see:
http://www.xilinx.com/tools/microblaze.htm
http://en.wikipedia.org/wiki/MicroBlaze

The current LLVM MicroBlaze backend generates assembly which can be
compiled using the an appropriate binutils assembler.

llvm-svn: 96969
 2010-02-23 19:15:24 +00:00
Richard Osborne 3a53f4e240 ECALLF, ECALLT shouldn't be marked as barriers. 
llvm-svn: 96964
 2010-02-23 18:29:49 +00:00
Richard Osborne f81db146b4 Mark unconditional branches as barriers. Found using -verify-machineinstrs 
llvm-svn: 96960
 2010-02-23 18:13:38 +00:00
Jim Grosbach 2f840382e2 Spelling. s/suppor /support / 
llvm-svn: 96954
 2010-02-23 17:16:27 +00:00
Richard Osborne e3eb3105d9 Remove unused lowering function LowerJumpTable 
llvm-svn: 96943
 2010-02-23 14:17:20 +00:00
Richard Osborne f578196968 Lower BR_JT on the XCore to a jump into a series of jump instructions. 
llvm-svn: 96942
 2010-02-23 13:25:07 +00:00
Chris Lattner 89f6ec462d disable two patterns that are using non-sensical result pattern types. 
llvm-svn: 96903
 2010-02-23 07:21:15 +00:00
Chris Lattner 7489838a89 remove a confused pattern that is trying to match an address 
then use it as an MMX register (!?).

llvm-svn: 96901
 2010-02-23 07:16:12 +00:00
Chris Lattner d17089231a remove a bunch of dead named arguments in input patterns, 
though some look dubious afaict, these are all ok.

llvm-svn: 96899
 2010-02-23 06:54:29 +00:00
Chris Lattner 48370e14e7 fix a type mismatch in this pattern, where we were using an i64 imm in a 
place where an i32 imm was required, the old isel just got lucky.

This fixes CodeGen/X86/x86-64-and-mask.ll

llvm-svn: 96894
 2010-02-23 06:09:57 +00:00
Chris Lattner c51b7198a9 reapply my cellspu changes with a fix to not break the old isel. 
llvm-svn: 96885
 2010-02-23 05:30:43 +00:00
Dan Gohman 7e5c4906dd Revert 96854, 96852, and 96849, unbreaking test/CodeGen/CellSPU/i64ops.ll. 
llvm-svn: 96871
 2010-02-23 02:33:29 +00:00
Chris Lattner a828850b4d X86InstrInfoSSE.td declares PINSRW as having type v8i16, 
don't alis it in the MMX .td file with a different width,
split into two X86ISD opcodes.  This fixes an x86 testcase.

llvm-svn: 96859
 2010-02-23 02:07:48 +00:00
Johnny Chen 21dbd6f449 Added versions of VCGE, VCGT, VCLE, and VCLT NEON instructions which compare to 
(immediate #0) for disassembly only.

A8.6.283, A8.6.285, A8.6.287, A8.6.290

llvm-svn: 96856
 2010-02-23 01:42:58 +00:00
Chris Lattner 22bc26e4cf fix hte last cellspu failure. 
llvm-svn: 96854
 2010-02-23 01:37:39 +00:00
Chris Lattner 807666783c hack around more crimes in instruction selection. 
llvm-svn: 96852
 2010-02-23 01:33:17 +00:00
Chris Lattner fbbe2617dc the cell backend is making all sorts of unsafe and incorrect assumptions 
about ownership and update policies.  It isn't clear why it is doing all
this lowering at isel time instead of in legalize.  This fixes fcmp64.ll

llvm-svn: 96849
 2010-02-23 01:20:00 +00:00
Johnny Chen 886915e3bb Added VCEQ (immediate #0) NEON instruction for disassembly only. 
A8.6.281

llvm-svn: 96838
 2010-02-23 00:33:12 +00:00
Jim Grosbach 45fceea0e4 Updated version of r96634 (which was reverted due to failing 176.gcc and 
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

llvm-svn: 96822
 2010-02-22 23:10:38 +00:00
Jim Grosbach 017a505716 Clean up a bit and fix for when SPAdj != 0 
llvm-svn: 96818
 2010-02-22 22:54:55 +00:00
Jim Grosbach 15f6ed348f The predicate index isn't fixed, so scan for it to make sure we get the proper 
value.

Thumb2 uses the tADJCALLSTACK* instructions, and doesn't need t2 versions, so
remove the FIXME entry.

llvm-svn: 96817
 2010-02-22 22:47:46 +00:00
Chris Lattner 3ac438b920 remove dupes now. 
llvm-svn: 96811
 2010-02-22 22:15:05 +00:00
Chris Lattner 435611200b move #includes earlier. 
llvm-svn: 96810
 2010-02-22 22:14:47 +00:00
Johnny Chen 5ddd4aca97 Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD, 
for disassembly only.

llvm-svn: 96806
 2010-02-22 21:50:40 +00:00
Johnny Chen 9d4a3e2a7c Added a bunch of instructions for disassembly only: 
o signed/unsigned add/subtract
o signed/unsigned halving add/subtract
o unsigned sum of absolute difference [and accumulate]
o signed/unsigned saturate
o signed multiply accumulate/subtract [long] dual

llvm-svn: 96795
 2010-02-22 18:50:54 +00:00
Arnold Schwaighofer 30ece5b807 Mark the return address stack slot as mutable when moving the return address 
during a tail call. A parameter might overwrite this stack slot during the tail
call. 

The sequence during a tail call is:
1.) load return address to temp reg
2.) move parameters (might involve storing to return address stack slot)
3.) store return address to new location from temp reg

If the stack location is marked immutable CodeGen can colocate load (1) with the
store (3).

This fixes bug 6225.

llvm-svn: 96783
 2010-02-22 16:18:09 +00:00
Dan Gohman c1a545c307 Fix a typo in a comment. 
llvm-svn: 96778
 2010-02-22 04:09:26 +00:00
Dan Gohman b87de8d30d Remove the logic for reasoning about NaNs from the code that forms 
SSE min and max instructions. The real thing this code needs to be
concerned about is negative zero.

Update the sse-minmax.ll test accordingly, and add tests for
-enable-unsafe-fp-math mode as well.

llvm-svn: 96775
 2010-02-22 04:03:39 +00:00
Chris Lattner db8d6678e9 fix an incorrect VT: eflags is always i32. The bug was causing us to 
create an X86ISD::Cmp node with result type i64 on the 
CodeGen/X86/shift-i256.ll testcase and the new isel was assert on it
downstream.

llvm-svn: 96768
 2010-02-22 00:28:59 +00:00
Daniel Dunbar 40eb7f0991 MC/X86: Add stub AsmBackend. 
llvm-svn: 96763
 2010-02-21 21:54:14 +00:00
Anton Korobeynikov 31a9212b0b It turned out that we failed to emit proper symbol stubs on non-x86/darwin for ages (we emitted a reference to a stub, but no stub was emitted). The code inside x86-32/macho target objfile lowering should actually be the generic one - move it there. 
This (I really, really hope) should fix EH issues on ppc/darwin
and arm/darwin.

llvm-svn: 96755
 2010-02-21 20:28:15 +00:00
Duncan Sands 455201ba71 Remove a bunch of duplicated code, where there was one version taking a std::ostream 
and another taking a raw_ostream, but otherwise identical.  Use raw_ostream everywhere.

llvm-svn: 96746
 2010-02-21 19:15:19 +00:00
Anton Korobeynikov e96503faa1 IT turns out that during jumpless setcc lowering eq and ne were swapped. 
This fixes PR6348

llvm-svn: 96734
 2010-02-21 12:28:58 +00:00
Chris Lattner 3c29aff9ff fix and un-xfail X86/vec_ss_load_fold.ll 
llvm-svn: 96720
 2010-02-21 04:53:34 +00:00
Johnny Chen a07c9c7c56 Undo r96654. The printing of ARM shift instructions in canonical forms can be 
handled in ARMInstPrinter.cpp.

And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only.

llvm-svn: 96719
 2010-02-21 04:42:01 +00:00
Chris Lattner 18a32ce0f3 rename SelectScalarSSELoad -> SelectScalarSSELoadXXX and rewrite 
it to follow the mode needed by the new isel.  Instead of returning
the input and output chains, it just returns the (currently only one,
which is a silly limitation) node that has input and output chains.

Since we want the old thing to still work, add a new 
SelectScalarSSELoad to emulate the old interface.  The XXX suffix
and the wrapper will eventually go away.

llvm-svn: 96715
 2010-02-21 03:17:59 +00:00
Chris Lattner 986ab3fb1d Eliminate some uses of immAllOnes, just use -1, it does 
the same thing and is more efficient for the matcher.

llvm-svn: 96712
 2010-02-21 03:12:16 +00:00
Bob Wilson fbc9d8d424 Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in 
the armv6 nightly tests.

llvm-svn: 96691
 2010-02-19 18:59:53 +00:00
Charles Davis 7e47767763 Add support for the 'alignstack' attribute to the x86 backend. Fixes PR5254. 
Also, FileCheck'ize a test.

llvm-svn: 96686
 2010-02-19 18:17:13 +00:00
Bob Wilson 336c0a1c87 Revert Anton's most recent EH patch (r96637), since it breaks a lot of 
ARM and Thumb tests.

llvm-svn: 96680
 2010-02-19 17:10:59 +00:00
Duncan Sands d0bf6f640f Revert commits 96556 and 96640, because commit 96556 breaks the 
dragonegg self-host build.  I reverted 96640 in order to revert
96556 (96640 goes on top of 96556), but it also looks like with
both of them applied the breakage happens even earlier.  The
symptom of the 96556 miscompile is the following crash:

  llvm[3]: Compiling AlphaISelLowering.cpp for Release build
  cc1plus: /home/duncan/tmp/tmp/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:4982: void llvm::SelectionDAG::ReplaceAllUsesWith(llvm::SDNode*, llvm::SDNode*, llvm::SelectionDAG::DAGUpdateListener*): Assertion `(!From->hasAnyUseOfValue(i) || From->getValueType(i) == To->getValueType(i)) && "Cannot use this version of ReplaceAllUsesWith!"' failed.
  Stack dump:
  0.	Running pass 'X86 DAG->DAG Instruction Selection' on function '@_ZN4llvm19AlphaTargetLowering14LowerOperationENS_7SDValueERNS_12SelectionDAGE'
  g++: Internal error: Aborted (program cc1plus)

This occurs when building LLVM using LLVM built by LLVM (via
dragonegg).  Probably LLVM has miscompiled itself, though it
may have miscompiled GCC and/or dragonegg itself: at this point
of the self-host build, all of GCC, LLVM and dragonegg were built
using LLVM.  Unfortunately this kind of thing is extremely hard
to debug, and while I did rummage around a bit I didn't find any
smoking guns, aka obviously miscompiled code.

Found by bisection.

r96556 | evancheng | 2010-02-18 03:13:50 +0100 (Thu, 18 Feb 2010) | 5 lines

Some dag combiner goodness:
Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"

r96640 | evancheng | 2010-02-19 01:34:39 +0100 (Fri, 19 Feb 2010) | 16 lines

Transform (xor (setcc), (setcc)) == / != 1 to
(xor (setcc), (setcc)) != / == 1.

e.g. On x86_64
  %0 = icmp eq i32 %x, 0
  %1 = icmp eq i32 %y, 0
  %2 = xor i1 %1, %0
  br i1 %2, label %bb, label %return
=>
	testl   %edi, %edi
	sete    %al
	testl   %esi, %esi
	sete    %cl
	cmpb    %al, %cl
	je      LBB1_2

llvm-svn: 96672
 2010-02-19 11:30:41 +00:00
Johnny Chen 1ca8af9b76 Added entries for ASR, LSL, LSR, ROR, and RRX so that the disassembler prints 
out the canonical form (A8.6.98) instead of the pseudo-instruction as provided
via MOVs.

DBG_ARM_DISASM=YES llvm-mc -triple=arm-unknown-unknown --disassemble
0xc0 0x00 0xa0 0xe1
Opcode=29 Name=ASR Format=ARM_FORMAT_LDMISCFRM
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	asr	r0, r0, #1

llvm-svn: 96654
 2010-02-19 02:12:06 +00:00
Anton Korobeynikov 9baeb02000 Use the same encoding for EH stuff uniformly on all MachO targets. 
This hopefulyl should unbreak EH on PPC/Darwin.

llvm-svn: 96637
 2010-02-19 00:29:36 +00:00
Jim Grosbach aa34003f6f Radar 7636153. In the presence of large call frames, it's not sufficient 
for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.

llvm-svn: 96634
 2010-02-19 00:16:24 +00:00
Johnny Chen 688a90e2d7 Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only. 
llvm-svn: 96619
 2010-02-18 22:31:18 +00:00
Dale Johannesen 654528e8a7 Generate DBG_VALUE from dbg.value intrinsics. These currently 
comes out as comments but will eventually generate DWARF.

llvm-svn: 96601
 2010-02-18 18:51:15 +00:00
Sanjiv Gupta a124a46748 Remap the call sites of a shared function in interrupt line functions. 
llvm-svn: 96591
 2010-02-18 18:00:35 +00:00
Sanjiv Gupta 32db8a17c5 Re-factoring. 
llvm-svn: 96589
 2010-02-18 17:32:25 +00:00
Chris Lattner fd47c79774 add a missing type cast. 
llvm-svn: 96574
 2010-02-18 06:33:42 +00:00
Bob Wilson c6c13a3515 Use NEON vmin/vmax instructions for floating-point selects. 
Radar 7461718.

llvm-svn: 96572
 2010-02-18 06:05:53 +00:00
Johnny Chen 74c904589e Added LDRSBT, LDRHT, LDRSHT for disassembly only. And fixed encoding errors 
of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process.

llvm-svn: 96565
 2010-02-18 03:27:42 +00:00
Evan Cheng 0ceb68a552 Some dag combiner goodness: 
Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"

llvm-svn: 96556
 2010-02-18 02:13:50 +00:00
Johnny Chen f3d79a5025 Added for disassembly only the variants of DMB, DSB, and ISB. 
llvm-svn: 96540
 2010-02-18 00:19:08 +00:00
Bob Wilson cb2deb2aaf Remove the NEON N2VSInt instruction class: it's only used in one place and 
since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.

llvm-svn: 96525
 2010-02-17 22:42:54 +00:00
Johnny Chen 1d793a5e0e Added CLREX (Clear-Exclusive) for disassembly only. 
A8.6.30

llvm-svn: 96523
 2010-02-17 22:37:58 +00:00
Bob Wilson 004d280d5e More cleanup for NEON: 
* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.

llvm-svn: 96521
 2010-02-17 22:23:11 +00:00
Johnny Chen 5454e0633e Added RFE for disassembly only. 
B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the
specified address and the following word respectively.

llvm-svn: 96519
 2010-02-17 21:39:10 +00:00
Jakob Stoklund Olesen 34d6a4ff17 Remember to define super registers in mips calls. 
llvm-svn: 96504
 2010-02-17 20:18:50 +00:00
Chris Lattner bdceca6f49 "Fix and issue in SparcAsmPrinter where multiple identical .LLGETPCHn symbols could be emitted in the same file (it was uniqued by block number, but not by function number). " Patch by Nathan Keynes! 
llvm-svn: 96495
 2010-02-17 18:57:19 +00:00
Chris Lattner 1fa9c2cce4 move isOnlyReachableByFallthrough out of MachineBasicBlock into AsmPrinter, 
and add a sparc implementation that knows about delay slots.  Patch by
Nathan Keynes!

llvm-svn: 96492
 2010-02-17 18:52:56 +00:00
Chris Lattner cb80e2527e add a note, from PR5100 
llvm-svn: 96490
 2010-02-17 18:42:24 +00:00
Sanjiv Gupta 69346eb94f Added routine to clone the body of a function and maintain a map of already 
cloned functions.

llvm-svn: 96485
 2010-02-17 18:11:29 +00:00
Sanjiv Gupta 81b3aa1b2f Added a function to clone locals of a function.( which for pic16 are globals 
with mangled names).

llvm-svn: 96465
 2010-02-17 06:48:50 +00:00
Sanjiv Gupta 0f5c8f2339 Removed header files from .h by adding forward decls. 
Renamed PIC16FrameOverlay namespace to PIC16OVERLAY.
Renamed PIC16FrameOverlay class to PIC16Overlay.

llvm-svn: 96463
 2010-02-17 06:46:23 +00:00
Johnny Chen 036b2f6542 Added BFI for disassembly only. 
A8.6.18  BFI - Bitfield insert (Encoding A1)

llvm-svn: 96462
 2010-02-17 06:31:48 +00:00
Chris Lattner 3f48215480 rename and document some arguments so I don't have to keep 
reverse engineering what they are.

llvm-svn: 96456
 2010-02-17 06:07:47 +00:00
Anton Korobeynikov cf1f5b0286 Use pointer-wide encoding for LSDA and FDE on Darwin. 
Hopefully, this will fix the remaining issues seen there.

llvm-svn: 96454
 2010-02-17 05:53:11 +00:00
Chris Lattner b67807e7ef daniel remembered why this was needed. 
llvm-svn: 96440
 2010-02-17 01:55:54 +00:00
Chris Lattner d8716676ea add a comment explaining why darwin/i386 uses ## as a comment. 
It's not clear why this is really required, but it was explicitly
added in r48808 with no real explanation or rdar #.

llvm-svn: 96438
 2010-02-17 01:38:01 +00:00
Sanjiv Gupta 84a85fcb91 Initial implementation of PIC16 Cloner pass. 
This pass is supposed to be run on the linked .bc module.
It traveses the module call graph twice. Once starting from the main function
and marking each reached function as "ML". Again, starting from the ISR
and cloning any reachable function that was marked as "ML". After cloning
the function, it remaps all the call sites in IL functions to call the
cloned functions. 

Currently only marking is being done.

llvm-svn: 96435
 2010-02-17 01:11:53 +00:00
Dan Gohman 12995ba3c0 Make the operand and format specifier match, and print all 
64 bits, fixing a variety of problems.

llvm-svn: 96421
 2010-02-17 00:37:20 +00:00
Bob Wilson 9e89907ed5 Wrap lines to 80 columns and generally try to clean up whitespace and 
indentation.  No functional changes.

llvm-svn: 96418
 2010-02-17 00:31:29 +00:00
Bill Wendling 85e5081c77 Make error statement more personal. 
llvm-svn: 96410
 2010-02-16 22:47:14 +00:00
Chris Lattner afac7dad21 fix rdar://7653908, a crash on a case where we would fold a load 
into a roundss intrinsic, producing a cyclic dag.  The root cause
of this is badness handling ComplexPattern nodes in the old dagisel
that I noticed through inspection.  Eliminate a copy of the of the
code that handled ComplexPatterns by making EmitChildMatchCode call
into EmitMatchCode.

llvm-svn: 96408
 2010-02-16 22:35:06 +00:00
Bob Wilson 37f106e18c Handle tGPR register class in a few more places. This fixes some llvm-gcc 
build failures due to my fix for pr6111.

llvm-svn: 96402
 2010-02-16 22:01:59 +00:00
Johnny Chen 4c444bf606 Add SMC (Secure Monitor Call) system instruction for disassembly only. 
llvm-svn: 96401
 2010-02-16 21:59:54 +00:00
Dale Johannesen 1b967bf0e4 Really reserve R2 on PPC Darwin. PR 6314. 
llvm-svn: 96399
 2010-02-16 21:53:27 +00:00
Jim Grosbach 3e2cad3b1a 80 column cleanup 
llvm-svn: 96393
 2010-02-16 21:23:02 +00:00
Evan Cheng 82b04130cb Look for SSE and instructions of this form: (and x, (build_vector c1,c2,c3,c4)). 
If there exists a use of a build_vector that's the bitwise complement of the mask,
then transform the node to
(and (xor x, (build_vector -1,-1,-1,-1)), (build_vector ~c1,~c2,~c3,~c4)).

Since this transformation is only useful when 1) the given build_vector will
become a load from constpool, and 2) (and (xor x -1), y) matches to a single
instruction, I decided this is appropriate as a x86 specific transformation.
rdar://7323335

llvm-svn: 96389
 2010-02-16 21:09:44 +00:00
Jim Grosbach fba7fce5be Remove trailing whitespace 
llvm-svn: 96388
 2010-02-16 21:07:46 +00:00
David Greene 9641d06809 Add support for emitting non-temporal stores for DAGs marked 
non-temporal.  Fix from r96241 for botched encoding of MOVNTDQ.

Add documentation for !nontemporal metadata.

Add a simpler movnt testcase.

llvm-svn: 96386
 2010-02-16 20:50:18 +00:00
Jim Grosbach 2284ddab56 Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but 
to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.

llvm-svn: 96384
 2010-02-16 20:42:29 +00:00
Jim Grosbach 756ab53e60 Remove redundant setting of Defs. CPSR is already marked by the block level set of Defs. 
llvm-svn: 96383
 2010-02-16 20:35:59 +00:00
Jim Grosbach 0a334d0df9 First step in eliminating the CarryDefIsUnused and CarryDefIsUsed predicates. 
They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.

This patch handles ARM mode. Thumb2 will follow.

llvm-svn: 96381
 2010-02-16 20:17:57 +00:00
Johnny Chen 46c39d4f1f Added for disassembly the following instructions: 
o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)

llvm-svn: 96380
 2010-02-16 20:04:27 +00:00
Bob Wilson 70aa8d0745 Fix pr6111: Avoid using the LR register for the target address of an indirect 
branch in ARM v4 code, since it gets clobbered by the return address before
it is used.  Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.

llvm-svn: 96360
 2010-02-16 17:24:15 +00:00
Duncan Sands cbd43f89ac Introduce isOpaqueTy and use it rather than isa<OpaqueType>. Also, move some 
methods to try to have the type predicates be more logically positioned.

llvm-svn: 96349
 2010-02-16 14:50:09 +00:00
Duncan Sands 19d0b47b1f There are two ways of checking for a given type, for example isa<PointerType>(T) 
and T->isPointerTy().  Convert most instances of the first form to the second form.
Requested by Chris.

llvm-svn: 96344
 2010-02-16 11:11:14 +00:00
Benjamin Kramer d7d8afabd0 Minor warning fixes (semicolons, newline at EOF). 
llvm-svn: 96343
 2010-02-16 10:25:04 +00:00
Chris Lattner 52bfe24e2c mark all the generated node predicates 'const'. 
llvm-svn: 96337
 2010-02-16 07:26:36 +00:00
Chris Lattner 4964ef88c2 make pcrel immediate values relative to the start of the field, 
not the end of the field, fixing rdar://7651978

llvm-svn: 96330
 2010-02-16 05:03:17 +00:00
Sanjiv Gupta adcee844ea The code section for an ISR has a specific address. 
Currently, whether a function is ISR or not is encoded in the section attribute for that function.

llvm-svn: 96322
 2010-02-16 03:41:07 +00:00
Rafael Espindola af25cf825c Drop support for the InReg attribute on the ppc backend. This was used by 
llvm-gcc but has been replaced with pad argument which don't need any
special backend support.

llvm-svn: 96312
 2010-02-16 01:50:18 +00:00
Bob Wilson a945c64b5a Put repeated empty pattern into the AQI instruction class. 
We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.

llvm-svn: 96297
 2010-02-15 23:43:47 +00:00
Anton Korobeynikov c9adb6a463 Fix a silly darwin-only typo introduced during merge. 
llvm-svn: 96289
 2010-02-15 22:38:10 +00:00
Anton Korobeynikov ab663a0bfe Move TLOF implementations to libCodegen to resolve layering violation. 
llvm-svn: 96288
 2010-02-15 22:37:53 +00:00
Anton Korobeynikov 397aecb6d6 Add suffix for stubs, so we won't have name clashes with private symbols. 
llvm-svn: 96286
 2010-02-15 22:36:26 +00:00
Anton Korobeynikov ae4ccc10da Preliminary patch to improve dwarf EH generation - Hooks to return Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there 
llvm-svn: 96285
 2010-02-15 22:35:59 +00:00
Chris Lattner bcbaaba532 revert r96241. It breaks two regression tests, isn't documented, 
and the testcase needs improvement.

llvm-svn: 96265
 2010-02-15 20:53:01 +00:00
Evan Cheng 5e73ff2e3a Split SelectionDAGISel::IsLegalAndProfitableToFold to 
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.

This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.

llvm-svn: 96255
 2010-02-15 19:41:07 +00:00
David Greene 63cedef74b Add support for emitting non-temporal stores for DAGs marked 
non-temporal.

llvm-svn: 96241
 2010-02-15 17:02:56 +00:00
David Greene cbd39c5def Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96239
 2010-02-15 16:57:43 +00:00
David Greene 15478ac350 Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96238
 2010-02-15 16:57:13 +00:00
David Greene 772fc34209 Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96237
 2010-02-15 16:57:02 +00:00
David Greene 87a5abea33 Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96236
 2010-02-15 16:56:53 +00:00
David Greene 2138b0fc90 Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96235
 2010-02-15 16:56:34 +00:00
David Greene 27d044d65d Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96234
 2010-02-15 16:56:22 +00:00
David Greene 3cd87cc5ee Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96233
 2010-02-15 16:56:10 +00:00
David Greene cfa68983e8 Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96232
 2010-02-15 16:55:58 +00:00
David Greene af2931d7bf Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96231
 2010-02-15 16:55:37 +00:00
David Greene 0d0149f5ac Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96230
 2010-02-15 16:55:24 +00:00
David Greene e2e2073303 Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96229
 2010-02-15 16:55:07 +00:00
David Greene ff34702b04 Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96228
 2010-02-15 16:53:33 +00:00
David Greene 68ea4da8cb Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96227
 2010-02-15 16:49:52 +00:00
Duncan Sands 9dff9bec31 Uniformize the names of type predicates: rather than having isFloatTy and 
isInteger, we now have isFloatTy and isIntegerTy.  Requested by Chris!

llvm-svn: 96223
 2010-02-15 16:12:20 +00:00
Andrew Lenharth 6b5e62fb0b Fix changes from r75027 
llvm-svn: 96220
 2010-02-15 15:00:44 +00:00
Chris Lattner d4df64d15f no need to add the instruction count anymore. 
llvm-svn: 96212
 2010-02-15 06:38:41 +00:00
Chris Lattner 4aa57ba3ef mark "addr" as having type "iPTR", eliminating some type comparisons 
in hte generated dag isel fil.

llvm-svn: 96193
 2010-02-14 21:53:19 +00:00
Sanjiv Gupta d6cbe9f23f fixes to pagesel/banksel inserter. 
1. restore these across direct/indirect calls.
2. restore pagesel for any macros with gotos.

llvm-svn: 96175
 2010-02-14 18:27:42 +00:00
Anton Korobeynikov 0a5e0371b0 Forgot to commit the header 
llvm-svn: 96174
 2010-02-14 18:25:41 +00:00
Anton Korobeynikov ce77ce3072 Drop winmcasminfo and use normal AT&T COFF for all windows targets. 
Otherwise AT&T asm printer is used with non-compatible MCAsmInfo and
there is no way to override this behaviour.

llvm-svn: 96165
 2010-02-14 15:19:54 +00:00
Johnny Chen c95a814ec3 Try to factorize the specification of saturating add/subtract operations a bit, 
as suggested by Bob Wilson.

llvm-svn: 96153
 2010-02-14 06:32:20 +00:00
Chris Lattner 406cd61828 teach the encoder to handle pseudo instructions like FP_REG_KILL, 
encoding them into nothing.

llvm-svn: 96110
 2010-02-13 19:16:53 +00:00
Daniel Dunbar 2610a34b15 X86: Move extended MCFixupKinds into X86FixupKinds.h 
llvm-svn: 96088
 2010-02-13 09:27:52 +00:00
Chris Lattner f83726f6ba add encoder support and tests for rdtscp 
llvm-svn: 96076
 2010-02-13 03:42:24 +00:00
Johnny Chen 52a6ab3ba7 Add SETEND and BXJ instructions for disassembly only. 
llvm-svn: 96075
 2010-02-13 02:51:09 +00:00
Sean Callanan 4d804d794f Added the rdtscp instruction to the x86 instruction 
tables.

llvm-svn: 96073
 2010-02-13 02:06:11 +00:00
Evan Cheng 3b065cdb64 Teach MachineFrameInfo to track maximum alignment while stack objects are being 
created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.

llvm-svn: 96069
 2010-02-13 01:56:41 +00:00
Sean Callanan 44232af55a Fixed encodings for invlpg, invept, and invvpid. 
llvm-svn: 96065
 2010-02-13 01:48:34 +00:00
Johnny Chen b0208d2a06 Added a bunch of saturating add/subtract instructions for disassembly only. 
llvm-svn: 96063
 2010-02-13 01:21:01 +00:00
Chris Lattner 509154e0f9 rip out the 'heinous' x86 MCCodeEmitter implementation. 
We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.

llvm-svn: 96059
 2010-02-13 00:49:29 +00:00
Chris Lattner 140caa7240 remove special cases for vmlaunch, vmresume, vmxoff, and swapgs 
fix swapgs to be spelled right.

llvm-svn: 96058
 2010-02-13 00:41:14 +00:00
Daniel Dunbar 224340cabe MC/X86: Push immediate operands as immediates not expressions when possible. 
llvm-svn: 96055
 2010-02-13 00:17:21 +00:00
Chris Lattner 064e926362 Remove special cases for [LM]FENCE, MONITOR and MWAIT from 
encoder and decoder by using new MRM_ forms.

llvm-svn: 96048
 2010-02-12 23:54:57 +00:00
Chris Lattner 1e827fd8ca implement the rest of correct x86-64 encoder support for 
rip-relative addresses, and add a testcase.

llvm-svn: 96040
 2010-02-12 23:24:09 +00:00
Dale Johannesen 626b79d6a6 Add the problem I just hacked around in 96015/96020. 
The solution there produces correct code, but is seriously
deficient in several ways.

llvm-svn: 96039
 2010-02-12 23:16:24 +00:00
Chris Lattner 741580a5bd give MCCodeEmitters access to the current MCContext. 
llvm-svn: 96038
 2010-02-12 23:12:47 +00:00
Chris Lattner 4ad96055fb implement infrastructure to support fixups for rip-rel 
addressing.  This isn't complete because I need an MCContext
to generate new MCExprs.

llvm-svn: 96036
 2010-02-12 23:00:36 +00:00
Johnny Chen 29a9103ee6 Add YIELD, WFE, WFI, and SEV instructions for disassembly only. 
Plus add two formats: MiscFrm and ThumbMiscFrm.  Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.

llvm-svn: 96032
 2010-02-12 22:53:19 +00:00
Chris Lattner d18320361f pull the rip-relative addressing mode case up early. 
llvm-svn: 96031
 2010-02-12 22:47:55 +00:00
Chris Lattner 6c1c0141be fixme resolved! 
llvm-svn: 96029
 2010-02-12 22:39:06 +00:00
Chris Lattner 0055e75249 start producing reloc_pcrel_4byte/reloc_pcrel_1byte for calls. 
llvm-svn: 96028
 2010-02-12 22:36:47 +00:00
Chris Lattner 12455ca03d enhance the immediate field encoding to know whether the immediate 
is pc relative or not, mark call and branches as pcrel.

llvm-svn: 96026
 2010-02-12 22:27:07 +00:00
Evan Cheng 439bda9d3f Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case. 
llvm-svn: 96023
 2010-02-12 22:17:21 +00:00
Dale Johannesen cb39340b81 This should have gone in with 26015, see comments there. 
llvm-svn: 96020
 2010-02-12 22:00:40 +00:00
Johnny Chen dc2051c802 Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only. 
llvm-svn: 96019
 2010-02-12 21:59:23 +00:00
Dale Johannesen 26062150fa When save/restoring CR at prolog/epilog, in a large 
stack frame, the prolog/epilog code was using the same
register for the copy of CR and the address of the save slot.  Oops.
This is fixed here for Darwin, sort of, by reserving R2 for this case.
A better way would be to do the store before the decrement of SP,
which is safe on Darwin due to the red zone.

SVR4 probably has the same problem, but I don't know how to fix it;
there is no red zone and R2 is already used for something else.
I'm going to leave it to someone interested in that target.

Better still would be to rewrite the CR-saving code completely;
spilling each CR subregister individually is horrible code.

llvm-svn: 96015
 2010-02-12 21:35:34 +00:00
Chris Lattner 392be58cad Add support for a union type in LLVM IR. Patch by Talin! 
llvm-svn: 96011
 2010-02-12 20:49:41 +00:00
Johnny Chen bdf1b9520c Add SWP (Swap) and SWPB (Swap Byte) for disassembly only. 
llvm-svn: 96010
 2010-02-12 20:48:24 +00:00
Johnny Chen cf20cbec49 Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. 
llvm-svn: 95999
 2010-02-12 18:55:33 +00:00
Anton Korobeynikov c3c357006e Setup correct data layout to match gcc's expectations on mingw32. 
llvm-svn: 95981
 2010-02-12 15:28:56 +00:00
Anton Korobeynikov c9276dfe04 Cleanup stdcall / fastcall name mangling. 
This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936

llvm-svn: 95980
 2010-02-12 15:28:40 +00:00
Chris Lattner f7477e599f add a bunch of mod/rm encoding types for fixed mod/rm bytes. 
This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.

llvm-svn: 95960
 2010-02-12 02:06:33 +00:00
Chris Lattner 44ac89f517 revert r95949, it turns out that adding new prefixes is not a 
great solution for the disassembler, we'll go with "plan b".

llvm-svn: 95957
 2010-02-12 01:55:31 +00:00
Johnny Chen 905a2d7727 Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, 
MRRC, MRRc2.  For disassembly only.

llvm-svn: 95955
 2010-02-12 01:44:23 +00:00
Daniel Dunbar d7e9212e2d X86: Fix definition for RCL/RCR.*m? operations -- they were getting represented 
with "tied memory operands", which is wrong.

llvm-svn: 95950
 2010-02-12 01:22:03 +00:00
Chris Lattner 336f9abb45 add another bit of space for new kinds of instruction prefixes. 
llvm-svn: 95949
 2010-02-12 01:15:16 +00:00
Nate Begeman c780af6471 Add a missing pattern for movhps so that we get: 
movq	(%ecx,%edx,2), %xmm2
movhps	(%ecx,%eax,2), %xmm2

rather than:

movq     (%eax, %edx, 2), %xmm2		
movq     (%eax, %ebx, 2), %xmm3		
movlhps  %xmm3, %xmm2			

Testcase forthcoming.

llvm-svn: 95948
 2010-02-12 01:10:45 +00:00
Chris Lattner 1572e760bc fix the encodings of monitor and mwait, which were completely 
busted in both encoders.  I'm not bothering to fix it in the
old one at this point.

llvm-svn: 95947
 2010-02-12 01:06:22 +00:00
Chris Lattner b1913c4df9 enhance llvm-mc -show-inst to print the enum of an instruction, like so: 
testb	%al, %al                ## <MCInst #2412 TEST8rr
                                        ##   <MCOperand Reg:2>
                                        ##   <MCOperand Reg:2>>
	jne	LBB1_7                  ## <MCInst #938 JNE_1
                                        ##   <MCOperand Expr:(LBB1_7)>>

llvm-svn: 95935
 2010-02-11 22:57:32 +00:00
Chris Lattner 524138176d add a new MCInstPrinter::getOpcodeName interface, when it is 
implemented, llvm-mc --show-inst now uses it to print the
instruction opcode as well as the number.

llvm-svn: 95929
 2010-02-11 22:39:10 +00:00
Chris Lattner b8af65ed0b improve encoding information for branches. We now know they have 
8 or 32-bit immediates, which allows the new encoder to handle
them.

llvm-svn: 95927
 2010-02-11 21:45:31 +00:00
Chris Lattner ddeceae839 make getFixupKindInfo return a const reference, allowing 
the tables to be const.  Teach MCCodeEmitter to handle
the target-indep kinds so that we don't crash on them.

llvm-svn: 95924
 2010-02-11 21:27:18 +00:00
Chris Lattner 2a34015abc switch to target-indep fixups for 1/2/4/8 byte data. 
llvm-svn: 95920
 2010-02-11 21:17:54 +00:00
Johnny Chen af88c0a84d Added LDRT/LDRBT/STRT/STRBT for disassembly only. 
llvm-svn: 95916
 2010-02-11 20:31:08 +00:00
Chris Lattner 1f298326b0 unbreak the build. 
llvm-svn: 95915
 2010-02-11 19:52:11 +00:00
Chris Lattner 2b0a7a2592 refactor the conditional jump instructions in the .td file to 
use a multipattern that generates both the 1-byte and 4-byte 
versions from the same defm

llvm-svn: 95901
 2010-02-11 19:25:55 +00:00
Johnny Chen 3964059a16 Forgot to also check in this file for vcvt (floating-point <-> fixed-point, VFP). 
Sorry!

llvm-svn: 95892
 2010-02-11 18:47:03 +00:00
Johnny Chen 2588efd071 Added VCVT (between floating-point and fixed-point, VFP) for disassembly. 
A8.6.297

llvm-svn: 95885
 2010-02-11 18:17:16 +00:00
Johnny Chen f40b8e03fb Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose. 
llvm-svn: 95884
 2010-02-11 18:12:29 +00:00
Johnny Chen 9c13dfb5dd Add pseudo instruction TRAP for disassembly, which is encoded according to A5-21 
as the "Permanently UNDEFINED" instruction.

llvm-svn: 95873
 2010-02-11 17:14:31 +00:00
Chris Lattner fbf1f02fee dont' call getX86RegNum on X86::RIP, it doesn't like that. This 
fixes the remaining x86-64 jit failures afaik.

llvm-svn: 95867
 2010-02-11 08:45:56 +00:00
Chris Lattner 5a4ec879bf fix a really nasty bug I introduced in r95693: r12 (and r12d, 
r12b, etc) also encodes to a R/M value of 4, which is just
as illegal as ESP/RSP for the non-sib version an address.

This fixes x86-64 jit miscompilations of a bunch of programs.

llvm-svn: 95866
 2010-02-11 08:41:21 +00:00
Chris Lattner 6bb2463f85 Add and commonize encoder support for all immediates. 
Stub out some dummy fixups to make things work.

We can now emit fixups like this:
	subl	$20, %esp               ## encoding: [0x83,0xec,A]
                                        ##   fixup A - offset: 2, value: 20, kind: fixup_1byte_imm

Emitting $20 as a single-byte fixup to be later resolved
by the assembler is ridiculous of course (vs just emitting
the byte) but this is a failure of the matcher, which 
should be producing an imm of 20, not an MCExpr of 20.

llvm-svn: 95860
 2010-02-11 07:06:31 +00:00
Chris Lattner 167842f90b generalize EmitDisplacementField to work with any size 
and rename it to EmitImmediate.

llvm-svn: 95859
 2010-02-11 06:54:23 +00:00
Chris Lattner 3555993312 eliminate the dead IsPCRel argument. 
llvm-svn: 95858
 2010-02-11 06:51:36 +00:00
Chris Lattner 5a40e6c95c eliminate the dead "PCAdj" logic. 
llvm-svn: 95857
 2010-02-11 06:49:52 +00:00
Mon P Wang 5b77f0dac1 The previous fix of widening divides that trap was too fragile as it depends on custom 
lowering and requires that certain types exist in ValueTypes.h.  Modified widening to
check if an op can trap and if so, the widening algorithm will apply only the op on
the defined elements.  It is safer to do this in widening because the optimizer can't
guarantee removing unused ops in some cases.

llvm-svn: 95823
 2010-02-10 23:37:45 +00:00
Eli Friedman 4d4c6944e9 A few missed optimizations; the last one could have a significant impact on 
code with lots of bitfields.

llvm-svn: 95809
 2010-02-10 21:26:04 +00:00
Daniel Dunbar 3e0c9790f2 MC/X86 AsmMatcher: Fix a use after free spotted by d0k, and de-XFAIL 
x86_32-encoding.s in on expectation of it passing.

llvm-svn: 95806
 2010-02-10 21:19:28 +00:00
Johnny Chen c7e14704d0 Added NOP, DBG, SVC to the instruction table for disassembly purpose. 
llvm-svn: 95784
 2010-02-10 18:02:25 +00:00
Dan Gohman 4a618827de Fix "the the" and similar typos. 
llvm-svn: 95781
 2010-02-10 16:03:48 +00:00
Chris Lattner de03bd0ab4 emit some simple (and probably incorrect) fixups for symbolic 
displacement values.

llvm-svn: 95773
 2010-02-10 06:52:12 +00:00
Chris Lattner f58d0074d7 keep track of what the current byte being emitted is 
throughout the X86 encoder.

llvm-svn: 95771
 2010-02-10 06:41:02 +00:00
Chris Lattner a725d785a9 simplify displacement handling, emit displacements by-operand 
even for the immediate case.  No functionality change.

llvm-svn: 95770
 2010-02-10 06:30:00 +00:00
Daniel Dunbar 605474463f MC: Switch MCFixup to just hold an MCExpr pointer instead of index into the 
MCInst it came from.

llvm-svn: 95767
 2010-02-10 04:47:08 +00:00
Chris Lattner ff68a42121 print all the newlines at the end of instructions with 
OutStreamer.AddBlankLine instead of textually.

llvm-svn: 95734
 2010-02-10 00:36:00 +00:00
Kevin Enderby a7c1d6cfd1 Fix the encoding of the movntdqa X86 instruction. It was missing the 0x66 
prefix which is part of the opcode encoding.

llvm-svn: 95729
 2010-02-10 00:10:31 +00:00
Chris Lattner 482bf69bfe Add ability for MCInstPrinters to add comments for instructions. 
Enhance the x86 backend to show the hex values of immediates in
comments when they are large.  For example:

        movl    $1072693248, 4(%esp)    ## imm = 0x3FF00000

llvm-svn: 95728
 2010-02-10 00:10:18 +00:00
David Greene 509be1fe5e TableGen fragment refactoring. 
Move some utility TableGen defs, classes, etc. into a common file so
they may be used my multiple pattern files.  We will use this for
the AVX specification to help with the transition from the current
SSE specification.

llvm-svn: 95727
 2010-02-09 23:52:19 +00:00
Johnny Chen 1215c774f2 Add VBIF/VBIT for disassembly only. 
A8.6.279

llvm-svn: 95713
 2010-02-09 23:05:23 +00:00
Daniel Dunbar 0e42dc0dac MC/X86: Add a dummy implementation of MCFixup generation for hacky X86 MCCodeEmitter. 
llvm-svn: 95709
 2010-02-09 23:00:03 +00:00
Daniel Dunbar b311a6b3ae MC: First cut at MCFixup, for getting fixup/relocation information out of an MCCodeEmitter. 
llvm-svn: 95708
 2010-02-09 22:59:55 +00:00
Johnny Chen b618f66c5f Added VMRS/VMSR for disassembly only. 
A8.6.335 & A8.6.336

llvm-svn: 95703
 2010-02-09 22:35:38 +00:00
Chris Lattner 8aef06f8eb port encoder enhancements over to the new encoder. 
llvm-svn: 95699
 2010-02-09 21:57:34 +00:00
Chris Lattner 0c3b66cd87 fix X86 encoder to output [disp] only addresses with no SIB byte 
in X86-32 mode.  This is still required in x86-64 mode to avoid
forming [disp+rip] encoding.  Rewrite the SIB byte decision logic
to be actually understandable.

llvm-svn: 95693
 2010-02-09 21:47:19 +00:00
Chris Lattner 45d89644ae revert r95689: getX86RegNum(BaseReg) != N86::ESP is 
a confusing idiom to check for ESP or RSP.

llvm-svn: 95690
 2010-02-09 21:21:26 +00:00
Chris Lattner e464a4d815 simplify. 
llvm-svn: 95689
 2010-02-09 21:00:12 +00:00
Chris Lattner b06015aa69 move target-independent opcodes out of TargetInstrInfo 
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
 2010-02-09 19:54:29 +00:00
Jim Grosbach f7279bd10f Radar 7417921 
tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686
 2010-02-09 19:51:37 +00:00
Johnny Chen 64e0ae8dd4 Added vcvtb/vcvtt (between half-precision and single-precision, VFP). 
For disassembly only.

A8.6.300

llvm-svn: 95669
 2010-02-09 17:21:56 +00:00
Chris Lattner f5f335da37 move PR3462 to here. 
llvm-svn: 95650
 2010-02-09 05:55:14 +00:00
Chris Lattner cf11e602a2 add a note from PR6194 
llvm-svn: 95649
 2010-02-09 05:45:29 +00:00
Chris Lattner d00faaa9c7 Implement x86 asm parsing support for %st and %st(4) 
llvm-svn: 95634
 2010-02-09 00:49:22 +00:00
Chris Lattner 60db0a6ba5 pass stringref by value instead of by const& 
llvm-svn: 95627
 2010-02-09 00:34:28 +00:00
Chris Lattner 187242b3ab move PR6212 to this file. 
llvm-svn: 95624
 2010-02-09 00:11:10 +00:00
Chris Lattner 08297ad15d this is done, tested by CodeGen/ARM/iabs.ll 
llvm-svn: 95609
 2010-02-08 23:48:10 +00:00
Jim Grosbach a570d05228 tighten up eh.setjmp sequence a bit. 
llvm-svn: 95603
 2010-02-08 23:22:00 +00:00
Chris Lattner d9d7186dc0 unify the paths for external symbols and global variables: 
2 files changed, 48 insertions(+), 83 deletions(-)

llvm-svn: 95599
 2010-02-08 23:03:41 +00:00
Chris Lattner 99777dd78f switch the rest of the "@ concatentation" logic in the X86 
backend to use X86MCTargetExpr, simplifying a bunch of code.

llvm-svn: 95595
 2010-02-08 22:52:47 +00:00
Sean Callanan 4d16049c61 Fixed the AT&T AsmLexer to report the proper strings 
for register tokens.  Before, if it encountered
'%al,' it would report 'al,' as the token.  Now it
correctly reports '%al'.

llvm-svn: 95594
 2010-02-08 22:50:23 +00:00
Chris Lattner b8479fb309 switch ELF @GOTOFF references to use X86MCTargetExpr. 
llvm-svn: 95593
 2010-02-08 22:33:55 +00:00
Chris Lattner b6b2164e28 add an x86 implementation of MCTargetExpr for 
representing @GOT and friends.  Use it for
personality references as a first use.

llvm-svn: 95588
 2010-02-08 22:09:08 +00:00
Johnny Chen 9e60686a83 Add VCVTR (between floating-point and integer, VFP) for disassembly purpose. 
The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.

A8.6.295

llvm-svn: 95584
 2010-02-08 22:02:41 +00:00
Dan Gohman 3464a5b609 Rename the PerformTailCallOpt variable to GuaranteedTailCallOpt to reflect 
its current purpose.

llvm-svn: 95564
 2010-02-08 20:27:50 +00:00
Johnny Chen beb1238a85 Add VCMP (VFP floating-point compare without 'E' bit set) for disassembly purpose. 
llvm-svn: 95560
 2010-02-08 19:41:48 +00:00
Johnny Chen c7e606f132 Added VMOVRRS/VMOVSRR to ARMInstrVFP.td for disassembly purpose. 
A8.6.331 VMOV (between two ARM core registers and two single-precision registers)

llvm-svn: 95548
 2010-02-08 17:26:09 +00:00
Torok Edwin 6e29e9d262 Fix x86 JIT stub on MSVC. 
Thanks to Kristaps Straupe for noticing the bug.

llvm-svn: 95537
 2010-02-08 08:37:27 +00:00
Bruno Cardoso Lopes d59cddc098 Add suport for VASTART on Mips. 
llvm-svn: 95506
 2010-02-06 21:00:02 +00:00
Bruno Cardoso Lopes d6fff557db First step towards varargs support in Mips: 
- o32 cc must pass all arguments in A0...A3 and stack regardless
if its type (but respect the alignment).
- Store all variable arguments back to the caller stack.

llvm-svn: 95500
 2010-02-06 19:20:49 +00:00
Evan Cheng ea5c6be766 Run codegen dce pass for all targets at all optimization levels. Previously it's 
only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.

llvm-svn: 95493
 2010-02-06 09:07:11 +00:00
Rafael Espindola 4536b9a904 Fix alignment on ppc linux. This fixes the build of crtend.o 
llvm-svn: 95477
 2010-02-06 03:32:21 +00:00
Evan Cheng d064aefefc Do not emit callseq instructions around sibcalls. This eliminated some unnecessary stack adjustments. 
llvm-svn: 95475
 2010-02-06 03:28:46 +00:00
Jakob Stoklund Olesen 74bb06c0f0 Reintroduce the InlineHint function attribute. 
This time it's for real! I am going to hook this up in the frontends as well.

The inliner has some experimental heuristics for dealing with the inline hint.
When given a -respect-inlinehint option, functions marked with the inline
keyword are given a threshold just above the default for -O3.

We need some experiments to determine if that is the right thing to do.

llvm-svn: 95466
 2010-02-06 01:16:28 +00:00
Bob Wilson 5638c36efd Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex. 
Radar 7614112.

llvm-svn: 95456
 2010-02-06 00:24:38 +00:00
Chris Lattner 9d624778a3 fix incorrect encoding of SBB8mi that Kevin noticed. 
llvm-svn: 95448
 2010-02-05 22:56:11 +00:00
Chris Lattner d91f302a05 fix a case where we'd mis-encode fisttp because of an incorrect (and 
redundant with a correct one) pattern that was added for the disassembler.

llvm-svn: 95446
 2010-02-05 22:49:06 +00:00
Chris Lattner a60af09414 add note. 
llvm-svn: 95445
 2010-02-05 22:48:33 +00:00
Chris Lattner 58827ff98e port X86InstrInfo::determineREX over to the new encoder. 
llvm-svn: 95440
 2010-02-05 22:10:22 +00:00
Chris Lattner 9c9453e582 wire up 64-bit MCCodeEmitter. 
llvm-svn: 95438
 2010-02-05 21:51:35 +00:00
Chris Lattner 86bd194234 really kill off the last MRMInitReg inst, remove logic from encoder. 
llvm-svn: 95437
 2010-02-05 21:34:18 +00:00
Chris Lattner e96d534ce0 lower the last of the MRMInitReg instructions in MCInstLower. 
llvm-svn: 95435
 2010-02-05 21:30:49 +00:00
Chris Lattner 90916287ed teach X86MCInstLower to lower the MOV32r0 and MOV8r0 
pseudo instructions.

llvm-svn: 95433
 2010-02-05 21:21:06 +00:00
Chris Lattner fd7976a432 genericize helpers, use them for MOV16r0/MOV64r0 
llvm-svn: 95432
 2010-02-05 21:15:57 +00:00
Chris Lattner 340b542f8b factor code better in X86MCInstLower::Lower, teach it to 
lower the SETB* instructions.

llvm-svn: 95431
 2010-02-05 21:13:48 +00:00
Chris Lattner 89f7dfff21 implement the rest of the encoding types. 
llvm-svn: 95414
 2010-02-05 19:37:31 +00:00
Chris Lattner 503243559a move functions for decoding X86II values into the X86II namespace. 
llvm-svn: 95410
 2010-02-05 19:24:13 +00:00
Chris Lattner 342762fdba constant propagate a method away. 
llvm-svn: 95408
 2010-02-05 19:20:30 +00:00
Chris Lattner b8d375fd21 change getSizeOfImm and getBaseOpcodeFor to just take 
TSFlags directly instead of a TargetInstrDesc.

llvm-svn: 95405
 2010-02-05 19:16:26 +00:00
Chris Lattner 37166eb419 add some more encodings. 
llvm-svn: 95403
 2010-02-05 19:04:37 +00:00
Johnny Chen a778db9a91 VMOVRRD and VMOVDRR both have Inst{7-6} = 0b00. 
llvm-svn: 95397
 2010-02-05 18:04:58 +00:00
Chris Lattner df84b1aa50 implement the non-relocation forms of memory operands 
llvm-svn: 95368
 2010-02-05 06:16:07 +00:00
Evan Cheng a366c61f77 Handle tail call with byval arguments. 
llvm-svn: 95351
 2010-02-05 02:21:12 +00:00
Chris Lattner 610c84a7c2 start adding MRMDestMem, which requires memory form mod/rm encoding 
to start limping.

llvm-svn: 95350
 2010-02-05 02:18:40 +00:00
Chris Lattner 4f627ba89f Add a few more encodings, we can now encode all of: 
pushl	%ebp
	movl	%esp, %ebp
	movl	$42, %eax
	popl	%ebp
	ret

llvm-svn: 95344
 2010-02-05 01:53:19 +00:00
Evan Phoenix ee9d33b4e7 Disable external stubs for X86-32 and X86-64 
Instruction selection for X86 now can choose an instruction
sequence that will fit any address of any symbol, no matter
the pointer width. X86-64 uses a mov+call-via-reg sequence
for this.

llvm-svn: 95323
 2010-02-04 19:56:59 +00:00
Chris Lattner fb5670fc16 move the PR6214 microoptzn to this file. 
llvm-svn: 95299
 2010-02-04 07:32:01 +00:00
Evan Cheng aeba2250a5 Re-enable x86 tail call optimization. 
llvm-svn: 95295
 2010-02-04 06:47:24 +00:00
Chris Lattner 8228b11abc add support for the sparcv9-*-* target triple to turn on 
64-bit sparc codegen.  Patch by Nathan Keynes!

llvm-svn: 95293
 2010-02-04 06:34:01 +00:00
Evan Cheng 9976832a05 Indirect tail call has to go through a call preserved register since it's after callee register pops. X86 isel lowering is using EAX / R11 and it was somehow adding that to function live out. That prevented the real function return register from being added to the function live out list and bad things happen. 
This fixes 483.xalancbmk (with tail call opt).

llvm-svn: 95280
 2010-02-04 02:40:39 +00:00
Dale Johannesen c337d6538a Rewrite FP constant handling in DEBUG_VALUE yet 
again, so it more or less handles long double.
Restore \n removed in latest MC frenzy.

llvm-svn: 95271
 2010-02-04 01:33:43 +00:00
Chris Lattner 223084d3ac enhance new encoder to support prefixes + RawFrm 
instructions with no operands.  It can now handle

define void @test2() nounwind { ret void }

llvm-svn: 95261
 2010-02-03 21:57:59 +00:00
Chris Lattner 6794f9b9f6 set up some infrastructure, some minor cleanups. 
llvm-svn: 95260
 2010-02-03 21:43:43 +00:00
Evan Cheng f4139067ee Speculatively disable x86 automatic tail call optimization while we track down a self-hosting issue. 
llvm-svn: 95259
 2010-02-03 21:40:40 +00:00
Chris Lattner f914be06d2 stub out a new X86 encoder, which can be tried with 
-enable-new-x86-encoder until its stable.

llvm-svn: 95256
 2010-02-03 21:24:49 +00:00
Chris Lattner 2f750f3b5a rename createX86MCCodeEmitter to more accurately reflect what it creates. 
llvm-svn: 95254
 2010-02-03 21:14:33 +00:00
Kevin Enderby 00f1e6c030 Added support for X86 instruction prefixes so llvm-mc can assemble them. The 
Lock prefix, Repeat string operation prefixes and the Segment override prefixes.
Also added versions of the move string and store string instructions without the
repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of
move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is
happy building the disassembler files.

llvm-svn: 95252
 2010-02-03 21:04:42 +00:00
Chris Lattner 3bcbdb8a28 reapply r95206, this time actually delete the code I'm replacing in the third stub case. 
llvm-svn: 95209
 2010-02-03 06:42:38 +00:00
Chris Lattner 37fad99a05 revert r95206, it is apparently causing bootstrap failure on i386-darwin9 
llvm-svn: 95208
 2010-02-03 06:41:18 +00:00
Chris Lattner 3eef965b06 make the x86 backend emit darwin stubs through mcstreamer 
instead of textually.

llvm-svn: 95206
 2010-02-03 06:21:16 +00:00
Chris Lattner 082f484074 make MachineModuleInfoMachO hold non-const MCSymbol*'s instead 
of const ones.  non-const ones aren't very useful, because you can't
even, say, emit them.

llvm-svn: 95205
 2010-02-03 06:18:30 +00:00
Evan Cheng 40905b4302 Allow all types of callee's to be tail called. But avoid automatic tailcall if the callee is a result of bitcast to avoid losing necessary zext / sext etc. 
llvm-svn: 95195
 2010-02-03 03:28:02 +00:00
Chris Lattner 0b78cc2af5 don't emit \n's at the start of X86AsmPrinter::runOnMachineFunction, 
.o files don't like that.

llvm-svn: 95187
 2010-02-03 01:49:49 +00:00
Chris Lattner aaa1db66a1 rename printMachineInstruction -> EmitInstruction 
llvm-svn: 95184
 2010-02-03 01:41:03 +00:00
Chris Lattner 6f1f865fba print instructions through the mcstreamer. 
llvm-svn: 95181
 2010-02-03 01:16:28 +00:00
Chris Lattner 402a111318 emit instructions through the streamer. 
llvm-svn: 95180
 2010-02-03 01:15:03 +00:00
Chris Lattner 183ef68ef7 Finally eliminate printMCInst and send instructions through 
the streamer.  Demo:

$ cat t.ll 
define i32 @test() nounwind {
  ret i32 42
}
$ llc t.ll -o -
...
_test: 
	movl	$42, %eax
	ret
$ llc t.ll -o t.o -filetype=obj
$ otool -tv t.o 
t.o:
(__TEXT,__text) section
_test:
00000000	movl	$0x0000002a,%eax
00000005	ret

llvm-svn: 95179
 2010-02-03 01:13:25 +00:00
Chris Lattner 996ec840d0 rejigger the world so that EmitInstruction prints the \n at 
the end of the instruction instead of expecting the caller to
do it.  This currently causes the asm-verbose instruction 
comments to be on the next line.

llvm-svn: 95178
 2010-02-03 01:09:55 +00:00
Chris Lattner 41ad1905c9 sink handling of target-independent machine instrs (other 
than DEBUG_VALUE :(  ) into the target indep AsmPrinter.cpp
file.   This allows elimination of the 
NO_ASM_WRITER_BOILERPLATE hack among other things.

llvm-svn: 95177
 2010-02-03 01:00:52 +00:00
Dale Johannesen 55e768c99a Print FPImm a less kludgy way; APFloat.toString seems 
to have some problems anyway.

llvm-svn: 95171
 2010-02-03 00:36:40 +00:00
Evan Cheng 5f238a9650 ByVal frame object size should be that of the byval argument, not the size of the type which is just a pointer. This is not known to break stuff but is wrong nevertheless. 
llvm-svn: 95163
 2010-02-02 23:58:13 +00:00
Jim Grosbach d0a2f52f8f As of r79039, we still try to eliminate the frame pointer on leaf functions, 
even when -disable-fp-elim is specified.

llvm-svn: 95161
 2010-02-02 23:56:14 +00:00