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Author SHA1 Message Date
Evan Cheng b07a29ecd4 Disable folding loads into tail call in 32-bit PIC mode. It can introduce illegal code like this: 
addl    $12, %esp
        popl    %esi
        popl    %edi
        popl    %ebx
        popl    %ebp
        jmpl    *__Block_deallocator-L1$pb(%esi)  # TAILCALL

The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class.

The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit.

llvm-svn: 99455
 2010-03-25 00:10:31 +00:00
Bob Wilson 5b2da69f6d Speculatively revert this to see if it fixes buildbot failures. 
--- Reverse-merging r99440 into '.':
U    test/MC/AsmParser/X86/x86_32-bit_cat.s
U    test/MC/AsmParser/X86/x86_32-encoding.s
U    include/llvm/IntrinsicsX86.td
U    include/llvm/CodeGen/SelectionDAGNodes.h
U    lib/Target/X86/X86InstrSSE.td
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 99450
 2010-03-24 23:26:29 +00:00
Kevin Enderby f5584a7397 Added the Advanced Encryption Standard (AES) Instructions. 
llvm-svn: 99440
 2010-03-24 22:33:33 +00:00
Jim Grosbach 34de7768bf Make the use of the vmla and vmls VFP instructions controllable via cmd line. 
Preliminary testing shows significant performance wins by not using these
instructions.

llvm-svn: 99436
 2010-03-24 22:31:46 +00:00
Kevin Enderby b96eb68497 Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it does 
not get an "Unknown immediate size" assert failure when used.  All instructions 
of this form have an 8-bit immediate.  Also added a test case of an example
instruction that is of this form.

llvm-svn: 99435
 2010-03-24 22:28:42 +00:00
Nate Begeman 2ceb288416 Per chris's request, add some comments. 
llvm-svn: 99434
 2010-03-24 22:19:06 +00:00
Johnny Chen bff23ca690 Trivial formating change. 
llvm-svn: 99428
 2010-03-24 21:25:07 +00:00
Nate Begeman 583e05d8ce BUILD_VECTOR was missing out on some prime opportunities to use SSE 4.1 inserts. 
llvm-svn: 99423
 2010-03-24 20:49:50 +00:00
Johnny Chen e99953ce9c Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm. 
NVCVTFrm will later be used to describe "vcvt with fractional bits".

llvm-svn: 99415
 2010-03-24 19:47:14 +00:00
Johnny Chen da44d5977f Reverted r99376. The disassembler will deal with the 2-reg format of these two 
N3VX instructions using special case code.

llvm-svn: 99409
 2010-03-24 18:46:34 +00:00
Jim Grosbach 07607382d8 tweak the arm if conversion heuristic 
llvm-svn: 99402
 2010-03-24 16:15:14 +00:00
Johnny Chen aa9b1c81a7 Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler. 
llvm-svn: 99376
 2010-03-24 01:29:25 +00:00
Chris Lattner 9096bcdeda Switch INC8r to defining its pattern in terms of X86inc_flag 
and defining the add pattern with Pat<>, eliminating a use of
parallel.

llvm-svn: 99375
 2010-03-24 01:02:12 +00:00
Johnny Chen 9b1f60adec Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm, 
respectively, and add some more comment.

llvm-svn: 99373
 2010-03-24 00:57:50 +00:00
Chris Lattner f9c8bec6c5 switch SDTBinaryArithWithFlags to be a multiple-result node as well. 
llvm-svn: 99370
 2010-03-24 00:49:29 +00:00
Chris Lattner db1ac3cf3e Switch SDTUnaryArithWithFlags to being modeled as a two-result 
ISD node.  The only change in the generated isel code are comments
like:

<                 // Src: (X86dec_flag:i16 GR16:i16:$src)
---
>                 // Src: (X86dec_flag:i16:i32 GR16:i16:$src)

because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case.  Wewt.

llvm-svn: 99369
 2010-03-24 00:47:47 +00:00
Chris Lattner cca83a7aa4 remove 64-bit or_is_add parallels. 
llvm-svn: 99360
 2010-03-24 00:16:52 +00:00
Chris Lattner f5e5004327 remove useless or_is_add parallel's. 
llvm-svn: 99359
 2010-03-24 00:15:23 +00:00
Chris Lattner 237d38e748 reduce nesting. 
llvm-svn: 99358
 2010-03-24 00:12:57 +00:00
Jim Grosbach e0874fa02f try being more permissive for if-conversion on ARM V7. see what the nightly 
test run permformance numbers say as to whether it helps.

llvm-svn: 99355
 2010-03-24 00:03:13 +00:00
Jakob Stoklund Olesen a86ccbfe88 Revert "Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings." 
This reverts commit 99345. It was breaking buildbots.

llvm-svn: 99352
 2010-03-23 23:48:51 +00:00
Chris Lattner 3d9ec39116 [llvm_void_ty] is no longer needed for result types, 
just use an empty result list.

llvm-svn: 99346
 2010-03-23 23:46:07 +00:00
Jakob Stoklund Olesen 31da45b7af Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings. 
This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.

llvm-svn: 99345
 2010-03-23 23:14:44 +00:00
Johnny Chen 6a64320da8 Renamed NVdImmFrm to N1RegModImmFrm. 
llvm-svn: 99344
 2010-03-23 23:09:14 +00:00
Johnny Chen 8a687233e3 Fix typo in the comment for N3VX class. 
llvm-svn: 99328
 2010-03-23 21:35:03 +00:00
Johnny Chen 5be6d5a6a9 Add comment. 
llvm-svn: 99327
 2010-03-23 21:30:12 +00:00
Johnny Chen 5dbf39285d Add New NEON Format NVdVmVCVTFrm. 
Converted some of the NEON vcvt instructions to this format.

llvm-svn: 99326
 2010-03-23 21:25:38 +00:00
Johnny Chen 020023a3fa Add New NEON Format NVdVmImmFrm. 
llvm-svn: 99322
 2010-03-23 20:40:44 +00:00
Evan Cheng b6dee6e015 Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically? 
llvm-svn: 99320
 2010-03-23 20:35:45 +00:00
Bob Wilson 59f75bba24 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes. 
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.

llvm-svn: 99309
 2010-03-23 18:54:46 +00:00
Bob Wilson 3968c6a252 Fix bad indentation, 80-column violations, and trailing whitespace. 
llvm-svn: 99295
 2010-03-23 17:23:59 +00:00
Johnny Chen ac5024bbeb Add New NEON Format NVdImmFrm. 
Ref: A7.4.6 One register and a modified immediate value.

llvm-svn: 99288
 2010-03-23 16:43:47 +00:00
Bob Wilson 9b680e21c0 Rename some instructions to match the corresponding NEON opcode. 
llvm-svn: 99266
 2010-03-23 06:26:18 +00:00
Bob Wilson cc0a2a75a0 Change VST1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

llvm-svn: 99265
 2010-03-23 06:20:33 +00:00
Bob Wilson 340861d29e Change VLD1 instructions for loading Q register values to operate on pairs 
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

llvm-svn: 99261
 2010-03-23 05:25:43 +00:00
Daniel Dunbar 86face8333 MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation. 
llvm-svn: 99249
 2010-03-23 03:13:05 +00:00
Daniel Dunbar a9ae3ae698 MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler. 
llvm-svn: 99248
 2010-03-23 02:36:58 +00:00
Daniel Dunbar e0c43577c1 MC: Add TargetAsmBackend::RelaxInstruction callback, and custom X86 implementation. 
llvm-svn: 99245
 2010-03-23 01:39:09 +00:00
Bob Wilson e60e3ab624 Rename one more NEON instruction that I missed earlier. 
llvm-svn: 99201
 2010-03-22 20:31:39 +00:00
Bob Wilson c286c88db0 Regroup some instructions. No functional change. 
llvm-svn: 99192
 2010-03-22 18:22:06 +00:00
Bob Wilson c53a1125ff Rename some VLD1/VST1 instructions to match the implementation, i.e., the 
corresponding NEON instructions, instead of operation they are currently
used for.

llvm-svn: 99189
 2010-03-22 18:13:18 +00:00
Bob Wilson 98bf5189d7 Remove some redundant instruction classes. 
llvm-svn: 99187
 2010-03-22 18:02:38 +00:00
Bob Wilson debe0bdb13 Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to 
specify encoding bits in arguments instead of "let" expressions.

llvm-svn: 99185
 2010-03-22 16:43:10 +00:00
Jakob Stoklund Olesen 5db5506093 Completely remove Blackfin patterns that thought JustCC was i1. 
Thanks, Chris!

llvm-svn: 99183
 2010-03-22 16:30:04 +00:00
Jeffrey Yasskin 7d116ce2e3 Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters. 
llvm-svn: 99182
 2010-03-22 16:13:21 +00:00
Daniel Dunbar fbd12cc36c MC/X86: Fix an MCOperand link, when we parsing shrld $1,%eax and friends; I believe this fixes the last memory leaks under test/MC. 
llvm-svn: 99102
 2010-03-20 22:36:38 +00:00
Daniel Dunbar fed917e078 TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects. 
llvm-svn: 99097
 2010-03-20 22:36:22 +00:00
Bob Wilson 162242b63b pr6652: Use LDM to restore PC to the return address on ARMv4. 
Patch by John Tytgat!

llvm-svn: 99096
 2010-03-20 22:20:40 +00:00
Bob Wilson ae08a736d6 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") 
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

llvm-svn: 99095
 2010-03-20 22:13:40 +00:00
Bob Wilson 59e5141d44 Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with 
address register writeback.

llvm-svn: 99094
 2010-03-20 21:57:36 +00:00