ce413c8c9f
This file is now dead.
...
llvm-svn: 19333
2005-01-07 07:49:05 +00:00
ff9e21c8d3
Add a new prototype
...
llvm-svn: 19332
2005-01-07 07:48:33 +00:00
ae15482076
Codegen -1 and -0.0 more efficiently. This implements CodeGen/X86/negatize_zero.ll
...
llvm-svn: 19313
2005-01-06 21:19:16 +00:00
1ee6dfa501
1. If a double FP constant must be put into a constant pool, but it can be
...
precisely represented as a float, put it into the constant pool as a
float.
2. Use the cbw/cwd/cdq instructions instead of an explicit SAR for signed
division.
llvm-svn: 19291
2005-01-05 16:30:14 +00:00
0f7e786a6b
Minor optimization to allocate R8 registers in a better order.
...
llvm-svn: 19289
2005-01-05 16:09:16 +00:00
68f28730b7
Revert elimination of global variable hack... still needed.
...
llvm-svn: 19273
2005-01-03 16:34:19 +00:00
d4bb2bbce1
ADC and IMUL are also commutable.
...
llvm-svn: 19264
2005-01-03 01:27:59 +00:00
2cf40e142c
Eliminate the use of the global variable hack in the X86 target that was used
...
to get Visual Studio to link in X86.lib to the executables that need it. There
is another way of doing it.
llvm-svn: 19252
2005-01-02 04:23:12 +00:00
733aac1270
Disable 2->3 address promotion of add and inc instructions to LEA's. In
...
addition to being three address, LEA's don't set the flags.
This fixes 186.crafty.
llvm-svn: 19251
2005-01-02 04:18:17 +00:00
e7228736e0
Add a new method.
...
llvm-svn: 19249
2005-01-02 02:38:18 +00:00
b62b45b3fc
Add support for SETNPr to lower to memory form.
...
llvm-svn: 19248
2005-01-02 02:37:46 +00:00
b7782d77c1
Implement the convertToThreeAddress method, add support for inverting JP/JNP
...
branches.
llvm-svn: 19247
2005-01-02 02:37:07 +00:00
295e45e60e
Two changes here:
...
1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP.
2. Set the isCommutable and isPromotableTo3Address bits on several
instructions.
llvm-svn: 19246
2005-01-02 02:35:46 +00:00
45382d34cc
Remove unused enum value
...
llvm-svn: 19024
2004-12-17 22:41:46 +00:00
db0bf10e4a
Change the sentinal
...
llvm-svn: 19007
2004-12-17 00:46:51 +00:00
979b903916
Create a stack slot for the return address lazily instead of eagerly. This
...
save small amounts of time for functions that don't call llvm.returnaddress
or llvm.frameaddress (which is almost all functions).
llvm-svn: 19006
2004-12-17 00:07:46 +00:00
20d74fd986
Adjust to changes in asmwriter filenames
...
llvm-svn: 18987
2004-12-16 17:33:24 +00:00
c97cac3d32
Set the rounding mode for the X86 FPU to 64-bits instead of 80-bits. We
...
don't support long double anyway, and this gives us FP results closer to
other targets.
This also speeds up 179.art from 41.4s to 18.32s, by eliminating a problem
with extra precision that causes an FP == comparison to fail (leading to
extra loop iterations).
llvm-svn: 18895
2004-12-13 17:23:11 +00:00
17550c456c
Use the target triple to pick this target.
...
llvm-svn: 18830
2004-12-12 17:40:28 +00:00
9d76c236f7
Fix a regression caused by the previous patch
...
llvm-svn: 18449
2004-12-03 05:13:15 +00:00
33660426a5
Spill/restore X86 floating point stack registers with 64-bits of precision
...
instead of 80-bits of precision. This fixes PR467.
This change speeds up fldry on X86 with LLC from 7.32s on apoc to 4.68s.
llvm-svn: 18433
2004-12-02 18:17:31 +00:00
96b14e18bb
Consider 64-bit registers to be FP as well.
...
llvm-svn: 18432
2004-12-02 17:57:21 +00:00
e94b466a8e
Reverting this patch:
...
http://mail.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20041122/021428.html
It broke Mutlisource/Applications/obsequi
llvm-svn: 18407
2004-12-01 18:27:03 +00:00
f9c5dc9fb4
Revamp long/ulong comparisons to use a much more efficient sequence (thanks
...
to Brian and the Sun compiler for pointing out that the obvious works :)
This also enables folding all long comparisons into setcc and branch
instructions: before we could only do == and !=
For example, for:
void test(unsigned long long A, unsigned long long B) {
if (A < B) foo();
}
We now generate:
test:
subl $4, %esp
movl %esi, (%esp)
movl 8(%esp), %eax
movl 12(%esp), %ecx
movl 16(%esp), %edx
movl 20(%esp), %esi
subl %edx, %eax
sbbl %esi, %ecx
jae .LBBtest_2 # UnifiedReturnBlock
.LBBtest_1: # then
call foo
movl (%esp), %esi
addl $4, %esp
ret
.LBBtest_2: # UnifiedReturnBlock
movl (%esp), %esi
addl $4, %esp
ret
Instead of:
test:
subl $12, %esp
movl %esi, 8(%esp)
movl %ebx, 4(%esp)
movl 16(%esp), %eax
movl 20(%esp), %ecx
movl 24(%esp), %edx
movl 28(%esp), %esi
cmpl %edx, %eax
setb %al
cmpl %esi, %ecx
setb %bl
cmove %ax, %bx
testb %bl, %bl
je .LBBtest_2 # UnifiedReturnBlock
.LBBtest_1: # then
call foo
movl 4(%esp), %ebx
movl 8(%esp), %esi
addl $12, %esp
ret
.LBBtest_2: # UnifiedReturnBlock
movl 4(%esp), %ebx
movl 8(%esp), %esi
addl $12, %esp
ret
llvm-svn: 18330
2004-11-29 05:55:24 +00:00
a76f09d0d3
Do not push two return addresses on the stack when we call external functions who have their addresses taken. This fixes test-call.ll
...
llvm-svn: 18134
2004-11-22 22:25:30 +00:00
d68ebaacc0
There is no reason to emit function stubs for direct calls.
...
llvm-svn: 18082
2004-11-21 03:46:06 +00:00
894bf8eed0
ignore generated files
...
llvm-svn: 18073
2004-11-21 00:01:54 +00:00
d02c9eb697
Remove all JIT specific code and switch the code generator over to emitting
...
relocations for global references.
llvm-svn: 18068
2004-11-20 23:55:15 +00:00
b7e72cba22
Implement the X86 JIT interfaces
...
llvm-svn: 18067
2004-11-20 23:54:33 +00:00
8f2ed923ea
Describe the X86 target-specific relocations.
...
llvm-svn: 18066
2004-11-20 23:54:19 +00:00
8c645ec0d3
We implement these interfaces
...
llvm-svn: 18065
2004-11-20 23:53:56 +00:00
4cd9def8b7
Dont' forget to switch back to decimal output
...
llvm-svn: 18010
2004-11-19 20:57:07 +00:00
2004d90f97
Fix a major bug in the signed shr code, which apparently only breaks 134.perl!
...
llvm-svn: 17902
2004-11-16 18:40:52 +00:00
6b7652fae5
Remove a dead function, which died when we got GAS emission working (phwew,
...
hold your nose!)
llvm-svn: 17869
2004-11-16 04:34:29 +00:00
c927072b50
Implement a simple FIXME: if we are emitting a basic block address that has
...
already been emitted, we don't have to remember it and deal with it later,
just emit it directly.
llvm-svn: 17868
2004-11-16 04:30:51 +00:00
2e182fc39b
* Merge some win32 ifdefs together
...
* Get rid of "emitMaybePCRelativeValue", either we want to emit a PC relative
value or not: drop the maybe BS. As it turns out, the only places where
the bool was a variable coming in, the bool was a dynamic constant.
llvm-svn: 17867
2004-11-16 04:21:18 +00:00
9cc2dac7c1
Add debug-only=jit printout, so we see when lazily resolved symbols are
...
set up.
llvm-svn: 17862
2004-11-15 23:16:55 +00:00
34b754d99b
Simplify and rearrange long shift code
...
llvm-svn: 17861
2004-11-15 23:16:34 +00:00
7f245d47c5
GhostLinkage should not reach asm printing stage
...
llvm-svn: 17750
2004-11-14 21:03:49 +00:00
56c4c99cca
Don't print unneeded labels
...
llvm-svn: 17714
2004-11-13 23:27:11 +00:00
049d33a717
shld is a very high latency operation. Instead of emitting it for shifts of
...
two or three, open code the equivalent operation which is faster on athlon
and P4 (by a substantial margin).
For example, instead of compiling this:
long long X2(long long Y) { return Y << 2; }
to:
X3_2:
movl 4(%esp), %eax
movl 8(%esp), %edx
shldl $2, %eax, %edx
shll $2, %eax
ret
Compile it to:
X2:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl %eax, %edx
shrl $30, %edx
leal (%edx,%ecx,4), %edx
shll $2, %eax
ret
Likewise, for << 3, compile to:
X3:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl %eax, %edx
shrl $29, %edx
leal (%edx,%ecx,8), %edx
shll $3, %eax
ret
This matches icc, except that icc open codes the shifts as adds on the P4.
llvm-svn: 17707
2004-11-13 20:48:57 +00:00
ef6bd92a8c
Add missing check
...
llvm-svn: 17706
2004-11-13 20:04:38 +00:00
8d521bb16e
Compile:
...
long long X3_2(long long Y) { return Y+Y; }
int X(int Y) { return Y+Y; }
into:
X3_2:
movl 4(%esp), %eax
movl 8(%esp), %edx
addl %eax, %eax
adcl %edx, %edx
ret
X:
movl 4(%esp), %eax
addl %eax, %eax
ret
instead of:
X3_2:
movl 4(%esp), %eax
movl 8(%esp), %edx
shldl $1, %eax, %edx
shll $1, %eax
ret
X:
movl 4(%esp), %eax
shll $1, %eax
ret
llvm-svn: 17705
2004-11-13 20:03:48 +00:00
04570265a5
Correct the name of stosd for the AT&T syntax:
...
It's stosl (l for long == 32 bit).
llvm-svn: 17658
2004-11-10 04:48:15 +00:00
ab79288e37
Fix compilation problem; make the cast and the LHS be the same type.
...
llvm-svn: 17488
2004-11-05 16:17:06 +00:00
429aaa5855
Quiet VC++ warnings
...
llvm-svn: 17484
2004-11-05 04:50:59 +00:00
99d7bb3378
Fix a warning
...
llvm-svn: 17431
2004-11-02 15:27:57 +00:00
720eb217a7
Add placeholder variable to make Win32 work, applied for Morten Ofstad
...
llvm-svn: 17406
2004-11-01 20:10:20 +00:00
57cbe39d1e
Change Library Names Not To Conflict With Others When Installed
...
llvm-svn: 17286
2004-10-27 23:18:45 +00:00
30d8baea8d
Adjust to changes in Makefile.rules
...
llvm-svn: 17167
2004-10-22 21:02:08 +00:00
c1c320c335
We won't use automake
...
llvm-svn: 17155
2004-10-22 03:35:04 +00:00
6a11a75f31
Initial automake generated Makefile template
...
llvm-svn: 17136
2004-10-18 23:55:41 +00:00
fbc070bfdc
Improve compatibility with VC++, patch contributed by Morten Ofstad!
...
llvm-svn: 17126
2004-10-18 15:54:17 +00:00
068555314b
Don't print stuff out from the code generator. This broke the JIT horribly
...
last night. :) bork!
llvm-svn: 17093
2004-10-17 17:40:50 +00:00
839abf57a6
Rewrite support for cast uint -> FP. In particular, we used to compile this:
...
double %test(uint %X) {
%tmp.1 = cast uint %X to double ; <double> [#uses=1]
ret double %tmp.1
}
into:
test:
sub %ESP, 8
mov %EAX, DWORD PTR [%ESP + 12]
mov %ECX, 0
mov DWORD PTR [%ESP], %EAX
mov DWORD PTR [%ESP + 4], %ECX
fild QWORD PTR [%ESP]
add %ESP, 8
ret
... which basically zero extends to 8 bytes, then does an fild for an
8-byte signed int.
Now we generate this:
test:
sub %ESP, 4
mov %EAX, DWORD PTR [%ESP + 8]
mov DWORD PTR [%ESP], %EAX
fild DWORD PTR [%ESP]
shr %EAX, 31
fadd DWORD PTR [.CPItest_0 + 4*%EAX]
add %ESP, 4
ret
.section .rodata
.align 4
.CPItest_0:
.quad 5728578726015270912
This does a 32-bit signed integer load, then adds in an offset if the sign
bit of the integer was set.
It turns out that this is substantially faster than the preceeding sequence.
Consider this testcase:
unsigned a[2]={1,2};
volatile double G;
void main() {
int i;
for (i=0; i<100000000; ++i )
G += a[i&1];
}
On zion (a P4 Xeon, 3Ghz), this patch speeds up the testcase from 2.140s
to 0.94s.
On apoc, an athlon MP 2100+, this patch speeds up the testcase from 1.72s
to 1.34s.
Note that the program takes 2.5s/1.97s on zion/apoc with GCC 3.3 -O3
-fomit-frame-pointer.
llvm-svn: 17083
2004-10-17 08:01:28 +00:00
112fd88a05
Unify handling of constant pool indexes with the other code paths, allowing
...
us to use index registers for CPI's
llvm-svn: 17082
2004-10-17 07:49:45 +00:00
af19d396ac
Give the asmprinter the ability to print memrefs with a constant pool index,
...
index reg and scale
llvm-svn: 17081
2004-10-17 07:16:32 +00:00
653d8663fe
fold:
...
%X = and Y, constantint
%Z = setcc %X, 0
instead of emitting:
and %EAX, 3
test %EAX, %EAX
je .LBBfoo2_2 # UnifiedReturnBlock
We now emit:
test %EAX, 3
je .LBBfoo2_2 # UnifiedReturnBlock
This triggers 581 times on 176.gcc for example.
llvm-svn: 17080
2004-10-17 06:10:40 +00:00
e4bea062c7
Teach the X86 backend about unreachable and undef. Among other things, we
...
now compile:
'foo() {}' into "ret" instead of "mov EAX, 0; ret"
llvm-svn: 17049
2004-10-16 18:13:05 +00:00
15914416ec
Instruction select globals with offsets better. For example, on this test
...
case:
int C[100];
int foo() {
return C[4];
}
We now codegen:
foo:
mov %EAX, DWORD PTR [C + 16]
ret
instead of:
foo:
mov %EAX, OFFSET C
mov %EAX, DWORD PTR [%EAX + 16]
ret
Other impressive features may be coming later.
This patch is contributed by Jeff Cohen!
llvm-svn: 17011
2004-10-15 05:05:29 +00:00
3b78938b9e
Give the X86 JIT the ability to encode global+disp constants. Patch
...
contributed by Jeff Cohen!
llvm-svn: 17010
2004-10-15 04:53:13 +00:00
19025d5ad0
Give the X86 asm printer the ability to print out addressing modes that have
...
constant displacements from global variables. Patch by Jeff Cohen!
llvm-svn: 17009
2004-10-15 04:44:53 +00:00
df7b984f5a
Allow X86 addressing modes to represent globals with offsets. Patch contributed
...
by Jeff Cohen!
llvm-svn: 17008
2004-10-15 04:43:20 +00:00
ace94df71f
Update to reflect changes in Makefile rules.
...
llvm-svn: 16950
2004-10-13 11:46:52 +00:00
97327f05fc
Initial version of automake Makefile.am file.
...
llvm-svn: 16893
2004-10-10 22:20:40 +00:00
23c8d0b65a
The person who was planning to add SSE support isn't anymore, so disable
...
the -sse* options (to avoid misleading people).
Also, the stack alignment of the target doesn't depend on whether SSE is
eventually implemented, so remove a comment.
llvm-svn: 16860
2004-10-08 22:41:46 +00:00
97ea4206f7
Fix a major regression from the bugfix for 2004-10-08-SelectSetCCFold.llx,
...
which prevented setcc's from being folded into branches. It appears that
conditional branchinst's CC operand is actually operand(2), not operand(0)
as we might expect. :(
llvm-svn: 16859
2004-10-08 22:24:31 +00:00
0be2f50401
Fix bug: 2004-10-08-SelectSetCCFold.llx. Normally this is hidden by the
...
instcombine xform, which is why we didn't notice it before.
llvm-svn: 16840
2004-10-08 16:34:13 +00:00
93867e516a
Remove debugging code, fix encoding problem. This fixes the problems
...
the JIT had last night.
llvm-svn: 16766
2004-10-06 14:31:50 +00:00
6835dedb5b
Codegen signed mod by 2 or -2 more efficiently. Instead of generating:
...
t:
mov %EDX, DWORD PTR [%ESP + 4]
mov %ECX, 2
mov %EAX, %EDX
sar %EDX, 31
idiv %ECX
mov %EAX, %EDX
ret
Generate:
t:
mov %ECX, DWORD PTR [%ESP + 4]
*** mov %EAX, %ECX
cdq
and %ECX, 1
xor %ECX, %EDX
sub %ECX, %EDX
*** mov %EAX, %ECX
ret
Note that the two marked moves are redundant, and should be eliminated by the
register allocator, but aren't.
Compare this to GCC, which generates:
t:
mov %eax, DWORD PTR [%esp+4]
mov %edx, %eax
shr %edx, 31
lea %ecx, [%edx+%eax]
and %ecx, -2
sub %eax, %ecx
ret
or ICC 8.0, which generates:
t:
movl 4(%esp), %ecx #3.5
movl $-2147483647, %eax #3.25
imull %ecx #3.25
movl %ecx, %eax #3.25
sarl $31, %eax #3.25
addl %ecx, %edx #3.25
subl %edx, %eax #3.25
addl %eax, %eax #3.25
negl %eax #3.25
subl %eax, %ecx #3.25
movl %ecx, %eax #3.25
ret #3.25
We would be in great shape if not for the moves.
llvm-svn: 16763
2004-10-06 05:01:07 +00:00
7bd8f1332d
Fix a scary bug with signed division by a power of two. We used to generate:
...
s: ;; X / 4
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, %EAX
sar %ECX, 1
shr %ECX, 30
mov %EDX, %EAX
add %EDX, %ECX
sar %EAX, 2
ret
When we really meant:
s:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, %EAX
sar %ECX, 1
shr %ECX, 30
add %EAX, %ECX
sar %EAX, 2
ret
Hey, this also reduces register pressure too :)
llvm-svn: 16761
2004-10-06 04:19:43 +00:00
147edd2f7e
Codegen signed divides by 2 and -2 more efficiently. In particular
...
instead of:
s: ;; X / 2
movl 4(%esp), %eax
movl %eax, %ecx
shrl $31, %ecx
movl %eax, %edx
addl %ecx, %edx
sarl $1, %eax
ret
t: ;; X / -2
movl 4(%esp), %eax
movl %eax, %ecx
shrl $31, %ecx
movl %eax, %edx
addl %ecx, %edx
sarl $1, %eax
negl %eax
ret
Emit:
s:
movl 4(%esp), %eax
cmpl $-2147483648, %eax
sbbl $-1, %eax
sarl $1, %eax
ret
t:
movl 4(%esp), %eax
cmpl $-2147483648, %eax
sbbl $-1, %eax
sarl $1, %eax
negl %eax
ret
llvm-svn: 16760
2004-10-06 04:02:39 +00:00
e9bfa5a2a4
Add some new instructions. Fix the asm string for sbb32rr
...
llvm-svn: 16759
2004-10-06 04:01:02 +00:00
d1ab378be5
* Prune #includes
...
* Update comments
* Rearrange code a bit
* Finally ELIMINATE the GAS workaround emitter for Intel mode. woot!
llvm-svn: 16647
2004-10-04 07:31:08 +00:00
68ab0beb1b
Add support for emitting AT&T style .s files, and make it the default. Users
...
may now choose their output format with the -x86-asm-syntax={intel|att} flag.
llvm-svn: 16646
2004-10-04 07:24:48 +00:00
8bbde2fb33
Convert some missed patterns to support AT&T style
...
llvm-svn: 16645
2004-10-04 07:23:07 +00:00
2e99778aad
Apparently the GNU assembler has a HUGE hack to be compatible with really
...
old and broken AT&T syntax assemblers. The problem with this hack is that
*SOME* forms of the fdiv and fsub instructions have the 'r' bit inverted.
This was a real pain to figure out, but is trivially easy to support: thus
we are now bug compatible with gas and gcc.
llvm-svn: 16644
2004-10-04 07:08:46 +00:00
af69503332
Fix incorrect suffix
...
llvm-svn: 16642
2004-10-04 05:20:16 +00:00
e1a2826d51
Fix some more missed suffixes and swapped operands
...
llvm-svn: 16641
2004-10-04 01:38:10 +00:00
a488f04f3e
Add missing suffixes to FP instructions for AT&T mode
...
llvm-svn: 16640
2004-10-04 00:43:31 +00:00
5683260187
Add support for the -x86-asm-syntax flag, which can be used to choose between
...
Intel and AT&T style assembly language. The ultimate goal of this is to
eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission
is not fully operational.
llvm-svn: 16639
2004-10-03 20:36:57 +00:00
4e59a14909
Add support to the instruction patterns for AT&T style output, which will
...
hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also
includes changes to wrap the whole file to 80 columns! Woot! :)
Note that the AT&T style output has not been tested at all.
llvm-svn: 16638
2004-10-03 20:35:00 +00:00
89dd63733a
The real x87 floating point registers should not be allocatable. They
...
are only used by the stackifier when transforming FPn register
allocations to the real stack file x87 registers.
llvm-svn: 16472
2004-09-21 21:22:11 +00:00
43bd39e04e
s/ISel/X86ISel/ to have unique class names for debugging via gdb because the C++
...
front-end in gcc does not mangle classes in anonymous namespaces correctly.
llvm-svn: 16469
2004-09-21 18:21:21 +00:00
6614946443
Convert code to compile with vc7.1.
...
Patch contributed by Paolo Invernizzi. Thanks Paolo!
llvm-svn: 16368
2004-09-15 17:06:42 +00:00
4bf01357e1
Fit long lines into 80 cols via creative space elimination
...
llvm-svn: 16353
2004-09-15 01:40:18 +00:00
e8e81a2941
Revamp the Register class, and allow the use of the RegisterGroup class to
...
specify aliases directly in register definitions.
Patch contributed by Jason Eckhardt!
llvm-svn: 16330
2004-09-14 04:17:02 +00:00
72be9ae024
Fix filename: Printer.cpp has become X86AsmPrinter.cpp
...
llvm-svn: 16299
2004-09-12 21:26:04 +00:00
371403193c
Use a shorter form to express implicit use/defs in FpGETRESULT and
...
FpSETRESULT.
llvm-svn: 16247
2004-09-08 18:29:31 +00:00
8b700215ed
A call instruction should implicitely define ST0 since the return
...
value is returned in that register. The pseudo instructions
FpGETRESULT and FpSETRESULT shold also have an implicity use and def
of ST0 repsecitvely.
llvm-svn: 16246
2004-09-08 16:54:54 +00:00
7c16caa336
Changes For Bug 352
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Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.
llvm-svn: 16137
2004-09-01 22:55:40 +00:00
8aca0b494d
Reduce the number of arguments in the instruction builder and make some
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improvements on instruction selection that account for register and frame
index bases.
Patch contributed by Jeff Cohen. Thanks Jeff!
llvm-svn: 16110
2004-08-30 00:13:26 +00:00
dfa9dbceaa
Add -sse[,2,3] arguments to LLC
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llvm-svn: 16018
2004-08-24 08:18:44 +00:00
61e6dbc761
Nuke commented out stuff
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llvm-svn: 16017
2004-08-24 08:18:27 +00:00
5f6556da45
Switch from bytes to bits for alignment for consistency
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llvm-svn: 15974
2004-08-21 20:14:13 +00:00
7c98308013
Reduce uses of getRegClass
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llvm-svn: 15973
2004-08-21 20:13:52 +00:00
10262ab3f1
Rename var
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llvm-svn: 15897
2004-08-18 02:22:55 +00:00
866b58d2ef
Start using alignment output routines from AsmPrinter.
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Changes to make this more similar to the ppc asmprinter
llvm-svn: 15890
2004-08-17 19:25:42 +00:00
b3739ceb6e
Use the AsmPrinter emitGlobalConstant.
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llvm-svn: 15872
2004-08-17 06:48:55 +00:00
9cf46456cb
Start using the AsmPrinter to emit our first class constants. This also
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drops our half-assed support for cygwin, which noone uses and doesn't work
anyway.
llvm-svn: 15839
2004-08-16 23:16:06 +00:00
1d088db15e
Disable the pattern isel
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llvm-svn: 15787
2004-08-15 23:02:17 +00:00
a0b38d3cb1
Code insertion methods now return void instead of an int.
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llvm-svn: 15780
2004-08-15 22:15:11 +00:00
98de1d7795
These methods no longer take a TargetRegisterClass* operand.
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llvm-svn: 15774
2004-08-15 21:56:44 +00:00
a4da0d6294
Eliminate MachineFunction& argument from eliminateFrameIndex in x86 Target. Get MachineFunction from MachineInstruction's parent's parent
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llvm-svn: 15739
2004-08-14 22:05:10 +00:00
eb34c59930
Remove a bunch of ad-hoc target-specific flags that were only used by the
...
old asmprinter.
llvm-svn: 15660
2004-08-11 07:12:04 +00:00
085663c4ec
Remove a dead method
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llvm-svn: 15659
2004-08-11 07:07:14 +00:00
d1bee6ee12
Finally, the entire instruction asmprinter is now generated from tblgen, woo!
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llvm-svn: 15658
2004-08-11 07:02:04 +00:00
a0bafce127
Add asmprintergen support for the last X86 instruction that needs it: pcrelative calls.
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llvm-svn: 15657
2004-08-11 06:59:12 +00:00
5edeb20bbb
This file is long dead
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llvm-svn: 15656
2004-08-11 06:55:12 +00:00
5f4b65e57d
Scrunch memoperands, add a few more for floating point memops
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Eliminate the FPI*m classes, converting them to use FPI instead.
llvm-svn: 15655
2004-08-11 06:50:10 +00:00
b975636f71
Move hacks up
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llvm-svn: 15654
2004-08-11 06:09:55 +00:00
6dd0474edd
Make FPI take asm string and operand list
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llvm-svn: 15653
2004-08-11 05:54:16 +00:00
c52899c3c7
Nuke the Im*i* patterns, by asmprintergenifying all users.
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llvm-svn: 15652
2004-08-11 05:31:07 +00:00
f5c767038a
X86 instructions that read-modify-write memory are not LLVM two-address instructions.
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llvm-svn: 15651
2004-08-11 05:07:25 +00:00
0d7bc2c5da
Get rid of the Im8, Im16, Im32 classes, converting more instructions over to
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asmprintergeneration
llvm-svn: 15650
2004-08-11 04:31:00 +00:00
4dfadc05e6
Remove dead method
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llvm-svn: 15647
2004-08-11 02:26:39 +00:00
09ee05bcdf
Convert asmprinter to new style of instruction printer
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Start asmprintergen'ifying machine instrs with memory operands.
llvm-svn: 15646
2004-08-11 02:25:00 +00:00
ce5fb7db1c
This is purely a formatting patch that gets us closer to the mecca of fitting
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X86InstrInfo.td into 80 columns
llvm-svn: 15629
2004-08-10 21:21:30 +00:00
116fc25d79
Drop the first argument of FPI, and asmprinterify fxch
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llvm-svn: 15628
2004-08-10 21:02:13 +00:00
ead14c1a07
This purely mechanical patch gives the "I" tblgen class operand list and asm
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string operands, and adjusts all users to pass them in instead of using II.
llvm-svn: 15624
2004-08-10 20:17:41 +00:00
c4eb5951d5
Convert Ii32 instructions over to use the asmprinter generator
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llvm-svn: 15621
2004-08-10 19:06:36 +00:00
9f49a91b44
Convert the Ii16 instructions over
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llvm-svn: 15606
2004-08-10 16:22:02 +00:00
4d66b78036
Convert all Ii8 instructions over to the autogenerated asmprinter.
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llvm-svn: 15605
2004-08-10 16:09:54 +00:00
832437255d
Stop using getValues().
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llvm-svn: 15487
2004-08-04 08:44:43 +00:00
4d7af1c680
Fix a warning
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llvm-svn: 15409
2004-08-01 19:31:30 +00:00
2b47c02b64
Convert all I<> instructions to asmformat.
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Delete the 'name' field of all instructions that have asmformats.
llvm-svn: 15403
2004-08-01 09:52:59 +00:00
27fcf976f2
Eliminate 3 of the X86 printImplicit* flags.
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llvm-svn: 15398
2004-08-01 08:23:17 +00:00
e42675f5af
Get rid of 3 of the 4 'printimplicit' flags. Implicit operands are now
...
explicitly listed in the asm string.
llvm-svn: 15397
2004-08-01 08:22:29 +00:00
f6bd77190e
Convert more instructions over to the asmprinter
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llvm-svn: 15396
2004-08-01 08:13:11 +00:00
06cf67ee14
Handle registers a bit more efficiently
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llvm-svn: 15395
2004-08-01 08:12:41 +00:00
ba52a58836
give FP stack registers names
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llvm-svn: 15394
2004-08-01 08:12:13 +00:00
275d98dcbb
Switch more instructions over to using the asmprinter. Fix bugs in the emission
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of in/out instructions (missing %'s on registers).
llvm-svn: 15393
2004-08-01 07:44:35 +00:00
d5540021fc
The tblgen'erated asmparser wants a way to print operands.
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llvm-svn: 15392
2004-08-01 07:43:46 +00:00
9520d20c83
Rename the Printer class -> X86AsmPrinter.
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Include the tablegenerated assembly writer.
llvm-svn: 15389
2004-08-01 06:02:08 +00:00
1d21ea7f1f
Factor a bunch of the rules and add support for generating the asmwriter.
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llvm-svn: 15388
2004-08-01 06:01:32 +00:00
321763358b
Specify an asm string and operands lists for a bunch of instructions.
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This only really covers no-operand instructions so far.
llvm-svn: 15387
2004-08-01 06:01:00 +00:00
6971be8159
Completely disable the pattern isel until it is more substantial.
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llvm-svn: 15380
2004-08-01 03:28:02 +00:00
70d2260eb9
Entirely eliminate all patterns and expanders from this file. We shall go
...
with an incremental approach rather than a revolutionary approach.
llvm-svn: 15379
2004-08-01 03:25:01 +00:00
06bfc0d930
Remove obsolete file
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llvm-svn: 15377
2004-08-01 03:19:28 +00:00
bb635a27a4
Align breaks.
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llvm-svn: 15371
2004-07-31 10:05:44 +00:00
fcef7655fa
Add breaks
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llvm-svn: 15365
2004-07-31 09:53:31 +00:00
ce15f8f4c9
Simplify code a bit.
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llvm-svn: 15364
2004-07-31 09:44:32 +00:00
aaf642103a
Correctly spell 'unconditional'.
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llvm-svn: 15363
2004-07-31 09:41:44 +00:00
f57d78a87d
Implement insertGoto and reverseBranchCondition for the X86.
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llvm-svn: 15362
2004-07-31 09:38:47 +00:00
66a13e230d
Mark barrier instructions. Execution does not fall through uncond branches
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or return intructions.
llvm-svn: 15356
2004-07-31 02:10:53 +00:00
a332a646a0
Fix indentation: should be 2 spaces.
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llvm-svn: 15240
2004-07-26 18:48:58 +00:00
cf7d3af07f
Fix file header as it has been renamed.
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llvm-svn: 15239
2004-07-26 18:45:48 +00:00
bca562404c
Renamed files to have the `X86' prefix for uniqueness purposes.
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All CVS history was renamed, the *,v were copied over. No worries.
llvm-svn: 15238
2004-07-26 18:43:11 +00:00
8d06c43f01
Remove some (LARGE) abandoned code for the release. If this is ever needed
...
again in the future, it can be resurrected out of CVS
llvm-svn: 15112
2004-07-22 21:30:35 +00:00
fac8452acf
Fix cases where we generated horrible code like this:
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mov %EDI, 12
add %EDI, %ECX
mov %ECX, 12
add %ECX, %EDX
mov %EDX, 12
add %EDX, %ESI
instead (really!) generate this:
add %ECX, 12
add %EDX, 12
add %ESI, 12
llvm-svn: 15090
2004-07-21 21:28:26 +00:00
Chris Lattner