Commit Graph

584 Commits

Author SHA1 Message Date
Chad Rosier 295bd43adb The getRegForInlineAsmConstraint function should only accept MVT value types.
llvm-svn: 184642
2013-06-22 18:37:38 +00:00
Bill Wendling a3cd350249 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
llvm-svn: 184360
2013-06-19 21:36:55 +00:00
David Blaikie b735b4d6db DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

llvm-svn: 184067
2013-06-16 20:34:27 +00:00
Bill Wendling 999dacc55b Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183572
2013-06-07 21:04:35 +00:00
Bill Wendling f77190855d Cache the TargetLowering info object as a pointer.
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.

llvm-svn: 183361
2013-06-06 00:43:09 +00:00
Andrew Trick ad6d08ac6f Order CALLSEQ_START and CALLSEQ_END nodes.
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.

Patch by Xiaoyi Guo!

This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.

llvm-svn: 182885
2013-05-29 22:03:55 +00:00
Andrew Trick ef9de2a739 Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

llvm-svn: 182703
2013-05-25 02:42:55 +00:00
Michael J. Spencer df1ecbd734 Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
llvm-svn: 182680
2013-05-24 22:23:49 +00:00
Benjamin Kramer 534d3a4670 Remove the Copied parameter from MemoryObject::readBytes.
There was exactly one caller using this API right, the others were relying on
specific behavior of the default implementation. Since it's too hard to use it
right just remove it and standardize on the default behavior.

Defines away PR16132.

llvm-svn: 182636
2013-05-24 10:54:58 +00:00
Patrik Hagglund b3391b58f7 Removed unused variable, detected by gcc
-Wunused-but-set-variable. Leftover from r181979.

llvm-svn: 181993
2013-05-16 08:37:22 +00:00
Rafael Espindola e3d5e5354e Don't call addFrameMove on XCore.
getExceptionHandlingType is not ExceptionHandling::DwarfCFI on xcore, so
etFrameInstructions is never called. There is no point creating cfi
instructions if they are never used.

llvm-svn: 181979
2013-05-16 04:16:25 +00:00
Rafael Espindola 227144c23c Remove the MachineMove class.
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.

I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.

llvm-svn: 181680
2013-05-13 01:16:13 +00:00
Rafael Espindola 1b09836bc3 Change getFrameMoves to return a const reference.
To add a frame now there is a dedicated addFrameMove which also takes
care of constructing the move itself.

llvm-svn: 181657
2013-05-11 02:38:11 +00:00
Rafael Espindola 140a837acd Remove unused argument.
llvm-svn: 181618
2013-05-10 18:16:59 +00:00
Richard Osborne 1333fa3d68 [XCore] Fix handling of functions where only the LR is spilled.
Previously we only checked if the LR required saving if the frame size was
non zero. However because the caller reserves 1 word for the callee to use
that doesn't count towards our frame size it is possible for the LR to need
saving and for the frame size to be 0.

We didn't hit when the LR needed saving because of a function calls because
the 1 word of stack we must allocate for our callee means the frame size
is always non zero in this case. However we can hit this case if the LR is
clobbered in inline asm.

llvm-svn: 181520
2013-05-09 16:43:42 +00:00
Richard Osborne 4498bd352f [XCore] Add LDAPB instructions.
With the change the disassembler now supports the XCore ISA in its
entirety.

llvm-svn: 181155
2013-05-05 13:36:53 +00:00
Richard Osborne e41cdbd3aa [XCore] Update LDAP to use pcrel_imm.
llvm-svn: 181154
2013-05-05 13:33:10 +00:00
Richard Osborne 8bdfdf717a [XCore] Rename calltarget -> pcrel_imm.
No functionality change.

llvm-svn: 181153
2013-05-05 13:29:02 +00:00
Richard Osborne 4d3514ee94 [XCore] Add BLRB instructions.
llvm-svn: 181152
2013-05-05 13:24:16 +00:00
Richard Osborne 53a04fe2b4 [XCore] Remove '-' from back branch asm syntax.
Instead operands are treated as negative immediates
where the sign bit is implicit in the instruction
encoding.

llvm-svn: 181151
2013-05-05 13:20:22 +00:00
Richard Osborne 2f75a0c0d8 Fix buildbot failure on 64 bit linux due to std::max() having different
operand types.

llvm-svn: 181128
2013-05-04 17:41:01 +00:00
Richard Osborne 0a7abb655b [XCore] Remove unused operand type.
llvm-svn: 181127
2013-05-04 17:30:05 +00:00
Richard Osborne 54ff84a8f8 [XCore] Make use of the target independent global address offset folding.
This let us to remove some custom code that matched constant offsets
from globals at instruction selection time as a special addressing mode.
No intended functionality change.

llvm-svn: 181126
2013-05-04 17:24:33 +00:00
Richard Osborne a282fa5b60 [XCore] Simplify code that checks for an aligned base plus a constant.
The code now makes use of ComputeMaskedBits,
SelectionDAG::isBaseWithConstantOffset and TargetLowering::isGAPlusOffset
where appropriate reducing the amount of logic needed in XCoreISelLowering.
No intended functionality change.

llvm-svn: 181125
2013-05-04 17:17:10 +00:00
Richard Osborne 8bbea9cde7 [XCore] Move lowering of thread local storage to a separate pass.
Thread local storage is not supported by the XMOS linker so we handle
thread local variables by lowering the variable to an array of n elements
(where n is the number of hardware threads per core, currently 8
for all XMOS devices) indexed by the the current thread ID.

Previously this lowering was spread across the XCoreISelLowering and the
XCoreAsmPrinter classes. Moving this to a separate pass should be much
cleaner.

llvm-svn: 181124
2013-05-04 17:01:55 +00:00
Richard Osborne df9e574105 [XCore] Use static relocation model by default.
This allows us to get get rid of a hack in XCoreTargetObjectFile where the
the DataRel* sections were overridden.

llvm-svn: 181116
2013-05-04 16:40:58 +00:00
Michael Liao b53d8963ce ArrayRefize getMachineNode(). No functionality change.
llvm-svn: 179901
2013-04-19 22:22:57 +00:00
Richard Osborne 0c12d1851e [XCore] Add bru instruction.
llvm-svn: 178783
2013-04-04 20:05:35 +00:00
Richard Osborne f18d95f756 [XCore] The RRegs register class is a superset of GRRegs.
At the time when the XCore backend was added there were some issues with
with overlapping register classes but these all seem to be fixed now.
Describing the register classes correctly allow us to get rid of a
codegen only instruction (LDAWSP_lru6_RRegs) and it means we can
disassemble ru6 instructions that use registers above r11.

llvm-svn: 178782
2013-04-04 19:57:46 +00:00
Hal Finkel 9e331c2f9c Allow the register scavenger to spill multiple registers
This patch lets the register scavenger make use of multiple spill slots in
order to guarantee that it will be able to provide multiple registers
simultaneously.

To support this, the RS's API has changed slightly: setScavengingFrameIndex /
getScavengingFrameIndex have been replaced by addScavengingFrameIndex /
isScavengingFrameIndex / getScavengingFrameIndices.

In forthcoming commits, the PowerPC backend will use this capability in order
to implement the spilling of condition registers, and some special-purpose
registers, without relying on r0 being reserved. In some cases, spilling these
registers requires two GPRs: one for addressing and one to hold the value being
transferred.

llvm-svn: 177774
2013-03-22 23:32:27 +00:00
Tom Stellard b1588fc057 DAGCombiner: Use correct value type for checking legality of BR_CC v3
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.

v2:
  - Expand more BR_CC value types for NVPTX

v3:
  - Expand correct BR_CC value types for Hexagon, Mips, and XCore.

llvm-svn: 176694
2013-03-08 15:36:57 +00:00
Michael Liao 6af16fc3b7 Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
  but TLI.getShiftAmountTy() so far only return scalar type. As a
  result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
  TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
  return target-specificed scalar type or the same vector type as the
  1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
  type.

llvm-svn: 176364
2013-03-01 18:40:30 +00:00
Eli Bendersky 8da87163ca Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.

llvm-svn: 175788
2013-02-21 20:05:00 +00:00
Jim Grosbach 341ad3e72a Update TargetLowering ivars for name policy.
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.

No functional change intended.

llvm-svn: 175667
2013-02-20 21:13:59 +00:00
Richard Osborne 53fff94527 [XCore] Add missing 2r instructions.
These instructions are not targeted by the compiler but it is needed for
the MC layer.

llvm-svn: 175407
2013-02-17 22:38:05 +00:00
Richard Osborne f5a3ffcba9 [XCore] Add TSETR instruction.
This instruction is not targeted by the compiler but it is needed for the
MC layer.

llvm-svn: 175406
2013-02-17 22:32:41 +00:00
Richard Osborne 2192615d9f [XCore] Add missing u10 / lu10 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 175404
2013-02-17 20:44:48 +00:00
Richard Osborne 3814491fb1 [XCore] Add missing u6 / lu6 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 175403
2013-02-17 20:43:17 +00:00
Jakob Stoklund Olesen 4af19d0014 Move MRI liveouts to XCore return instructions.
llvm-svn: 174414
2013-02-05 18:21:46 +00:00
Chad Rosier df782d2225 [PEI] Pass the frame index operand number to the eliminateFrameIndex function.
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458

llvm-svn: 174083
2013-01-31 20:02:54 +00:00
Richard Osborne 038d24f90c [XCore] Add missing l2rus instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173634
2013-01-27 22:28:30 +00:00
Richard Osborne f2ecd40929 [XCore] Add missing l2r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173629
2013-01-27 21:26:02 +00:00
Richard Osborne 7fe8f63544 [XCore] Add missing 1r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173624
2013-01-27 20:46:21 +00:00
Richard Osborne 8f56317287 [XCore] Add missing 0r instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173623
2013-01-27 20:42:57 +00:00
Richard Osborne 6b86eec819 Add instruction encodings / disassembly support for l4r instructions.
llvm-svn: 173501
2013-01-25 21:55:32 +00:00
Richard Osborne a520a7dcf3 Use the correct format in the STW / SETPSC instruction names.
llvm-svn: 173494
2013-01-25 21:25:12 +00:00
Richard Osborne 9a228a13c6 Fix order of operands for crc8_l4r
The order in which operands appear in the encoded instruction is different
to order in which they appear in assembly. This changes the XCore backend to
use the instruction encoding order.

llvm-svn: 173493
2013-01-25 21:20:28 +00:00
Richard Osborne a19fa86a70 Add instruction encodings / disassembly support for l5r instructions.
llvm-svn: 173479
2013-01-25 20:20:07 +00:00
Richard Osborne 8ae02d3cef Fix order of operands for l5r instructions.
With this change the operands order matches the order in which the operands
are encoded in the instruction.

llvm-svn: 173477
2013-01-25 20:16:00 +00:00
Richard Osborne ea023fcde1 Use correct mnemonic / instruction name for ldivu.
llvm-svn: 173476
2013-01-25 20:11:26 +00:00