Commit Graph

65 Commits

Author SHA1 Message Date
Akira Hatanaka 8f1caeb0e1 [mips] Partially revert r193641. Stack alignment should not be determined by
the floating point register mode.
 

llvm-svn: 194423
2013-11-11 21:49:03 +00:00
Akira Hatanaka 3048b0248a [mips] Compute stack alignment on the fly.
llvm-svn: 193673
2013-10-30 02:29:43 +00:00
Akira Hatanaka 6b2d841975 [mips] Align the stack to 16-bytes for mfp64.
llvm-svn: 193641
2013-10-29 19:29:03 +00:00
Reed Kotler 91ae9829a9 Make first substantial checkin of my port of ARM constant islands code to Mips.
Before I just ported the shell of the pass. I've tried to keep everything
nearly identical to the ARM version. I think it will be very easy to eventually
merge these two and create a new more general pass that other targets can
use. I have some improvements I would like to make to allow pools to 
be shared across functions and some other things. When I'm all done we
can think about making a more general pass. More to be ported but the
basic mechanism works now almost as good as gcc mips16.

llvm-svn: 193509
2013-10-27 21:57:36 +00:00
Akira Hatanaka 4a3836bed4 [mips] Do not generate INS/EXT nodes if target does not have support for
ins/ext.

llvm-svn: 192330
2013-10-09 23:36:17 +00:00
Akira Hatanaka a8a05be7d6 [mips] Define method MipsSubtarget::enableLongBranchPass.
llvm-svn: 192122
2013-10-07 19:06:57 +00:00
Reed Kotler c03807a3a5 Fix a problem with dual mips16/mips32 mode. When the underlying processor
has hard float, when you compile the mips32 code you have to make sure
that it knows to compile any mips32 routines as hard float. I need to clean
up the way mips16 hard float is specified but I need to first think through
all the details. Mips16 always has a form of soft float, the difference being
whether the underlying hardware has floating point. So it's not really
necessary to pass the -soft-float to llvm since soft-float is always true
for mips16 by virtue of the fact that it will not register floating point
registers. By using this fact, I can simplify the way this is all handled.

llvm-svn: 189690
2013-08-30 19:40:56 +00:00
Akira Hatanaka bfb6624797 [mips] Add support for calling convention CC_MipsO32_FP64, which is used when the
size of floating point registers is 64-bit.

Test case will be added when support for mfhc1 and mthc1 is added.

llvm-svn: 188847
2013-08-20 23:38:40 +00:00
Jack Carter 3a2c2d42b8 [Mips][msa] Added initial MSA support.
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions

Does not correctly prohibit use of both 32-bit FPU registers and MSA together.

Patch by Daniel Sanders

llvm-svn: 188313
2013-08-13 20:54:07 +00:00
Akira Hatanaka 66bc419366 [mips] Implement MipsTargetMachine::getInstrItineraryData().
llvm-svn: 186227
2013-07-12 23:33:22 +00:00
Reed Kotler 783c79446b Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability. 

This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.

Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.

This is needed when returning float, double, single complex, double complex
in the Mips ABI.

Helper functions in libc for mips16 are available to do this.

For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.

Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.

This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.

The only register that is modified is ra in this call.

The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
 

llvm-svn: 181641
2013-05-10 22:25:39 +00:00
Reed Kotler fe94cc3ea0 This is for an experimental option -mips-os16. The idea is to compile all
Mips32 code as Mips16 unless it can't be compiled as Mips 16. For now this
would happen as long as floating point instructions are not needed.
Probably it would also make sense to compile as mips32 if atomic operations
are needed too. There may be other cases too.

A module pass prescans the IR and adds the mips16 or nomips16 attribute
to functions depending on the functions needs.

Mips 16 mode can result in a 40% code compression by utililizing 16 bit
encoding of many instructions.

The hope is for this to replace the traditional gcc way of dealing with
Mips16 code using floating point which involves essentially using soft float
but with a library implemented using mips32 floating point. This gcc 
method also requires creating stubs so that Mips32 code can interact with
these Mips 16 functions that have floating point needs. My conjecture is
that in reality this traditional gcc method would never win over this
new method.

I will be implementing the traditional gcc method also. Some of it is already
done but I needed to do the stubs to finish the work and those required
this mips16/32 mixed mode capability.

I have more ideas for to make this new method much better and I think the old
method will just live in llvm for anyone that needs the backward compatibility
but I don't for what reason that would be needed.

llvm-svn: 179185
2013-04-10 16:58:04 +00:00
Reed Kotler 1595f36d6d This patch enables llvm to switch between compiling for mips32/mips64
and mips16 on a per function basis.

Because this patch is somewhat involved I have provide an overview of the
key pieces of it.

The patch is written so as to not change the behavior of the non mixed
mode. We have tested this a lot but it is something new to switch subtargets
so we don't want any chance of regression in the mainline compiler until
we have more confidence in this.

Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1.
For that reason there are derived versions of the register info, frame info, 
instruction info and instruction selection classes.

Now we register three separate passes for instruction selection.
One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then
one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and
MipsSEISelDAGToDAG.cpp).

When the ModuleISel pass runs, it determines if there is a need to switch
subtargets and if so, the owning pointers in MipsTargetMachine are
appropriately changed.

When 16Isel or SEIsel is run, they will return immediately without doing
any work if the current subtarget mode does not apply to them.

In addition, MipsAsmPrinter needs to be reset on a function basis.

The pass BasicTargetTransformInfo is substituted with a null pass since the
pass is immutable and really needs to be a function pass for it to be
used with changing subtargets. This will be fixed in a follow on patch.

llvm-svn: 179118
2013-04-09 19:46:01 +00:00
Akira Hatanaka 1454ed8ad3 [mips] Remove android calling convention.
This calling convention was added just to handle functions which return vector
of floats. The fix committed in r165585 solves the problem.

llvm-svn: 176530
2013-03-05 23:22:30 +00:00
Jack Carter 428a06cc75 This patch that sets the Mips ELF header flag for
MicroMips architectures. 

Contributer: Zoran Jovanovic
 
llvm-svn: 174360
2013-02-05 09:30:03 +00:00
Jack Carter 7f378104b6 This patch implements runtime Mips specific
setting of ELF header e_flags.

Contributer: Jack Carter
 
llvm-svn: 173884
2013-01-30 02:16:36 +00:00
Jack Carter c1b17ed2e1 This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Support for Mips register information sections.

Mips ELF object files have a section that is dedicated
to register use info. Some of this information such as
the assumed Global Pointer value is used by the linker
in relocation resolution.

The register info file is .reginfo in o32 and .MIPS.options
in 64 and n32 abi files.

This patch contains the changes needed to create the sections,
but leaves the actual register accounting for a future patch.


Contributer: Jack Carter
 
llvm-svn: 172847
2013-01-18 21:20:38 +00:00
Akira Hatanaka c5dc055922 [mips] Delete unused sub-target features.
llvm-svn: 169578
2012-12-07 03:04:05 +00:00
Chandler Carruth 802d755533 Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.

Note that the script is now able to handle all of these headers without
manual edits. =]

llvm-svn: 169224
2012-12-04 07:12:27 +00:00
Akira Hatanaka 3bc1beb696 [mips] Add predicate HasFPIdx for floating-point indexed load instruction
support and use it in place of HasMips32r2Or64.

llvm-svn: 168089
2012-11-15 21:17:13 +00:00
Akira Hatanaka 65ce931f9a Add flags and feature bits for mips dsp.
llvm-svn: 164428
2012-09-21 23:41:49 +00:00
Akira Hatanaka ad4950258b Add register Mips::GP to the list of reserved registers if target is bare-metal
to prevent it from being clobbered. mips uses $gp to access small data section.

This bug was originally reported by Carl Norum.

llvm-svn: 162340
2012-08-22 03:18:13 +00:00
Akira Hatanaka 89d50b3957 Add Android ABI to Mips backend to handle functions returning vectors of four
floats.

llvm-svn: 162008
2012-08-16 03:48:05 +00:00
Akira Hatanaka cdf4fd8267 This patch adds a predicate to existing mips32 and mips64 so that those
instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234
2012-05-22 03:10:09 +00:00
Akira Hatanaka 0faaebf27c This patch adds the register class for MIPS16 as well as the ability for
llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the
mips16 ASE for mips32 by default.

As part of fixing of adding this we discovered some small changes that
need to be made to MipsInstrInfo::storeRegToStackSLot and
MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests
where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead,
per suggestion of Jakob Stoklund Olesen.

Patch by Reed Kotler.

llvm-svn: 156958
2012-05-16 22:19:56 +00:00
Akira Hatanaka 047473e293 Turn on post register allocation scheduler.
llvm-svn: 153554
2012-03-28 00:24:17 +00:00
Jia Liu f54f60f3ce remove blanks, and some code format
llvm-svn: 151625
2012-02-28 07:46:26 +00:00
Akira Hatanaka 330d901ce3 Add support for floating point base register + offset register addressing mode
load and store instructions.

llvm-svn: 151611
2012-02-28 02:55:02 +00:00
David Blaikie a379b18173 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
llvm-svn: 146960
2011-12-20 02:50:00 +00:00
Akira Hatanaka 6de4d12120 Set ABI if it hasn't been set on the command line.
Check if architecture & ABI combination is valid.

llvm-svn: 140230
2011-09-21 02:45:29 +00:00
Akira Hatanaka 6e506eb57d Fix typo.
llvm-svn: 140229
2011-09-21 02:24:25 +00:00
Akira Hatanaka bb49e721b8 Change the names of functions isMips* to hasMips*.
llvm-svn: 140214
2011-09-20 23:53:09 +00:00
Akira Hatanaka 2b37261fd6 Initial Mips64 support. Patch by Liu with some modifications.
llvm-svn: 140178
2011-09-20 20:28:08 +00:00
Akira Hatanaka 3efff6c9f8 Add comment.
llvm-svn: 139699
2011-09-14 17:22:51 +00:00
Akira Hatanaka 8b983d9773 O64 will not be supported.
llvm-svn: 139421
2011-09-09 22:22:48 +00:00
Akira Hatanaka 4444daeec5 Drop support for Mips1 and Mips2.
llvm-svn: 139405
2011-09-09 20:45:50 +00:00
Evan Cheng 1a72add615 Compute feature bits at time of MCSubtargetInfo initialization.
llvm-svn: 134606
2011-07-07 07:07:08 +00:00
Evan Cheng c9c090d7a5 Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
llvm-svn: 134281
2011-07-01 22:36:09 +00:00
Evan Cheng 0d639a28aa Rename TargetSubtarget to TargetSubtargetInfo for consistency.
llvm-svn: 134259
2011-07-01 21:01:15 +00:00
Evan Cheng 54b68e3432 - Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

llvm-svn: 134257
2011-07-01 20:45:01 +00:00
Evan Cheng fe6e405e8c Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!

llvm-svn: 134127
2011-06-30 01:53:36 +00:00
Evan Cheng 8264e272a9 Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
llvm-svn: 134049
2011-06-29 01:14:12 +00:00
Akira Hatanaka e24891251c Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
llvm-svn: 129612
2011-04-15 21:51:11 +00:00
Akira Hatanaka aef55c8801 Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
llvm-svn: 129606
2011-04-15 21:00:26 +00:00
Bruno Cardoso Lopes ed874eff93 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
llvm-svn: 127003
2011-03-04 17:51:39 +00:00
Bruno Cardoso Lopes 03c0330176 Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>
llvm-svn: 118864
2010-11-12 00:38:32 +00:00
Bruno Cardoso Lopes 9c656fe815 Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com)
llvm-svn: 118447
2010-11-08 21:42:32 +00:00
Douglas Gregor 740ab38bb7 Fix a bunch of little errors that Clang complains about when its being pedantic
llvm-svn: 91764
2009-12-19 07:05:23 +00:00
Chris Lattner 68535f7603 reintroduce support for Mips "small" section handling. This is
implemented somewhat differently than before, but it should have
the same functionality and the previous testcase passes again.

llvm-svn: 78900
2009-08-13 06:28:06 +00:00
Chris Lattner 58e8be847c Restore some "small section" support code, reverting my patch from r76936.
llvm-svn: 78894
2009-08-13 05:41:27 +00:00