cc5e54e986
Fix a possible crash on delete of an uninitialized variable.
...
llvm-svn: 77846
2009-08-02 01:25:15 +00:00
321dc97adf
Don't call SectionForGlobal for hasAvailableExternallyLinkage()
...
variables either.
llvm-svn: 77844
2009-08-02 01:18:44 +00:00
a17d2e5c21
don't call SectionForGlobal on declarations, you can't tell the section a
...
declaration will end up in.
llvm-svn: 77843
2009-08-02 01:02:43 +00:00
4e7dfafc03
convert ctors/dtors section to be in TLOF instead of
...
TAI.
llvm-svn: 77842
2009-08-02 00:34:36 +00:00
9836976567
don't override the default of this, the only difference is \t instead of ' '.
...
llvm-svn: 77838
2009-08-02 00:12:20 +00:00
b2aebed2dc
Change MCOperand to use Create style instead of Make style for constructing
...
operands.
llvm-svn: 77837
2009-08-02 00:09:22 +00:00
73d577c933
Make SectionKind::get() private.
...
llvm-svn: 77835
2009-08-02 00:02:44 +00:00
f8d9710b6f
(re)introduce new simpler apis for creation sectionkinds.
...
llvm-svn: 77834
2009-08-01 23:57:16 +00:00
0c40266b5a
Remove "JumpTableDataSection" from TAI, instead, have AsmPrinter
...
compute it based on what it knows. As part of this, rename getSectionForMergeableConstant
to getSectionForConstant because it works for non-mergable constants also.
The only functionality change from this is that Xcore will start dropping
its jump tables into readonly section instead of data section in -static mode.
This should be fine as the linker resolves the relocations. If this is a
problem, let me know and we'll come up with another solution.
llvm-svn: 77833
2009-08-01 23:46:12 +00:00
cc71620c86
give alpha its readonly section. This optimizes alpha, and prevents a
...
testsuite regression with a coming patch.
llvm-svn: 77832
2009-08-01 23:44:04 +00:00
84b453aca4
.rdata == .rodata on mips.
...
llvm-svn: 77827
2009-08-01 23:07:29 +00:00
b1a3309a18
no need to override the default with the default.
...
llvm-svn: 77826
2009-08-01 23:05:25 +00:00
b2bbb61f33
REmove dead fields of TAI.
...
llvm-svn: 77820
2009-08-01 22:40:22 +00:00
5aa4952625
update for rename
...
llvm-svn: 77817
2009-08-01 22:06:53 +00:00
d5c01136ef
fix a fixme by sinking various target-specific directives down into
...
the appropriate subclasses.
llvm-svn: 77815
2009-08-01 21:56:13 +00:00
286326ed24
coff also doesn't have a ReadOnlySection yet, (!)
...
llvm-svn: 77814
2009-08-01 21:49:24 +00:00
bc3d5f5db0
coff doesn't set a .bss seciton, so this is dead.
...
llvm-svn: 77813
2009-08-01 21:48:25 +00:00
26fb277f92
it turns out that isWeak() was basically dead anyway. Kill off SectionInfo :-/
...
llvm-svn: 77812
2009-08-01 21:46:23 +00:00
72c3e7746f
don't use isWeak anymore.
...
llvm-svn: 77810
2009-08-01 21:42:58 +00:00
9139b02cda
Fix typos in comments.
...
llvm-svn: 77806
2009-08-01 21:25:00 +00:00
c9c277ba0f
Change SectionKind to be a property that is true of a *section*, it
...
should have no state that is specific to particular globals in the
section. In this case, it means the removal of the "isWeak" and
"ExplicitSection" bits. MCSection uses the new form of SectionKind.
To handle isWeak, I introduced a new SectionInfo class, which is
SectionKind + isWeak, and it is used by the part of the code generator
that does classification of a specific global.
The ExplicitSection disappears. It is moved onto MCSection as a new
"IsDirective" bit. Since the Name of a section is either a section
or directive, it makes sense to keep this bit in MCSection. Ultimately
the creator of MCSection should canonicalize (e.g.) .text to whatever
the actual section is.
llvm-svn: 77803
2009-08-01 21:11:14 +00:00
c278621694
Minor code cleanups.
...
llvm-svn: 77795
2009-08-01 19:14:37 +00:00
04e3a30a21
Add newline at end of file to remove gcc warning.
...
llvm-svn: 77791
2009-08-01 19:09:44 +00:00
95bad379a9
All MCSections are now required to have a SectionKind.
...
llvm-svn: 77787
2009-08-01 18:25:49 +00:00
e64f48ba8b
Workaround a couple of Darwin assembler bugs.
...
llvm-svn: 77781
2009-08-01 06:13:52 +00:00
edfad17d9b
Minor code simplifications.
...
llvm-svn: 77768
2009-08-01 03:42:59 +00:00
e6e8289d72
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
...
llvm-svn: 77764
2009-08-01 01:43:45 +00:00
d0984565de
The X86 maximal stack alignment calculator preserves the CFG. Also,
...
be more careful about the return value of runOnMachineFunction.
llvm-svn: 77758
2009-08-01 00:31:02 +00:00
6735e10fb0
X86 floating-point passes don't modify the CFG.
...
llvm-svn: 77757
2009-08-01 00:26:16 +00:00
6ab54fdb0a
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
...
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
llvm-svn: 77756
2009-08-01 00:16:10 +00:00
82e72324dd
Use setPreservesAll in X86CodeEmitter.
...
llvm-svn: 77755
2009-07-31 23:44:16 +00:00
a4fc8d94ce
llvm-mc: A few more parsing / match tweaks.
...
- Operands which are just a label should be parsed as immediates, not memory
operands (from the assembler perspective).
- Match a few more flavors of immediates.
- Distinguish match functions for memory operands which don't take a segment
register.
- We match the .s for "hello world" now!
llvm-svn: 77745
2009-07-31 22:22:54 +00:00
95d6325859
t2BR_JT is mov pc, it's 2 byte long, not 4.
...
llvm-svn: 77744
2009-07-31 22:22:22 +00:00
9eb3f88048
Thumb2 movcc need .w suffix.
...
llvm-svn: 77743
2009-07-31 22:21:55 +00:00
63779b8d57
PreferredEHDataFormat is always call with data and global, but this whole
...
thing is #if0'd out anyway. Just simplify the code by reducing the interface.
Not deleting this is essential for Bill's continuing happiness.
llvm-svn: 77736
2009-07-31 21:39:55 +00:00
3ebf848b47
llvm-mc/X86: Sketch match functions for immediates and memory operands.
...
Also, change scale value to always be 1 when unspecified to machine MachineInst
encoding.
llvm-svn: 77728
2009-07-31 20:53:16 +00:00
d25701c114
move emitUsedDirectiveFor to TargetLoweringObjectFile and rename it to
...
indicate that it is a predicate, not an emitter. This eliminates TAI
dependencies on Mangler and GlobalValue.
llvm-svn: 77726
2009-07-31 20:52:39 +00:00
740749b470
remove the PPCLinuxTargetAsmInfo implementation of PreferredEHDataFormat,
...
because it just calls the default impl.
Remove the PPCDarwinTargetAsmInfo version of PreferredEHDataFormat because
it just returns DW_EH_PE_absptr unless on 10.6. However, 10.6 doesn't support
PPC, so the default impl is just fine.
llvm-svn: 77724
2009-07-31 20:43:26 +00:00
5ebf64e075
remove a pointless override.
...
llvm-svn: 77723
2009-07-31 20:36:15 +00:00
5a1acd9912
Move a few more APIs back to 2.5 forms. The only remaining ones left to change back are
...
metadata related, which I'm waiting on to avoid conflicting with Devang.
llvm-svn: 77721
2009-07-31 20:28:14 +00:00
45d7185117
Whitespace and 80-col cleanup.
...
llvm-svn: 77718
2009-07-31 20:07:27 +00:00
4d2c0f9008
switch off of 'Section' onto MCSection. We're not properly using
...
MCSection subclasses yet, but this is a step in the right direction.
llvm-svn: 77708
2009-07-31 18:48:30 +00:00
be8422e8e0
Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align
...
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.
llvm-svn: 77705
2009-07-31 18:35:56 +00:00
f6d0fa3d33
- Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset
...
is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.
llvm-svn: 77701
2009-07-31 18:28:05 +00:00
ca8135379e
Normalize target registration code.
...
llvm-svn: 77692
2009-07-31 18:16:53 +00:00
5ea74d55ce
Reapply r77654 with a fix: MachineFunctionPass's getAnalysisUsage
...
shouldn't do AU.setPreservesCFG(), because even though CodeGen passes
don't modify the LLVM IR CFG, they may modify the MachineFunction CFG,
and passes like MachineLoop are registered with isCFGOnly set to true.
llvm-svn: 77691
2009-07-31 18:16:33 +00:00
51d5b43cda
refactor section construction in TLOF to be through an explicit
...
initialize method, which can be called when an MCContext is available.
llvm-svn: 77687
2009-07-31 17:42:42 +00:00
fc0264a38e
fix PR4650: we only track sizes for certain objects, so only put something
...
into the mergable section if it is one of our special cases. This could
obviously be improved, but this is the minimal fix and restores us to the
previous behavior.
llvm-svn: 77679
2009-07-31 16:17:13 +00:00
b60210ebab
Fix a struct/class mismatch, to silence a MSVC warning.
...
llvm-svn: 77673
2009-07-31 11:35:26 +00:00
7de154708a
define target names for std libcalls.
...
llvm-svn: 77667
2009-07-31 07:35:57 +00:00
5434756585
Revert r77654, it appears to be causing llvm-gcc bootstrap failures, and many
...
failures when building assorted projects with clang.
--- Reverse-merging r77654 into '.':
U include/llvm/CodeGen/Passes.h
U include/llvm/CodeGen/MachineFunctionPass.h
U include/llvm/CodeGen/MachineFunction.h
U include/llvm/CodeGen/LazyLiveness.h
U include/llvm/CodeGen/SelectionDAGISel.h
D include/llvm/CodeGen/MachineFunctionAnalysis.h
U include/llvm/Function.h
U lib/Target/CellSPU/SPUISelDAGToDAG.cpp
U lib/Target/PowerPC/PPCISelDAGToDAG.cpp
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/MachineVerifier.cpp
U lib/CodeGen/MachineFunction.cpp
U lib/CodeGen/PrologEpilogInserter.cpp
U lib/CodeGen/MachineLoopInfo.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
D lib/CodeGen/MachineFunctionAnalysis.cpp
D lib/CodeGen/MachineFunctionPass.cpp
U lib/CodeGen/LiveVariables.cpp
llvm-svn: 77661
2009-07-31 03:02:41 +00:00
b6d6aa2d22
llvm-mc: Match a few X86 instructions.
...
- This is "experimental" code, I am feeling my way around and working out the
best way to do things (and learning tblgen in the process). Comments welcome,
but keep in mind this stuff will change radically.
- This is enough to match "subb" and friends, but not much else. The next step is to
automatically generate the matchers for individual operands.
llvm-svn: 77657
2009-07-31 02:32:59 +00:00
bcb44baa57
Manage MachineFunctions with an analysis Pass instead of the Annotable
...
mechanism. To support this, make MachineFunctionPass a little more
complete.
llvm-svn: 77654
2009-07-31 01:52:50 +00:00
5811ab5cf3
When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.
...
llvm-svn: 77642
2009-07-30 23:29:25 +00:00
5aae45fb6f
Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode.
...
llvm-svn: 77632
2009-07-30 22:45:52 +00:00
0bfc8312c2
Darwin assembler now recognizes "orn", so remove workaround.
...
llvm-svn: 77627
2009-07-30 21:51:41 +00:00
ce774e2383
Darwin assembler now supports "rrx", so remove workaround.
...
llvm-svn: 77625
2009-07-30 21:38:40 +00:00
79c079b478
Cleanup and include code selection for some frame index cases.
...
llvm-svn: 77622
2009-07-30 18:56:48 +00:00
cab137d294
Add missing D* register clobbers for Thumb-2 call.
...
llvm-svn: 77611
2009-07-30 18:01:09 +00:00
703edcc553
Minor whitespace tidiness.
...
llvm-svn: 77602
2009-07-30 17:04:07 +00:00
013f007762
Rename GRAD to GR32_AD, to follow the naming convention of other
...
classes. And define its SubRegClassList.
llvm-svn: 77601
2009-07-30 17:02:08 +00:00
c667b60b93
add a random codegen deficiency.
...
llvm-svn: 77598
2009-07-30 16:08:58 +00:00
92df9c3323
Add a note.
...
llvm-svn: 77584
2009-07-30 08:56:19 +00:00
e62288fdd4
Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch.
...
When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.
This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.
Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.
llvm-svn: 77582
2009-07-30 08:33:02 +00:00
6afdc5e694
Switch obvious clients to Twine instead of utostr (when they were already using
...
a Twine, e.g., for names).
- I am a little ambivalent about this; we don't want the string conversion of
utostr, but using overload '+' mixed with string and integer arguments is
sketchy. On the other hand, this particular usage is something of an idiom.
llvm-svn: 77579
2009-07-30 04:20:37 +00:00
8787861004
Keep track of references to mem(cpy,move,set) and then print only one extern
...
declaration for them.
llvm-svn: 77578
2009-07-30 04:15:15 +00:00
49a6f16b7c
Add a new register class to describe operands that can't be SP,
...
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.
llvm-svn: 77565
2009-07-30 01:56:29 +00:00
652529ec9c
Eliminate a bunch of redundant tables.
...
llvm-svn: 77558
2009-07-30 00:40:42 +00:00
0dbdec8042
Lower a 128-bit BUILD_VECTOR with 2 elements to a pair of INSERT_VECTOR_ELTs.
...
llvm-svn: 77557
2009-07-30 00:31:25 +00:00
da9ba9ec2c
Use array_endof instead of doing it manually.
...
llvm-svn: 77553
2009-07-30 00:10:18 +00:00
e3493a91cc
tbb / tbh instructions only branch forward, not backwards.
...
llvm-svn: 77522
2009-07-29 23:20:20 +00:00
1f58eed638
Add VFP3 D registers to the DPR register class.
...
llvm-svn: 77521
2009-07-29 23:03:41 +00:00
4056ca9568
Move types back to the 2.5 API.
...
llvm-svn: 77516
2009-07-29 22:17:13 +00:00
7667332899
inline the global 'getInstrOperandRegClass' function into its callers
...
now that TargetOperandInfo does the heavy lifting.
llvm-svn: 77508
2009-07-29 21:36:49 +00:00
175bd14967
Make sure Thumb2 uses the right call instructions.
...
llvm-svn: 77507
2009-07-29 21:26:42 +00:00
f3239532cc
1. Introduce a new TargetOperandInfo::getRegClass() helper method
...
and convert code to using it, instead of having lots of things
poke the isLookupPtrRegClass() method directly.
2. Make PointerLikeRegClass contain a 'kind' int, and store it in
the existing regclass field of TargetOperandInfo when the
isLookupPtrRegClass() predicate is set. Make getRegClass pass
this into TargetRegisterInfo::getPointerRegClass(), allowing
targets to have multiple ptr_rc things.
llvm-svn: 77504
2009-07-29 21:10:12 +00:00
ee68a483ec
Give getPointerRegClass() a "kind" value so that targets can
...
support multiple different pointer register classes.
llvm-svn: 77501
2009-07-29 20:31:52 +00:00
0d98d8b8b3
- Fix an obvious copy and paste error.
...
- Darwin Thumb2 call clobbers r9.
llvm-svn: 77500
2009-07-29 20:10:36 +00:00
77268a56ff
Add llvm_unreachable for ... unreachable code!
...
llvm-svn: 77480
2009-07-29 18:14:04 +00:00
cf19885a32
Change Neon VLDn intrinsics to return multiple values instead of really
...
wide vectors. Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct. Adjust tests accordingly.
llvm-svn: 77468
2009-07-29 16:39:22 +00:00
4eb9df073d
more syntactic cleanups.
...
llvm-svn: 77442
2009-07-29 06:33:53 +00:00
5e6e022770
minor smallvector cleanups
...
llvm-svn: 77441
2009-07-29 06:29:53 +00:00
6b6dbb3bd8
whitespace cleanup.
...
llvm-svn: 77438
2009-07-29 05:48:09 +00:00
e033e6da08
mingw uses .data and .text, not _data and _text.
...
llvm-svn: 77435
2009-07-29 05:25:42 +00:00
c5397abb52
fix PR4584 with a trivial patch now that the pieces are in place.
...
llvm-svn: 77434
2009-07-29 05:20:33 +00:00
5034329f8d
pass the mangler down into the various SectionForGlobal methods.
...
No functionality change.
llvm-svn: 77432
2009-07-29 05:09:30 +00:00
8f35574c06
constant prop a utostr.
...
llvm-svn: 77430
2009-07-29 04:55:08 +00:00
7610c57d4b
remove some completely wrong code. 1 is never < 16. It turns out that GCC appears to put strings of any length into the ELF cstring equivalent, so just rip out the code.
...
llvm-svn: 77429
2009-07-29 04:54:38 +00:00
c6d70ae063
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
...
llvm-svn: 77422
2009-07-29 02:18:14 +00:00
99f5534296
Fix comment.
...
llvm-svn: 77415
2009-07-29 01:01:19 +00:00
bef0437d61
Change the "PreferredEHDataFormat" from "absptr" if we're on a Darwin system >
...
Leopard.
llvm-svn: 77414
2009-07-29 00:59:34 +00:00
f7802a33ce
Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower
...
to ptest instruction plus setcc. Revamp ptest instruction. Add test.
llvm-svn: 77407
2009-07-29 00:28:05 +00:00
0033199c50
Match X86 register names to number.
...
llvm-svn: 77404
2009-07-29 00:02:19 +00:00
0830980141
Thumb-2: fix typo that caused incorrect stack elimination for VFP operations and very large stack frames.
...
llvm-svn: 77401
2009-07-28 23:52:33 +00:00
e1fdb0e8ce
Move X86 instruction parsing into X86/AsmParser.
...
llvm-svn: 77384
2009-07-28 22:40:46 +00:00
26cf1e3baf
Output the correct format for Darwin.
...
llvm-svn: 77376
2009-07-28 22:03:50 +00:00
403990ad58
Darwin outputs (DW_EH_PE_pcrel | DW_EH_PE_indirect | DW_EH_PE_sdata4) when we're
...
dealing with Data.
llvm-svn: 77372
2009-07-28 21:53:17 +00:00
a4f43fb5dd
Rename MDNode.h header. It defines MDnode and other metadata classes.
...
New name is Metadata.h.
llvm-svn: 77370
2009-07-28 21:49:47 +00:00
4aa3295a65
Return ConstantVector to 2.5 API.
...
llvm-svn: 77366
2009-07-28 21:19:26 +00:00
c8bed03349
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
...
llvm-svn: 77364
2009-07-28 20:53:24 +00:00
68bb69d6e3
Remove support for ORN to workaround <rdar://problem/7096522>.
...
llvm-svn: 77363
2009-07-28 20:51:25 +00:00
f59ee96a16
Provide generic MCAsmParser when constructing target specific parsers.
...
llvm-svn: 77362
2009-07-28 20:47:52 +00:00
d6b4b29706
more simplifications and cleanup. :)
...
llvm-svn: 77350
2009-07-28 18:48:43 +00:00
c2c7932c64
Change ConstantArray to 2.5 API.
...
llvm-svn: 77347
2009-07-28 18:32:17 +00:00
865c6298d7
Add workaround for <rdar://problem/7098328>.
...
llvm-svn: 77340
2009-07-28 18:15:38 +00:00
513a36b63d
Fix PR4639, a ELF-TLS regression from some of my refactoring.
...
llvm-svn: 77336
2009-07-28 17:57:51 +00:00
a3242e93b7
the apple "ld_classic" linker doesn't support .literal16 in 32-bit
...
mode, and "ld64" (the default linker) falls back to it in -static
mode.
llvm-svn: 77334
2009-07-28 17:50:28 +00:00
e82862e24e
Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
...
llvm-svn: 77329
2009-07-28 17:06:49 +00:00
795b63fb65
fix unused variable warning
...
llvm-svn: 77326
2009-07-28 16:49:19 +00:00
12da273f90
tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.
...
llvm-svn: 77305
2009-07-28 07:38:35 +00:00
73a5119675
Code clean up. No functionality changes.
...
llvm-svn: 77301
2009-07-28 06:24:12 +00:00
780748d565
- More refactoring. This gets rid of all of the getOpcode calls.
...
- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
e1a70c964f
fix a casting problem on the llvm-x86_64-linux tester
...
llvm-svn: 77295
2009-07-28 03:20:34 +00:00
5e693ed07b
Rip all of the global variable lowering logic out of TargetAsmInfo. Since
...
it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.
Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.
This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
CStringSection_. Factor the code better.
5. fixes some bugs in string lowering on ELF targets.
llvm-svn: 77294
2009-07-28 03:13:23 +00:00
697150ec0c
don't copy TargetLowering.
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llvm-svn: 77293
2009-07-28 03:05:40 +00:00
57b51d9f82
ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM.
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llvm-svn: 77275
2009-07-27 23:34:12 +00:00
52d03b252e
llvm-mc: Move AsmLexer::getCurStrVal to StringRef based API.
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- My DFS traversal of LLVM is, at least for now, nearly complete! :)
llvm-svn: 77258
2009-07-27 21:49:56 +00:00
9d0e762c81
hoist MCContext/MCStreamer up to AsmPrinter since we're going to start creating
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MCSections soon instead of Section for all targets, and we need something to
own them.
llvm-svn: 77252
2009-07-27 21:28:04 +00:00
69c464dec4
Move ConstantFP construction back to the 2.5-ish API.
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llvm-svn: 77247
2009-07-27 20:59:43 +00:00
e5b969f6a6
Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).
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llvm-svn: 77242
2009-07-27 19:59:26 +00:00
e7cb8f7987
Sink getSectionPrefixForUniqueGlobal down into the TAI
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implementations that need it, rearrange ELFTAI.
llvm-svn: 77236
2009-07-27 19:14:14 +00:00
375a01c34a
remove dead code.
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llvm-svn: 77233
2009-07-27 19:00:33 +00:00
38b7eee164
More DCE.
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llvm-svn: 77231
2009-07-27 18:48:45 +00:00
0e075e2429
convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions).
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llvm-svn: 77230
2009-07-27 18:44:00 +00:00
18688f431d
Get rid of more dead code.
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llvm-svn: 77227
2009-07-27 18:38:54 +00:00
239ed4b343
Cosmetic change.
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llvm-svn: 77222
2009-07-27 18:31:40 +00:00
8f2ed1bc5a
Clean up.
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llvm-svn: 77221
2009-07-27 18:25:24 +00:00
056c669e93
Get rid of some more getOpcode calls.
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This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.
llvm-svn: 77218
2009-07-27 18:20:05 +00:00
447a8f29ef
Fix build.
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llvm-svn: 77217
2009-07-27 18:18:30 +00:00
96b3d4a2f9
Remove duplicate entries while printing decls for external symbols.
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Some libcall names are same, so they were getting printed twice.
llvm-svn: 77215
2009-07-27 18:04:34 +00:00
e48c85fa8b
add an explanatory comment about why we drop these in readonly and
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not in mergable
llvm-svn: 77210
2009-07-27 17:39:40 +00:00
1814e81e17
make COFF work like ELF and macho, by splitting out into its own
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header even though there is only one COFF target.
llvm-svn: 77204
2009-07-27 16:45:59 +00:00
ff1f401f9b
don't create default text/data sections for all targets.
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llvm-svn: 77203
2009-07-27 16:44:04 +00:00
e25817a138
Apparently alpha doesn't use ElfTargetAsmInfo (?)
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llvm-svn: 77202
2009-07-27 16:42:14 +00:00
007031d1b4
Thumb-2 does not have RSC.
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llvm-svn: 77201
2009-07-27 16:39:05 +00:00
782f242fd7
Add ".w" suffix for wide thumb-2 instructions.
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llvm-svn: 77199
2009-07-27 16:31:55 +00:00
543c83e8f2
inline a method.
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llvm-svn: 77198
2009-07-27 16:27:32 +00:00
3679ad5a77
apparently we have "windows" and "coff", which are different(?)
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llvm-svn: 77197
2009-07-27 16:22:39 +00:00
c51f3394f3
sink text/data section creation down into the target-specific places that
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should know about them. PECoff doesn't share these, and I want all sections
to be created by object-file-specific code.
llvm-svn: 77196
2009-07-27 16:20:58 +00:00
469ae8ac54
32-bit darwin targets support .literal16 too.
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llvm-svn: 77191
2009-07-27 15:44:04 +00:00
86b7255776
Eliminate getNamed/getUnnamedSection, adding a new and unified getOrCreateSection
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instead.
llvm-svn: 77186
2009-07-27 06:17:14 +00:00
149465ea06
Eliminate SectionFlags, just embed a SectionKind into Section
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instead and drive things based off of that.
llvm-svn: 77184
2009-07-27 05:32:16 +00:00
371ec9e810
If CPSR is modified but the def is dead, then it's ok to fold the load / store.
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llvm-svn: 77182
2009-07-27 04:18:04 +00:00
c47e109335
Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.
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llvm-svn: 77181
2009-07-27 03:14:20 +00:00
c8885129d8
Generate a libcall for i8 multiply.
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llvm-svn: 77179
2009-07-27 02:44:46 +00:00
e334b34bfd
fixed incorrect lowering of ISD::SUB node. SUB has only one result value.
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It wasn't caught during tests because we never got a sub generated, (i8 was always getting promoted to int, which in turn was broken into subc/sube). Though the optimizer leaves an i8 sub now.
llvm-svn: 77178
2009-07-27 02:26:06 +00:00
186332f898
Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements.
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llvm-svn: 77175
2009-07-27 00:33:08 +00:00
0e5b149930
Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.
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llvm-svn: 77174
2009-07-27 00:24:36 +00:00
26b51b15ed
Just use a single isMoveInstr to catch all the cases.
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llvm-svn: 77173
2009-07-27 00:05:15 +00:00
faede73a32
Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.
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llvm-svn: 77172
2009-07-26 23:59:01 +00:00
Daniel Dunbar