Commit Graph

8687 Commits

Author SHA1 Message Date
Kostya Kortchinsky 4acdac081d [docs][scudo] Update Scudo documentation
Update the Scudo document to align with the standalone version.
Add some more verbiage about the various component of the
allocator, rework a bit everything.
The build instructions have been updated.
The options and their default values have been updated, and
the `mallopt` ones have been added.

Differential Revision: https://reviews.llvm.org/D100230
2021-04-13 08:41:56 -07:00
Gulfem Savrun Yeniceri e96df3e531 [Passes] Add relative lookup table converter pass
Lookup tables generate non PIC-friendly code, which requires dynamic relocation as described in:
https://bugs.llvm.org/show_bug.cgi?id=45244

This patch adds a new pass that converts lookup tables to relative lookup tables to make them PIC-friendly.

Differential Revision: https://reviews.llvm.org/D94355
2021-04-13 01:29:41 +00:00
Kristof Beyls 28dc50c4b7 [docs] Add Windows/COFF call info 2021-04-12 17:11:25 +02:00
Sushma Unnibhavi 002c6c1187 Typo fix
Reviewed By: dsanders

Differential Revision: https://reviews.llvm.org/D100254
2021-04-11 12:24:27 +05:30
Sushma Unnibhavi e8b0542078 Missing syntax highlighting for LLVM IR in Langref
Added syntax highlighting

Differential Revision: https://reviews.llvm.org/D100125
2021-04-11 12:19:58 +05:30
Paul C. Anagnostopoulos 175b8819f2 [TableGen] [docs] Change title of tblgen.rst to fix man page filename 2021-04-09 09:37:56 -04:00
Konstantin Zhuravlyov 4fae63c612 AMDGPU: Add gfx90c support to code object v2 for backwards compatibility
Differential Revision: https://reviews.llvm.org/D100126
2021-04-08 16:42:43 -04:00
Paul C. Anagnostopoulos 3f919ff250 Revert "[TableGen] Add support for the 'assert' statement in multiclasses"
This reverts commit 3b9a15d910.
2021-04-08 13:58:58 -04:00
Paul C. Anagnostopoulos 3b9a15d910 [TableGen] Add support for the 'assert' statement in multiclasses 2021-04-08 08:36:03 -04:00
Philip Reames 0918f44e26 [docs] Document our norms around reverts
This has come up a few times recently, and I was surprised to notice that we don't have anything in the docs.

This patch deliberately sticks to stuff that is uncontroversial in the community. Everything herein is thought to be widely agreed to by a large majority of the community.  A few things were noted and removed in review which failed this standard, if you spot anything else, please point it out.

Differential Revision: https://reviews.llvm.org/D99305
2021-04-07 21:02:19 -07:00
Tony Tye 2e9465ce2e [NFC][AMDGPU] Correct indentation in AMDGPUUsage.rst
Correct indentation that results in rST syntax error.
2021-04-08 01:00:13 +00:00
Tony Tye 4658cd4c18 [AMDGPU] Update gfx90a memory model support
Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D100070
2021-04-07 22:17:58 +00:00
Paul C. Anagnostopoulos 13a84f21d7 [TableGen] [docs] Correct a couple of mistakes; use 'true' and 'false' in examples
Differential Revision: https://reviews.llvm.org/D99800
2021-04-05 09:15:58 -04:00
Nikita Popov 665065821e [FastISel] Remove kill tracking
This is a followup to D98145: As far as I know, tracking of kill
flags in FastISel is just a compile-time optimization. However,
I'm not actually seeing any compile-time regression when removing
the tracking. This probably used to be more important in the past,
before FastRA was switched to allocate instructions in reverse
order, which means that it discovers kills as a matter of course.

As such, the kill tracking doesn't really seem to serve a purpose
anymore, and just adds additional complexity and potential for
errors. This patch removes it entirely. The primary changes are
dropping the hasTrivialKill() method and removing the kill
arguments from the emitFast methods. The rest is mechanical fixup.

Differential Revision: https://reviews.llvm.org/D98294
2021-04-03 15:50:13 +02:00
Paul C. Anagnostopoulos 7f7f5e2543 [TableGen] [Docs] Add lldb-tblgen to command guide; add 4 guide stubs
Differential Revision: https://reviews.llvm.org/D99605
2021-04-02 09:52:16 -04:00
Tony 4c70f56ec6 [NFC][AMDGPU] Add product names for gfx908 and gfx10 processors
Reviewed By: msearles

Differential Revision: https://reviews.llvm.org/D99781
2021-04-02 00:58:11 +00:00
Jon Roelofs 58cbb222eb [docs] Fix up dead clang-format links after monorepo move. NFC 2021-03-30 14:29:35 -07:00
oToToT 1363fb8ca6
[Docs] Update googletest docs link.
The documentation link of Google Test on GitHub have been moved to the
top-level docs directory.
Thus, the original link is invalid now.

Reviewed By: Pavel Labath

Differential Revision: https://reviews.llvm.org/D99559
2021-03-30 23:20:23 +08:00
Krasimir Georgiev c51e91e046 Revert "[Passes] Add relative lookup table converter pass"
This reverts commit 5178ffc7cf.

Compiling `llvm-profdata` with a compiler build from this produces a
crashing binary.
2021-03-30 14:13:37 +02:00
Nuno Lopes ad613b1497 [docs] remove references to checking out svn repos 2021-03-30 10:00:31 +01:00
Tim Renouf 083b0f1b40 [AMDGPU] Update AMDGPU PAL usage documentation
Change-Id: I65f3edcfe5063551cad5aab0da1374c3a6ccd3a2
2021-03-30 08:33:18 +01:00
Gulfem Savrun Yeniceri 5178ffc7cf [Passes] Add relative lookup table converter pass
Lookup tables generate non PIC-friendly code, which requires dynamic relocation as described in:
https://bugs.llvm.org/show_bug.cgi?id=45244

This patch adds a new pass that converts lookup tables to relative lookup tables to make them PIC-friendly.

Differential Revision: https://reviews.llvm.org/D94355
2021-03-29 21:53:32 +00:00
Paul C. Anagnostopoulos 5f473a04af [TableGen] Add support for the 'assert' statement in class definitions.
Differential Revision: https://reviews.llvm.org/D99275
2021-03-29 09:20:29 -04:00
Matt Arsenault 9a0c9402fa Reapply "OpaquePtr: Turn inalloca into a type attribute"
This reverts commit 07e46367ba.
2021-03-29 08:55:30 -04:00
Oliver Stannard 07e46367ba Revert "Reapply "OpaquePtr: Turn inalloca into a type attribute""
Reverting because test 'Bindings/Go/go.test' is failing on most
buildbots.

This reverts commit fc9df30991.
2021-03-29 11:32:22 +01:00
Matt Arsenault fc9df30991 Reapply "OpaquePtr: Turn inalloca into a type attribute"
This reverts commit 20d5c42e0e.
2021-03-28 13:35:21 -04:00
Nico Weber 20d5c42e0e Revert "OpaquePtr: Turn inalloca into a type attribute"
This reverts commit 4fefed6563.
Broke check-clang everywhere.
2021-03-28 13:02:52 -04:00
Zakk Chen 821547cabb [RISCV][Clang] Update new overloading rules for RVV intrinsics.
RVV intrinsics has new overloading rule, please see
82aac7dad4

Changed:
1. Rename `generic` to `overloaded` because the new rule is not using C11 generic.
2. Change HasGeneric to HasNoMaskedOverloaded because all masked operations
   support overloading api.
3. Add more overloaded tests due to overloading rule changed.

Differential Revision: https://reviews.llvm.org/D99189
2021-03-28 09:04:35 -07:00
Matt Arsenault 4fefed6563 OpaquePtr: Turn inalloca into a type attribute
I think byval/sret and the others are close to being able to rip out
the code to support the missing type case. A lot of this code is
shared with inalloca, so catch this up to the others so that can
happen.
2021-03-28 11:12:23 -04:00
George Burgess IV 5079bc8a23 docs: Adding Google representative to the security group
This adds me as a Google representative for the LLVM security group.

This was proposed, discussed, and voted on in the differential revision
linked below; please see it for more information.

Differential Revision: https://reviews.llvm.org/D99232
2021-03-26 18:55:37 -07:00
Tony 850fcedb27 [NFC][AMDGPU] Corrections to AMD GPU initial kernel launch documentation
Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D99223
2021-03-26 02:05:45 +00:00
Amara Emerson 55533203d7 [GlobalISel] Add G_ROTR and G_ROTL opcodes for rotates.
Differential Revision: https://reviews.llvm.org/D99383
2021-03-25 17:23:30 -07:00
Djordje Todorovic 8420a53324 [Debugify] Expose original debug info preservation check as CC1 option
In order to test the preservation of the original Debug Info metadata
in your projects, a front end option could be very useful, since users
usually report that a concrete entity (e.g. variable x, or function fn2())
is missing debug info. The [0] is an example of running the utility
on GDB Project.

This depends on: D82546 and D82545.

Differential Revision: https://reviews.llvm.org/D82547
2021-03-25 05:29:42 -07:00
Gulfem Savrun Yeniceri 5fbe1fdf17 Revert "[Passes] Add relative lookup table converter pass"
This reverts commit 5fd001a5ff
because it broke clang-with-thin-lto-ubuntu bot.
2021-03-24 18:59:33 +00:00
Gulfem Savrun Yeniceri 5fd001a5ff [Passes] Add relative lookup table converter pass
Lookup tables generate non PIC-friendly code, which requires dynamic relocation as described in:
https://bugs.llvm.org/show_bug.cgi?id=45244

This patch adds a new pass that converts lookup tables to relative lookup tables to make them PIC-friendly.

Differential Revision: https://reviews.llvm.org/D94355
2021-03-24 17:31:18 +00:00
Vinicius Tinti 804ff7f293 [llvm-objdump] Implement --prefix-strip option
The option `--prefix-strip` is only used when `--prefix` is not empty.
It removes N initial directories from absolute paths before adding the
prefix.

This matches GNU's objdump behavior.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D96679
2021-03-24 13:22:35 +00:00
Andrew Savonichev 292da93d59 [MCA] Disable RCU for InOrderIssueStage
This is a follow-up for:
D98604 [MCA] Ensure that writes occur in-order

When instructions are aligned by the order of writes, they retire
in-order naturally. There is no need for an RCU, so it is disabled.

Differential Revision: https://reviews.llvm.org/D98628
2021-03-24 13:54:04 +03:00
Bruno Cardoso Lopes 431e3138a1 [CGAtomic] Lift stronger requirements on cmpxch and support acquire failure mode
- Fix `emitAtomicCmpXchgFailureSet` to support release/acquire (succ/fail) memory order.
- Remove stronger checks for cmpxch.

Effectively, this addresses http://wg21.link/p0418

Differential Revision: https://reviews.llvm.org/D98995
2021-03-23 16:45:37 -07:00
Tony c181724a9b [NFC][AMDGPU] Reserve AMD GPU ELF machine number 0x41
Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D99196
2021-03-23 17:53:02 +00:00
Fraser Cormack 38cf50bc04 [LangRef] Fix typos in the vector-type memory layout section
Reviewed By: bjope

Differential Revision: https://reviews.llvm.org/D99163
2021-03-23 12:28:50 +00:00
David Sherwood 748ae5281d [IR][SVE] Add new llvm.experimental.stepvector intrinsic
This patch adds a new llvm.experimental.stepvector intrinsic,
which takes no arguments and returns a linear integer sequence of
values of the form <0, 1, ...>. It is primarily intended for
scalable vectors, although it will work for fixed width vectors
too. It is intended that later patches will make use of this
new intrinsic when vectorising induction variables, currently only
supported for fixed width. I've added a new CreateStepVector
method to the IRBuilder, which will generate a call to this
intrinsic for scalable vectors and fall back on creating a
ConstantVector for fixed width.

For scalable vectors this intrinsic is lowered to a new ISD node
called STEP_VECTOR, which takes a single constant integer argument
as the step. During lowering this argument is set to a value of 1.
The reason for this additional argument at the codegen level is
because in future patches we will introduce various generic DAG
combines such as

  mul step_vector(1), 2 -> step_vector(2)
  add step_vector(1), step_vector(1) -> step_vector(2)
  shl step_vector(1), 1 -> step_vector(2)
  etc.

that encourage a canonical format for all targets. This hopefully
means all other targets supporting scalable vectors can benefit
from this too.

I've added cost model tests for both fixed width and scalable
vectors:

  llvm/test/Analysis/CostModel/AArch64/neon-stepvector.ll
  llvm/test/Analysis/CostModel/AArch64/sve-stepvector.ll

as well as codegen lowering tests for fixed width and scalable
vectors:

  llvm/test/CodeGen/AArch64/neon-stepvector.ll
  llvm/test/CodeGen/AArch64/sve-stepvector.ll

See this thread for discussion of the intrinsic:
https://lists.llvm.org/pipermail/llvm-dev/2021-January/147943.html
2021-03-23 10:43:35 +00:00
Tony 1e04706adb [AMDGPU] Reserve ELF code
Reserve AMD GPU ELF machine code 0x040.

Minor AMDGPUUsage format consistency change.

Reviewed By: kzhuravl

Differential Revision: https://reviews.llvm.org/D99122
2021-03-23 04:30:38 +00:00
Gulfem Savrun Yeniceri e3a6d70c68 Revert "[Passes] Add relative lookup table converter pass"
This reverts commit 78a65cd945 which
caused buildbot failures.
2021-03-23 00:43:16 +00:00
Gulfem Savrun Yeniceri fc069f0165 [doc] Fix typo in rel lookup table converter pass
Add additonal hypens to match the title size that was introduced in 78a65cd.
2021-03-22 23:25:06 +00:00
Gulfem Savrun Yeniceri 78a65cd945 [Passes] Add relative lookup table converter pass
Lookup tables generate non PIC-friendly code, which requires dynamic relocation as described in:
https://bugs.llvm.org/show_bug.cgi?id=45244

This patch adds a new pass that converts lookup tables to relative lookup tables to make them PIC-friendly.

Differential Revision: https://reviews.llvm.org/D94355
2021-03-22 22:09:02 +00:00
Bradley Smith 48f5a392cb [IR] Add vscale_range IR function attribute
This attribute represents the minimum and maximum values vscale can
take. For now this attribute is not hooked up to anything during
codegen, this will be added in the future when such codegen is
considered stable.

Additionally hook up the -msve-vector-bits=<x> clang option to emit this
attribute.

Differential Revision: https://reviews.llvm.org/D98030
2021-03-22 12:05:06 +00:00
Kristof Beyls ba0a28596e [docs] GettingInvolved: split out flang and openmp meeting series
Split out the flang and openmp meeting series, as each has a separate
canonical page where the information is maintained.
As part of that, also call out the alias analysis series separately as
it doesn't seem to be relevant for just flang.

Differential Revision: https://reviews.llvm.org/D99012
2021-03-22 09:25:57 +01:00
Jessica Paquette 4773dd5ba9 [GlobalISel] Add G_SBFX + G_UBFX (bitfield extraction opcodes)
There is a bunch of similar bitfield extraction code throughout *ISelDAGToDAG.

E.g, ARMISelDAGToDAG, AArch64ISelDAGToDAG, and AMDGPUISelDAGToDAG all contain
code that matches a bitfield extract from an and + right shift.

Rather than duplicating code in the same way, this adds two opcodes:

- G_UBFX (unsigned bitfield extract)
- G_SBFX (signed bitfield extract)

They work like this

```
%x = G_UBFX %y, %lsb, %width
```

Where `lsb` and `width` are

- The least-significant bit of the extraction
- The width of the extraction

This will extract `width` bits from `%y`, starting at `lsb`. G_UBFX zero-extends
the result, while G_SBFX sign-extends the result.

This should allow us to use the combiner to match the bitfield extraction
patterns rather than duplicating pattern-matching code in each target.

Differential Revision: https://reviews.llvm.org/D98464
2021-03-19 14:37:19 -07:00
Bjorn Pettersson 5737010a79 [LangRef] Describe memory layout for vectors types
There are a couple of caveats when it comes to how vectors are
stored to memory, and thereby also how bitcast between vector
and integer types work, in LLVM IR. Specially in relation to
endianess. This patch is an attempt to document such things.

Reviewed By: nlopes

Differential Revision: https://reviews.llvm.org/D94964
2021-03-19 19:00:37 +01:00
Christian Kühnel 4532ab76c9 propose Chocolately as package manager
Installing the Unix tools on Windows is quite painful. To make things easier,
I explained how to use a package manager or a Docker image.

Note: This still uses the GNUWin tools as explained on this page. Once we
replace these with something else, we would also need to update the
installation commands.

Differential Revision: https://reviews.llvm.org/D97387
2021-03-19 16:15:18 +01:00