If a base object is at a 0 offset, RegionStoreManager may find a lazy
binding for the entire object, then try to attach a FieldRegion or
grandparent CXXBaseObjectRegion on top of that (skipping the intermediate
region). We now preserve as many layers of base object regions necessary
to make the types match.
<rdar://problem/13239840>
llvm-svn: 175556
In my previous commit:
"Merge a f32 bitcast of a v2i32 extractelt
A vectorized sitfp on doubles will get scalarized to a sequence of an
extract_element of <2 x i32>, a bitcast to f32 and a sitofp.
Due to the the extract_element, and the bitcast we will uneccessarily generate
moves between scalar and vector registers."
I added a pattern containing a copy_to_regclass. The copy_to_regclass is
actually not needed.
radar://13191881
llvm-svn: 175555
- TestNamespace expected to fail due to PR-15302
- TestCPPBool and TestUnsignedTypes updated to handle GCC style debug information
- TestRvalueReferences expected fail due to GCC (4.7) not outputting rvalue-reference debug information
- TestDataFormatterStdVBool expected to fail due to PR-15301
llvm-svn: 175551
autoconf and CMake flavours both updated to auto-generate files for use
in cpp11-migrate's LIT tests.
Auto-generated files are placed in the build directory under
test/cpp11-migrate/autogen. The directory structure past this point
mirrors the structure in the source directory under test/cpp11-migrate.
A lit.site.cfg is generated in test/cpp11-migrate/autogen to describe
the new test suite. When LIT runs, it runs the standard testsuite and
now also the auto-generated testsuite.
llvm-svn: 175544
/dev/stdin as an input when stdin is connected to a tty, for example.
No test, because it's difficult to write a reasonably portable test
for this. /dev/stdin isn't a character device when stdin is redirected
from a file or connected to a pipe.
llvm-svn: 175542
When creating an allocation hint for a register pair, make sure the hint
for the physical register reference is still in the allocation order.
rdar://13240556
llvm-svn: 175541
Target implementations of getRegAllocationHints() should use the
provided allocation order, and they can never return hints outside the
order. This is already documented in TargetRegisterInfo.h.
<rdar://problem/13240556>
llvm-svn: 175540
I don't want to rule out the possibility of linking to e.g. interesting
blog posts about uses of Clang, so avoid restricting the content to
"projects".
This breaks URL compatibility, but this document was committed less than
an hour ago so hopefully nobody has linked to it yet.
llvm-svn: 175535
Using a new metafunction for detecting the presence of the member
'getDecl' in a type T, added support to hasDeclaration for any such type
T. This allows hasDecl() to be replaced and enables several other
subclasses of clang::Type to use hasDeclaration.
Updated unittests and LibASTMatchersReference.html.
Reviewers: klimek
llvm-svn: 175532
A couple concrete examples are sure to be a win. If you know of any
other external projects using Clang, please let me know!
Patch by Laszlo Nagy! (with a title tweak by me)
llvm-svn: 175529
Due to the execution order of doFinalization functions, the GC information were
deleted before AsmPrinter::doFinalization was executed. Thus, the
GCMetadataPrinter::finishAssembly was never called.
The patch fixes that by moving the code of the GCInfoDeleter::doFinalization to
Printer::doFinalization.
llvm-svn: 175528
- rework the way SBDebugger.SetAsync() is used to avoid side effects (reset original value at TearDownHook)
- refactor expectedFailureClang (and add expectedFailureGcc decorator)
- mark TestChangeValueAPI.py as expectedFailureGcc due to PR-15039
llvm-svn: 175523
A vectorized sitfp on doubles will get scalarized to a sequence of an
extract_element of <2 x i32>, a bitcast to f32 and a sitofp.
Due to the the extract_element, and the bitcast we will uneccessarily generate
moves between scalar and vector registers.
The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract
the element from the vector instead.
radar://13191881
llvm-svn: 175520
This stops the Machine Verifier from complaining about uses of undefined
physical registers.
NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175518
Kernel function arguments are lowered to loads from the PARAM_I address
space. When creating these load instructions, we were initializing
their MachinePointerInfo with an Arguement object that was not attached
to any function. This was causing the MachineScheduler to crash when
it tried to access the parent of the Arguement.
This has been fixed by initializing the MachinePointerInfo with a
UndefValue instead.
NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175517
In some cases, we were losing track of live implicit registers which
was creating dead defs and causing the scheduler to produce invalid
code.
NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175516