* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes
llvm-svn: 6655
* Frame information is now stuck in MachineFunctionInfo instead of directly
in MachineFunction.
* Don't require a TM as an argument to the ctor
llvm-svn: 5172
TargetMachine.cpp, since it is entirely machine-independent.
Also, add options to disable optional back-end passes (preselection and
instr. scheduling).
llvm-svn: 3740
- Eliminate Sparc*Order classes, moving contents to Sparc*Class classes
- get register name methods now return const char * const pointers instead
of std::string's.
- Added file header comments to SparcRegClassInfo.(cpp|h)
- Moved BIG constant arrays out of SparcRegClassInfo.h, into
SparcRegInfo.cpp. This should allow a LOT of std::string constructors to
not have to be called.
llvm-svn: 3295
- Rename runOnMethod to runOnFunction
* Transform getAnalysisUsageInfo into getAnalysisUsage
- Method is now const
- It now takes one AnalysisUsage object to fill in instead of 3 vectors
to fill in
- Pass's now specify which other passes they _preserve_ not which ones
they modify (be conservative!)
- A pass can specify that it preserves all analyses (because it never
modifies the underlying program)
* s/Method/Function/g in other random places as well
llvm-svn: 2333
the bodies of the GetInstructionsFor(Prolog|Epilog) functions from
SparcInstrSelection.cpp into the class. This eliminates the need for a static
global vector of instructions and a class of errors that is really unneccesary.
llvm-svn: 2193
Misha Brukman