Commit Graph

7 Commits

Author SHA1 Message Date
Simon Pilgrim b398da1d5c [X86][SSE] shift/rotate tests - remove unnecessary mcpu arguments and regenerate/cleanup
llvm-svn: 251232
2015-10-25 12:07:45 +00:00
Simon Pilgrim 3d11c994f7 [X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions
The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes.

Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases.

Differential Revision: http://reviews.llvm.org/D8690

llvm-svn: 248878
2015-09-30 08:17:50 +00:00
Simon Pilgrim ba10f76705 [X86][SSE] Keep 32-bit target i64 vector shifts on SSE unit.
This patch improves the 32-bit target i64 constant matching to detect the shuffle vector splats that are introduced by i64 vector shift vectorization (D8416).

Differential Revision: http://reviews.llvm.org/D11327

llvm-svn: 243577
2015-07-29 21:44:27 +00:00
Simon Pilgrim 769d58f9df [X86][SSE] Added nounwind attribute to vector shift tests.
Stop i686 codegen from generating cfi directives.

llvm-svn: 242443
2015-07-16 21:14:26 +00:00
Simon Pilgrim 4582ca5ecb [X86][SSE] Added i686/SSE2 vector shift tests.
We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets.

llvm-svn: 242273
2015-07-15 08:04:07 +00:00
Simon Pilgrim d865503b59 [X86][SSE] Vector shift test cleanup. NFC.
llvm-svn: 241730
2015-07-08 21:11:17 +00:00
Simon Pilgrim a0d5c5924a [X86][SSE] Added full set of 128-bit vector shift tests.
Removed some old duplicate tests.

llvm-svn: 240465
2015-06-23 21:18:15 +00:00