6 Commits

Author	SHA1	Message	Date
Simon Pilgrim	5fa0fb23ca	[X86][SSE] Missing SSE/AVX1 memory folding integer instructions ... Added most of the missing integer vector folding patterns for SSE (to SSE42) and AVX1. The most useful of these are probably the i32/i64 extraction, i8/i16/i32/i64 insertions, zero/sign extension, unsigned saturation subtractions, i64 subtractions and the variable mask blends (pblendvb) - others include CLMUL, SSE42 string comparisons and bit tests. Differential Revision: http://reviews.llvm.org/D7094 llvm-svn: 226745	2015-01-21 23:43:30 +00:00
Benjamin Kramer	548ffa274a	SelectionDAG: Teach FoldConstantArithmetic how to deal with vectors. ... This required disabling a PowerPC optimization that did the following: input: x = BUILD_VECTOR <i32 16, i32 16, i32 16, i32 16> lowered to: tmp = BUILD_VECTOR <i32 8, i32 8, i32 8, i32 8> x = ADD tmp, tmp The add now gets folded immediately and we're back at the BUILD_VECTOR we started from. I don't see a way to fix this currently so I left it disabled for now. Fix some trivially foldable X86 tests too. llvm-svn: 174325	2013-02-04 15:19:18 +00:00
Craig Topper	a183ddb0fe	Teach DAG combine to handle vector logical operations with vectors of all 1s or all 0s. These cases can show up when vectors are split for legalizing. Fix some tests that were dependent on these cases not being combined. ... llvm-svn: 169684	2012-12-08 22:49:19 +00:00
Nadav Rotem	0a1801015c	Add test arch to make it pass on non x86 targets ... llvm-svn: 145498	2011-11-30 17:34:28 +00:00
Nadav Rotem	66427bcce9	Add a tripple to the test ... llvm-svn: 145489	2011-11-30 11:20:56 +00:00
Nadav Rotem	96923cc2bb	X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479). ... llvm-svn: 145488	2011-11-30 10:13:37 +00:00