Chris Lattner
39f65335d5
remove some dead target hooks, subsumed by isLegalAddressingMode
...
llvm-svn: 35840
2007-04-09 22:27:04 +00:00
Chris Lattner
19ccd6226c
Fix a bug in PPCTargetLowering::isLegalAddressingMode, scales other than 0/1/2
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are always unsupported.
llvm-svn: 35835
2007-04-09 22:10:05 +00:00
Jeff Cohen
4397363c16
When the number of elements is zero, don't malloc 32GB on 64-bit systems.
...
Fixes unexpected failures on FreeBSD/amd64 of:
CFrontend/2005-09-24-BitFieldCrash.c:
CFrontend/2007-02-04-EmptyStruct.c:
CFrontend/2007-03-26-ZeroWidthBitfield.c:
CodeGen/Generic/2005-10-18-ZeroSizeStackObject.ll:
llvm-svn: 35828
2007-04-09 19:26:30 +00:00
Reid Spencer
71b79e3d99
For PR1146:
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Adapt handling of parameter attributes to use the new ParamAttrsList class.
llvm-svn: 35814
2007-04-09 06:17:21 +00:00
Chris Lattner
7451e4d6a1
move a bunch of register constraints from being handled by
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getRegClassForInlineAsmConstraint to being handled by
getRegForInlineAsmConstraint. This allows us to let the llvm register allocator
allocate, which gives us better code. For example, X86/2007-01-29-InlineAsm-ir.ll
used to compile to:
_run_init_process:
subl $4, %esp
movl %ebx, (%esp)
xorl %ebx, %ebx
movl $11, %eax
movl %ebx, %ecx
movl %ebx, %edx
# InlineAsm Start
push %ebx ; movl %ebx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
Now we get:
_run_init_process:
xorl %ecx, %ecx
movl $11, %eax
movl %ecx, %edx
# InlineAsm Start
push %ebx ; movl %ecx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
llvm-svn: 35804
2007-04-09 05:49:22 +00:00
Chris Lattner
2b6b4eb471
implement support for CodeGen/X86/inline-asm-x-scalar.ll:test3 - i32/i64 values
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used with x constraints.
llvm-svn: 35803
2007-04-09 05:31:48 +00:00
Chris Lattner
590ed5e5b7
implement CodeGen/X86/inline-asm-x-scalar.ll
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llvm-svn: 35799
2007-04-09 05:11:28 +00:00
Reid Spencer
e9f516384d
Squelch a warning about mismatch between sign of constant and sign of return
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type.
llvm-svn: 35674
2007-04-04 22:07:24 +00:00
Evan Cheng
1e150dedd1
Implement inline asm modifier P.
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llvm-svn: 35640
2007-04-04 00:13:29 +00:00
Evan Cheng
bd31f41daa
Typo.
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llvm-svn: 35639
2007-04-04 00:06:07 +00:00
Bill Wendling
ac5b650a54
Adding more MMX instructions.
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llvm-svn: 35638
2007-04-03 23:48:32 +00:00
Chris Lattner
f79fb5cad0
make a new missing features section
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llvm-svn: 35637
2007-04-03 23:41:34 +00:00
Evan Cheng
3c68d4e8ba
Remove unused constant pool entries.
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llvm-svn: 35635
2007-04-03 23:39:48 +00:00
Bill Wendling
2640b4a4ab
Updated
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llvm-svn: 35634
2007-04-03 23:37:20 +00:00
Evan Cheng
39d8b4db92
Fixed a bug that causes codegen of noop like add r0, r0, #0 .
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llvm-svn: 35627
2007-04-03 21:31:21 +00:00
Nicolas Geoffray
23710a7da3
Starting implementation of the ELF32 ABI specification of varargs handling.
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LowerVASTART emits the right code if the subtarget is ELF32, the other intrinsics
(VAARG, VACOPY and VAEND) are not yet implemented.
llvm-svn: 35625
2007-04-03 13:59:52 +00:00
Nicolas Geoffray
b3e99a18ee
The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
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as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/ ).
Change all ELF tests to ELF32.
llvm-svn: 35624
2007-04-03 12:35:28 +00:00
Nicolas Geoffray
ab559f6e3c
Addition to the previous commit for getCalleeSavedRegClasses:
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"The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO."
llvm-svn: 35623
2007-04-03 10:57:49 +00:00
Nicolas Geoffray
fbfc451ba9
The ELF ABI specifies F1-F8 registers as argument registers for double, not
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F1-F10. This affects only ELF, not MachO.
llvm-svn: 35622
2007-04-03 10:27:07 +00:00
Evan Cheng
e8315fe3f5
Inverted logic.
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llvm-svn: 35619
2007-04-03 06:44:25 +00:00
Bill Wendling
652c7b2d73
Changed to new MMX_ recipes.
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llvm-svn: 35617
2007-04-03 06:18:31 +00:00
Bill Wendling
e7b2a864f2
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them.
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llvm-svn: 35616
2007-04-03 06:00:37 +00:00
Chris Lattner
f742e2fe70
Arm supports negative strides as well, add them. This lets us compile:
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CodeGen/ARM/arm-negative-stride.ll to:
LBB1_2: @bb
str r1, [r3, -r0, lsl #2 ]
add r0, r0, #1
cmp r0, r2
bne LBB1_2 @bb
llvm-svn: 35609
2007-04-03 00:13:57 +00:00
Dale Johannesen
d13786dd82
fix off by 1 error in displacement computation
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llvm-svn: 35602
2007-04-02 20:31:06 +00:00
Chris Lattner
8e168a4f36
fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales
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to be folded into non-store instructions.
llvm-svn: 35601
2007-04-02 18:51:18 +00:00
Chris Lattner
6223e83f6d
add support for the 'w' inline asm register class.
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llvm-svn: 35598
2007-04-02 17:24:08 +00:00
Chris Lattner
3e21eb7fd7
Fix a bug which caused us to never be able to use signed comparisons for
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equality comparisons of a constant. This allows us to codegen the 'sintzero'
loop in PR1288 as:
LBB1_1: ;cond_next
li r4, 0
addi r2, r2, 1
stw r4, 0(r3)
addi r3, r3, 4
cmpwi cr0, r2, -1
bne cr0, LBB1_1 ;cond_next
instead of:
LBB1_1: ;cond_next
addi r2, r2, 1
li r4, 0
xoris r5, r2, 65535
stw r4, 0(r3)
addi r3, r3, 4
cmplwi cr0, r5, 65535
bne cr0, LBB1_1 ;cond_next
This implements CodeGen/PowerPC/compare-simm.ll, and also cuts 74
instructions out of kc++.
llvm-svn: 35590
2007-04-02 05:59:42 +00:00
Lauro Ramos Venancio
6be85337b0
- Divides the comparisons in two types: comparisons that only use N and Z
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flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
llvm-svn: 35573
2007-04-02 01:30:03 +00:00
Chris Lattner
59a6fa7af6
fix breakage from last night, simplify code.
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llvm-svn: 35560
2007-04-01 20:49:36 +00:00
Evan Cheng
17d48a8bc2
Add i16 address mode.
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llvm-svn: 35551
2007-04-01 08:06:46 +00:00
Andrew Lenharth
427ec7fa51
Readme
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llvm-svn: 35533
2007-03-31 15:05:44 +00:00
Anton Korobeynikov
a8cc1ebae1
Consistency with native compilers
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llvm-svn: 35532
2007-03-31 13:11:52 +00:00
Bill Wendling
b72fcddd23
Fix comment.
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llvm-svn: 35531
2007-03-31 09:36:12 +00:00
Chris Lattner
075b4db621
add a note
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llvm-svn: 35530
2007-03-31 07:06:25 +00:00
Bill Wendling
afddb2c6f8
Match GCC's MMX calling convention.
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llvm-svn: 35523
2007-03-31 01:03:53 +00:00
Chris Lattner
1eb94d973a
implement the new addressing mode description hook.
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llvm-svn: 35521
2007-03-30 23:15:24 +00:00
Bill Wendling
2fbcbc16b4
Add MMX calling conventions.
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llvm-svn: 35489
2007-03-30 00:35:22 +00:00
Evan Cheng
045414aa8e
New entry.
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llvm-svn: 35480
2007-03-29 21:40:13 +00:00
Evan Cheng
cc44b1e743
Can't re-materialize mov r, imm in thumb since mov would clobber the condition code.
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llvm-svn: 35479
2007-03-29 21:38:31 +00:00
Jeff Cohen
68e93b7c44
MS C does have inlining after all, just uses _inline instead of inline.
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llvm-svn: 35467
2007-03-29 17:42:21 +00:00
Evan Cheng
8f592160c0
Add support for hidden visibility to darwin/arm.
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llvm-svn: 35448
2007-03-29 07:49:34 +00:00
Jeff Cohen
cc560c93eb
Fix C Backend to generate code that works with Microsoft C for the benefit of
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front ends that do not depend on the GCC runtime (someday...).
llvm-svn: 35441
2007-03-28 23:08:37 +00:00
Bill Wendling
4ad38abd40
Made this into a bug report: PR1286
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llvm-svn: 35439
2007-03-28 19:07:34 +00:00
Anton Korobeynikov
0ad22563b8
Oops :)
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llvm-svn: 35438
2007-03-28 18:38:33 +00:00
Anton Korobeynikov
7522c9d8e1
Don't allow MatchAddress recurse too much. This trims exponential
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behaviour in some cases.
llvm-svn: 35437
2007-03-28 18:36:33 +00:00
Chris Lattner
2ba38c8711
add a note
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llvm-svn: 35435
2007-03-28 18:17:19 +00:00
Chris Lattner
bcd38852f2
Compile CodeGen/X86/lea-3.ll:test2 to:
...
_test3:
leaq (,%rdi,4), %rax
orq %rdi, %rax
ret
instead of:
_test2:
movq %rdi, %rax
shlq $2, %rax
orq %rdi, %rax
ret
llvm-svn: 35434
2007-03-28 18:12:31 +00:00
Chris Lattner
a6527d6a61
Dan pointed out that this is done, remove it!
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llvm-svn: 35430
2007-03-28 17:26:52 +00:00
Scott Michel
734077b1f0
First test check-in.
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llvm-svn: 35429
2007-03-28 17:04:43 +00:00
Evan Cheng
c2cba18f2b
Remove isLegalAddressImmediate.
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llvm-svn: 35406
2007-03-28 01:53:55 +00:00