9227f39c53
ARM add more 'gas' compatibility aliases for NEON instructions.
...
llvm-svn: 146507
2011-12-13 20:08:32 +00:00
8be2f6577e
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146296
2011-12-09 23:34:09 +00:00
ea1b353e67
ARM NEON data type aliases for VBIC(register).
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llvm-svn: 146281
2011-12-09 21:46:04 +00:00
d146a02c79
ARM assembly parsing and encoding for VLD2 with writeback.
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Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
8a4009dab2
Tidy up. Better base class factoring.
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llvm-svn: 146267
2011-12-09 19:07:20 +00:00
b076e6f3d5
Tidy up. Better base class factoring.
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llvm-svn: 146266
2011-12-09 18:54:11 +00:00
db731be7b8
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
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llvm-svn: 146194
2011-12-08 22:19:04 +00:00
ba7d6ed05d
ARM VSHR implied destination operand form aliases.
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llvm-svn: 146192
2011-12-08 22:06:06 +00:00
ab9c8bb45b
ARM VSUB implied destination operand form aliases.
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llvm-svn: 146182
2011-12-08 20:56:26 +00:00
66c9ad7642
ARM VQADD implied destination operand form aliases.
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llvm-svn: 146179
2011-12-08 20:49:43 +00:00
e9ee1092e1
ARM a few more VMUL implied destination operand form aliases.
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llvm-svn: 146177
2011-12-08 20:42:35 +00:00
00326406d4
ARM NEON two-operand aliases for VSHL(immediate).
...
llvm-svn: 146125
2011-12-08 01:30:04 +00:00
f10a635eb4
ARM NEON two-operand aliases for VSHL(register).
...
llvm-svn: 146123
2011-12-08 01:12:35 +00:00
0dd1bc9c79
Fix copy/past-o.
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llvm-svn: 146120
2011-12-08 01:02:26 +00:00
31a462c02c
ARM NEON two-operand aliases for VMUL.
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llvm-svn: 146119
2011-12-08 00:59:47 +00:00
6600f520b0
ARM optional destination operand variants for VEXT instructions.
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llvm-svn: 146114
2011-12-08 00:43:47 +00:00
90d961250b
ARM two-operand aliases for VAND/VEOR/VORR instructions.
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llvm-svn: 146095
2011-12-07 23:08:12 +00:00
3744a7febb
ARM two-operand aliases for VADDW instructions.
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llvm-svn: 146093
2011-12-07 23:01:10 +00:00
552691556c
ARM two-operand aliases for VADD instructions.
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llvm-svn: 146091
2011-12-07 22:52:54 +00:00
721042fa3a
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
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llvm-svn: 146039
2011-12-07 17:51:15 +00:00
2cf294a213
ARM tidy up and remove no longer needed InstAlias definitions.
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The TokenAlias handling of data type suffices renders these unnecessary.
llvm-svn: 146010
2011-12-07 01:50:36 +00:00
d4b8249434
ARM: NEON SHLL instruction immediate operand range checking.
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llvm-svn: 146003
2011-12-07 01:07:24 +00:00
47c24c2084
ARM: Parameterize the immediate operand type for NEON VSHLL.
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No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.
llvm-svn: 145994
2011-12-07 00:02:17 +00:00
fdf9e1587a
ARM assembly parsing for the rest of the VMUL data type aliases.
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Finish up rdar://10522016.
llvm-svn: 145846
2011-12-05 20:29:59 +00:00
9e90c5cde3
Fix previous commit. Oops.
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llvm-svn: 145844
2011-12-05 20:12:26 +00:00
2b37e4fc80
Tidy up. No functional change.
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llvm-svn: 145843
2011-12-05 20:09:44 +00:00
0a978ef715
ARM assmebler parsing for two-operand VMUL instructions.
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Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.
rdar://10522016
llvm-svn: 145842
2011-12-05 19:55:46 +00:00
9dff9f4c41
ARM NEON VEXT aliases for data type suffices.
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llvm-svn: 145726
2011-12-02 23:34:39 +00:00
2635f54cb6
ARM VEXT tighten up operand classes a bit.
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llvm-svn: 145722
2011-12-02 22:57:57 +00:00
eb53822f5a
ARM VST1 single lane assembly parsing.
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llvm-svn: 145718
2011-12-02 22:34:51 +00:00
dda976b804
ARM VLD1 single lane assembly parsing.
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llvm-svn: 145712
2011-12-02 22:01:52 +00:00
e7dcbc8691
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
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Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
04945c42c6
ARM start parsing VLD1 single lane instructions.
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The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.
llvm-svn: 145655
2011-12-02 00:35:16 +00:00
a68c9a847e
ARM parsing for VLD1 all lanes, with writeback.
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llvm-svn: 145510
2011-11-30 19:35:44 +00:00
3ecf976ca9
ARM parsing for VLD1 two register all lanes, no writeback.
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llvm-svn: 145504
2011-11-30 18:21:25 +00:00
cd6f5e757c
ARM parsing aliases for VLD1 single register all lanes.
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llvm-svn: 145464
2011-11-30 01:09:44 +00:00
182b6a077e
Tidy up a bit.
...
llvm-svn: 145458
2011-11-29 23:51:09 +00:00
ae672f8118
Add comment.
...
llvm-svn: 145456
2011-11-29 23:33:40 +00:00
e1154eef0b
ARM parsing aliases for data-size suffices on VST1.
...
llvm-svn: 145454
2011-11-29 23:21:31 +00:00
5ee209ce3a
ARM assembly parsing and encoding for four-register VST1.
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llvm-svn: 145450
2011-11-29 22:58:48 +00:00
98d032fd67
ARM assembly parsing and encoding for three-register VST1.
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llvm-svn: 145442
2011-11-29 22:38:04 +00:00
003cea6011
ARM assembly parsing for data type suffices on NEON VMOV aliases.
...
llvm-svn: 144722
2011-11-15 22:54:42 +00:00
131b45e632
ARM alternate size suffices for VTRN instructions.
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rdar://10435076
llvm-svn: 144694
2011-11-15 20:49:46 +00:00
0ac9058f89
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
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llvm-svn: 144683
2011-11-15 19:55:00 +00:00
2aabaa704a
ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions.
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rdar://10435076
llvm-svn: 144650
2011-11-15 17:49:59 +00:00
7ca4b6eb5c
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
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integer variants. rdar://10437054
llvm-svn: 144608
2011-11-15 02:12:34 +00:00
29cdcda80d
ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.
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rdar://10435076
llvm-svn: 144606
2011-11-15 01:46:57 +00:00
a498af2b1d
ARM parsing datatype suffix variants for non-writeback VST1 instructions.
...
rdar://10435076
llvm-svn: 144593
2011-11-14 23:43:46 +00:00
72838a0345
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
...
rdar://10435076
llvm-svn: 144592
2011-11-14 23:32:59 +00:00
750de7a399
Add explanatory comment.
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llvm-svn: 144589
2011-11-14 23:21:09 +00:00
3d6c0e0bb2
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
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rdar://10435076
llvm-svn: 144587
2011-11-14 23:11:19 +00:00
8ca13deecf
Re-apply 144430, this time with the associated isel and disassmbler bits.
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Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
llvm-svn: 144437
2011-11-12 00:31:53 +00:00
155763b630
Oops. Missed the isel half of this. revert while I sort that out.
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llvm-svn: 144431
2011-11-11 23:51:31 +00:00
28f721a2b4
ARM assembly parsing for VST1 two-register encoding.
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llvm-svn: 144430
2011-11-11 23:45:47 +00:00
05df460269
ARM VST1 w/ writeback assembly parsing and encoding.
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llvm-svn: 143369
2011-10-31 21:50:31 +00:00
409b694c6c
Specify that the high bit of the alignment field is fixed to 0 on these instructions.
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llvm-svn: 143220
2011-10-28 20:43:24 +00:00
17ec1a19e5
ARM assembly parsing and encoding for VLD1 with writeback.
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Four entry register lists.
llvm-svn: 142882
2011-10-25 00:14:01 +00:00
30c39c8bf2
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.
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llvm-svn: 142877
2011-10-24 23:40:46 +00:00
92fd05ecdc
ARM assembly parsing and encoding for VLD1 w/ writeback.
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Three entry register list variation.
llvm-svn: 142876
2011-10-24 23:26:05 +00:00
3ea0657d54
ARM assembly parsing and encoding for VLD1 w/ writeback.
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One and two length register list variants.
llvm-svn: 142861
2011-10-24 22:16:58 +00:00
2098cb1e6f
ARM refactor am6offset usage for VLD1.
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Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
llvm-svn: 142853
2011-10-24 21:45:13 +00:00
11c0b347c6
Assembly parsing for 4-register sequential variant of VLD2.
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llvm-svn: 142704
2011-10-21 23:58:57 +00:00
118b38cbf1
Assembly parsing for 2-register sequential variant of VLD2.
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llvm-svn: 142691
2011-10-21 22:21:10 +00:00
846bcff7c7
Assembly parsing for 4-register variant of VLD1.
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llvm-svn: 142682
2011-10-21 20:35:01 +00:00
c4360fe575
Assembly parsing for 3-register variant of VLD1.
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llvm-svn: 142675
2011-10-21 20:02:19 +00:00
2f2e3c4737
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
e3013dd62d
Remove some outdated comments.
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llvm-svn: 142653
2011-10-21 16:14:12 +00:00
9036c5cf2b
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
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llvm-svn: 142583
2011-10-20 15:04:25 +00:00
8db25984a9
ARM VTBX (one register) assembly parsing and encoding.
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llvm-svn: 142581
2011-10-20 14:48:50 +00:00
ad47cfcef9
ARM VTBL (one register) assembly parsing and encoding.
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llvm-svn: 142441
2011-10-18 23:02:30 +00:00
6918617e32
Yet more ARM NEON assembly parsing for the lane index operand.
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llvm-svn: 142416
2011-10-18 20:21:17 +00:00
e9f204c197
ARM vmla/vmls assembly parsing for the lane index operand.
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llvm-svn: 142413
2011-10-18 20:14:56 +00:00
712f3670fd
ARM vmov assembly parsing for the lane index operand.
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llvm-svn: 142412
2011-10-18 20:10:47 +00:00
611450071c
ARM vmla/vmls assembly parsing for the lane index operand.
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llvm-svn: 142389
2011-10-18 18:27:07 +00:00
c8eff0327a
ARM vqdmulh assembly parsing for the lane index operand.
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llvm-svn: 142386
2011-10-18 18:12:09 +00:00
e6fbca3a61
ARM vmul assembly parsing for the lane index operand.
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llvm-svn: 142381
2011-10-18 18:01:52 +00:00
af26d7e280
ARM vqdmlal assembly parsing for the lane index operand.
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llvm-svn: 142365
2011-10-18 17:16:30 +00:00
e4454e0de2
ARM assembly parsing and encoding for VMOV.i64.
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llvm-svn: 142356
2011-10-18 16:18:11 +00:00
8211c051ca
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
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llvm-svn: 142321
2011-10-18 00:22:00 +00:00
cda32ae372
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
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llvm-svn: 142303
2011-10-17 23:09:09 +00:00
741cd73aab
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
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NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
llvm-svn: 142293
2011-10-17 22:26:03 +00:00
2ad0dee309
Tidy up organization.
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llvm-svn: 142248
2011-10-17 21:00:11 +00:00
d0637bfc68
ARM NEON assembly parsing and encoding for VDUP(scalar).
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llvm-svn: 141446
2011-10-07 23:56:00 +00:00
61f92efb5c
Remove the VMOVQQ pseudo instruction.
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llvm-svn: 138177
2011-08-20 00:52:40 +00:00
baf5538da9
Remove VMOVQQQQ pseudo instruction.
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llvm-svn: 138174
2011-08-20 00:40:14 +00:00
a6201f0a72
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
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llvm-svn: 137686
2011-08-15 23:38:54 +00:00
b9d82f411c
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
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llvm-svn: 137635
2011-08-15 18:44:44 +00:00
e0152a73c2
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
8de11bab76
Add missing register constraint for some VLD3/VLD4 pseudo instructions.
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<rdar://problem/9878189>
llvm-svn: 136962
2011-08-05 07:24:09 +00:00
454e1c7abb
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
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llvm-svn: 135290
2011-07-15 18:46:47 +00:00
9cf6f8a9b8
Remove unnecessary duplicate instruction definitions that simply overloaded the type of VEXT. This can be achieved with a Pat definition, and is much more disassembler friendly.
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llvm-svn: 135283
2011-07-15 17:48:05 +00:00
7ef7ddd2df
Clean up a few 80 column violations.
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llvm-svn: 132946
2011-06-13 22:54:22 +00:00
f0759ef271
Fix encoding for VEXTdf.
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llvm-svn: 132486
2011-06-02 21:25:24 +00:00
92ff16b7bb
Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32
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llvm-svn: 131085
2011-05-09 17:47:27 +00:00
27f3330132
Fixed encoding for VEXTqf
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llvm-svn: 129101
2011-04-07 19:56:12 +00:00
abda3caf67
Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler.
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llvm-svn: 128587
2011-03-30 23:45:29 +00:00
53dd03d537
Add a ARM-specific SD node for VBSL so that forms with a constant first operand
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can be recognized. This fixes <rdar://problem/9183078>.
llvm-svn: 128584
2011-03-30 23:01:21 +00:00
d6c5a741b5
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
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llvm-svn: 128461
2011-03-29 16:45:53 +00:00
59eea670f8
ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
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as for VDUP32d and VDUP32q, respectively.
llvm-svn: 127489
2011-03-11 20:44:08 +00:00
c77dea7f55
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
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and VDUPLN32d, respectively.
llvm-svn: 127486
2011-03-11 20:31:17 +00:00
24fe5e36ea
ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
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as for VREV64d32 and VREV64q32, respectively.
llvm-svn: 127485
2011-03-11 20:18:05 +00:00
5e57137e87
* Correct encoding for VSRI.
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* Add tests for VSRI and VSLI.
llvm-svn: 127297
2011-03-09 00:33:17 +00:00
a7f303de71
Correct the encoding for VRSRA and VSRA instructions.
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llvm-svn: 127294
2011-03-09 00:00:35 +00:00
e313f16ad9
* Fix VRSHR and VSHR to have the correct encoding for the immediate.
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* Update the NEON shift instruction test to expect what 'as' produces.
llvm-svn: 127293
2011-03-08 23:48:09 +00:00
77ad1dc56d
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
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expand the testing of the narrowing shift right instructions.
No functionality change.
llvm-svn: 127193
2011-03-07 23:38:41 +00:00
3b1459b810
Narrow right shifts need to encode their immediates differently from a normal
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shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
llvm-svn: 126723
2011-03-01 01:00:59 +00:00
e3ecd5fb9b
Add patterns to use post-increment addressing for Neon VST1-lane instructions.
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llvm-svn: 126477
2011-02-25 06:42:42 +00:00
a609b8954e
Change VLD3/4 and VST3/4 for quad registers to not update the address register.
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These operations are expanded to pairs of loads or stores, and the first one
uses the address register update to produce the address for the second one.
So far, the second load/store has also updated the address register, just
for convenience, since that output has never been used. In anticipation of
actually supporting post-increment updates for these operations, this changes
the non-updating operations to use a non-updating load/store for the second
instruction.
llvm-svn: 125013
2011-02-07 17:43:15 +00:00
42e67b5f73
Fix some NEON instruction itineraries.
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llvm-svn: 125012
2011-02-07 17:43:12 +00:00
8265d56638
Add ARM patterns to match EXTRACT_SUBVECTOR nodes.
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Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle
vectors from being translated to EXTRACT_SUBVECTOR.
Patch by Tim Northover.
The test changes are needed to keep those spill-q tests from testing aligned
spills and restores. If the only aligned stack objects are spill slots, we
no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR
was legalized by loading from the stack, which created an aligned frame index.
Now, however, there is nothing except the spill slot in the stack frame, so
I added an aligned alloca.
llvm-svn: 122995
2011-01-07 04:59:04 +00:00
eda2a9ec89
Rearrange some Neon multiclasses. No functional changes.
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llvm-svn: 122119
2010-12-18 00:42:58 +00:00
00871c71e9
Fix result type of Neon floating-point comparisons against zero.
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The result vector elements are always integers. Radar 8782191.
llvm-svn: 122112
2010-12-18 00:04:33 +00:00
fa27a8621c
Add Neon VCVT instructions for f32 <-> f16 conversions.
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Clang is now providing intrinsics for these and so we need to support them
in the backend. Radar 8068427.
llvm-svn: 121902
2010-12-15 22:14:12 +00:00
651eaa02b8
Remove the rest of the *_sfp Neon instruction patterns.
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Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now. It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior. Since that isn't obviously wrong, I've just
changed the test file. This completes the work for Radar 8711675.
llvm-svn: 121730
2010-12-13 23:02:37 +00:00
aae0862172
Simplify N2VSPat, removing some unnecessary type arguments.
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llvm-svn: 121729
2010-12-13 23:02:31 +00:00
9c00c014ab
Delete a line that I forgot to revert previously.
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llvm-svn: 121719
2010-12-13 22:05:55 +00:00
9b3546d877
Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.
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Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns. The pattern
gets pretty ugly but it seems to work well. Partial fix for Radar 8711675.
llvm-svn: 121718
2010-12-13 21:58:05 +00:00
157fec42c9
Use pseudo instructions for 2-register Neon instructions for scalar FP.
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Partial fix for Radar 8711675.
llvm-svn: 121716
2010-12-13 21:05:52 +00:00
52f522720e
Remove unused instruction class arguments.
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llvm-svn: 121715
2010-12-13 21:05:44 +00:00
9375d27460
Add float patterns for Neon vld1-lane/dup and vst1-lane operations.
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llvm-svn: 121583
2010-12-10 22:13:32 +00:00
e1d3322111
Remove unused arguments.
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llvm-svn: 121582
2010-12-10 22:13:24 +00:00
62c7b5bf76
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
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difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
llvm-svn: 120960
2010-12-05 22:04:16 +00:00
371e586544
Fix copy/pasto in vmin.f32 encoding.
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llvm-svn: 120709
2010-12-02 16:30:58 +00:00
4472801765
Use by-name rather than by-order matching for NEON operands.
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llvm-svn: 120507
2010-12-01 00:28:25 +00:00
318ce7cb3f
Fix the encoding of VLD4-dup alignment.
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The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function. Use it
for all the VLD-dup instructions for the sake of consistency.
llvm-svn: 120358
2010-11-30 00:00:42 +00:00
0b27b68164
Rename VLDnDUP instructions with double-spaced registers
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in an attempt to make things a little more consistent.
llvm-svn: 120357
2010-11-30 00:00:38 +00:00
431ac4ef50
Add support for NEON VLD3-dup instructions.
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The encoding for alignment in VLD4-dup instructions is still a work in progress.
llvm-svn: 120356
2010-11-30 00:00:35 +00:00
77ab165afe
Add support for NEON VLD3-dup instructions.
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llvm-svn: 120312
2010-11-29 19:35:29 +00:00
2d790df105
Add support for NEON VLD2-dup instructions.
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llvm-svn: 120236
2010-11-28 06:51:26 +00:00
04b2c94205
Another minor refactoring for VLD1DUP instructions.
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The op11_8 field is the same for all of them so put it in the instruction
classes instead of specifying it separately for each instruction.
llvm-svn: 120234
2010-11-28 06:51:15 +00:00
d74cf2c8f6
Refactor. Set alignment bit in VLD1-dup instruction classes.
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llvm-svn: 120197
2010-11-27 07:12:02 +00:00
c92eea0175
Add NEON VLD1-dup instructions (load 1 element to all lanes).
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llvm-svn: 120194
2010-11-27 06:35:16 +00:00
7e484e0be7
Use by-name rather than by-order operand matching for some NEON encodings.
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llvm-svn: 119923
2010-11-21 06:47:06 +00:00
b4fd2c90e9
The Vm and Vn register fields must be the same for a register-register vmov.
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llvm-svn: 119867
2010-11-19 23:12:43 +00:00
785952e5ac
Operand names
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llvm-svn: 119864
2010-11-19 22:43:08 +00:00
7d8df3185f
Clarify operand names.
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llvm-svn: 119858
2010-11-19 22:36:02 +00:00
9c335bf977
Remove trailing whitespace.
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llvm-svn: 119608
2010-11-18 01:39:50 +00:00
a74c7ccd59
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
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the operand to the pattern.
llvm-svn: 119607
2010-11-18 01:38:26 +00:00
a68e3a5397
Encode the multi-load/store instructions with their respective modes ('ia',
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'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
c7baee31ad
Add support for ARM's specialized vector-compare-against-zero instructions.
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llvm-svn: 118453
2010-11-08 23:21:22 +00:00
30c4892ea5
Add codegen and encoding support for the immediate form of vbic.
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llvm-svn: 118291
2010-11-05 19:27:46 +00:00
0747307049
Add support for code generation of the one register with immediate form of vorr.
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We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
llvm-svn: 118201
2010-11-03 22:44:51 +00:00
bb81f80af6
Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
...
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
llvm-svn: 118183
2010-11-03 18:16:27 +00:00
7d0ac84abd
Add codegen patterns for VST1-lane instructions. Radar 8599955.
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llvm-svn: 118176
2010-11-03 16:24:53 +00:00
c6af2b4066
Break ARM addrmode4 (load/store multiple base address) into its constituent
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
0ebd1fd594
Revert r118097 to fix buildbots.
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llvm-svn: 118121
2010-11-02 23:47:29 +00:00
7c30390277
Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.
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llvm-svn: 118097
2010-11-02 22:41:42 +00:00
dec87e10fd
Provide correct encodings for the remaining vst variants that we currently generate.
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llvm-svn: 118087
2010-11-02 22:18:18 +00:00
adf88d4c5f
Tentative encodings for the "single element from one lane" variant of vst1.
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llvm-svn: 118084
2010-11-02 21:54:45 +00:00
b95618cfe0
Add correct encodings for basic variants for vst3 and vst4.
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llvm-svn: 118082
2010-11-02 21:47:03 +00:00
d80b29d6f7
Add NEON VST1-lane instructions. Partial fix for Radar 8599955.
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llvm-svn: 118069
2010-11-02 21:18:25 +00:00
fa08e1e277
Add correct encodings for the basic variants for vst2.
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llvm-svn: 118068
2010-11-02 21:16:58 +00:00
87c62e54e6
Add correct encodings for the basic form of vst1.
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llvm-svn: 118067
2010-11-02 21:06:06 +00:00
9f20daf3b4
Factor out a common encoding class for loads and stores with a lane parameter.
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llvm-svn: 118055
2010-11-02 20:47:39 +00:00
a83859539f
Add correct encodings for the rest of the vld instructions that we generate.
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llvm-svn: 118053
2010-11-02 20:40:59 +00:00
526ffd57d2
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
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llvm-svn: 117997
2010-11-02 01:24:55 +00:00
b3ca2060c0
Attempt to provide correct encodings for a number of other vld1 variants, which we can't test
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since we can neither generate nor parse them at the moment.
llvm-svn: 117988
2010-11-02 00:24:52 +00:00
ad40234eff
Add correct NEON encodings for the "multiple single elements" form of vld.
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llvm-svn: 117984
2010-11-02 00:05:05 +00:00
dc44990c7d
Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.
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llvm-svn: 117964
2010-11-01 22:04:05 +00:00
2ef668840a
Add correct NEON encodings for vtbl and vtbx.
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llvm-svn: 117513
2010-10-28 00:18:46 +00:00
14be930317
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
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llvm-svn: 117512
2010-10-27 23:56:39 +00:00
fadb951e5b
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
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for specifying fractional bits for fixed point conversions.
llvm-svn: 117501
2010-10-27 22:49:00 +00:00
ed9652f959
Provide correct encodings for the get_lane and set_lane variants of vmov.
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llvm-svn: 117495
2010-10-27 21:28:09 +00:00
40d24a4abf
Provide correct NEON encodings for vdup.
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llvm-svn: 117475
2010-10-27 19:25:54 +00:00
8576a42cf3
Add correct NEON encodings for vsli and vsri.
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llvm-svn: 117459
2010-10-27 17:40:08 +00:00
d7e8135e1e
Add correct NEON encodings for vsra and vrsra.
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llvm-svn: 117458
2010-10-27 17:29:29 +00:00
825b2d1946
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
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llvm-svn: 117411
2010-10-26 22:50:46 +00:00
2888e2c7f9
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
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llvm-svn: 117402
2010-10-26 21:58:41 +00:00
e18579976f
Simplify classes for shift instructions, which are never commutable.
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llvm-svn: 117398
2010-10-26 21:13:59 +00:00
3665fee8de
Provide correct NEON encodings for vshl, register and immediate forms.
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llvm-svn: 117394
2010-10-26 20:56:57 +00:00
691ce68d3c
Add correct NEON encoding for vpadal.
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llvm-svn: 117380
2010-10-26 18:18:03 +00:00
284cb361d1
Add NEON encodings for vmov and vmvn of immediates.
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llvm-svn: 117374
2010-10-26 17:40:54 +00:00
1f6aad053d
Add correct encodings for NEON vabal.
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llvm-svn: 117315
2010-10-25 21:29:04 +00:00
b9c91679aa
Add correct NEON encodings for vaba.
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llvm-svn: 117309
2010-10-25 20:52:57 +00:00
dd001b89d7
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
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llvm-svn: 117294
2010-10-25 20:17:22 +00:00
dea09c7564
Provide correct NEON encodings for vbsl.
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llvm-svn: 117293
2010-10-25 20:13:13 +00:00
2477446ee5
Add correct instruction encodings for vbic, vorn, and vmvn.
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llvm-svn: 117282
2010-10-25 18:43:52 +00:00
feb3ee0c93
Add NEON encoding tests for vcgt and vacgt.
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llvm-svn: 117276
2010-10-25 18:03:59 +00:00
e5d0677173
Add tests for NEON encodings of vcge and vacge.
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llvm-svn: 117274
2010-10-25 17:49:32 +00:00
c178b80f65
Add a warning about our inability to test the encoding of vceq with immediate zero.
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llvm-svn: 117273
2010-10-25 17:33:02 +00:00
9d0122af7d
Add correct NEON encodings for vqdmlal.
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llvm-svn: 117134
2010-10-22 19:35:48 +00:00
3d0264667f
Provide correct encodings for NEON vmlal.
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llvm-svn: 117131
2010-10-22 19:05:25 +00:00
f48719f1b5
Provide correct NEON encodings for vmla.
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llvm-svn: 117126
2010-10-22 18:54:37 +00:00
9e44cf2bb2
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
...
half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
llvm-svn: 117056
2010-10-21 20:21:49 +00:00
6b7e401049
Add correct NEON encodings for vhadd and vrhadd.
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llvm-svn: 117047
2010-10-21 18:55:04 +00:00
9561084188
Add correct encodings for NEON vaddw.s* and vaddw.u*.
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llvm-svn: 117040
2010-10-21 18:20:25 +00:00
15c97706e8
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
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llvm-svn: 117039
2010-10-21 18:09:17 +00:00
6083502848
Implement correct encodings for NEON vadd, both integer and floating point.
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llvm-svn: 116981
2010-10-21 00:48:00 +00:00
340cd5174b
A few 80 column fixes.
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llvm-svn: 116451
2010-10-13 23:34:31 +00:00
e790afcbe1
More ARM scheduling itinerary fixes.
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llvm-svn: 116266
2010-10-11 23:41:41 +00:00
94ad008beb
Proper VST scheduling itineraries.
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llvm-svn: 116251
2010-10-11 22:03:18 +00:00
d7a404d85f
Add VLD4 scheduling itineraries.
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llvm-svn: 116143
2010-10-09 04:07:58 +00:00
a762400bed
Finish vld3 and vld4.
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llvm-svn: 116140
2010-10-09 01:45:34 +00:00
05f13e94bf
Correct some load / store instruction itinerary mistakes:
...
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
llvm-svn: 116134
2010-10-09 01:03:04 +00:00
1958cefd69
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
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llvm-svn: 115898
2010-10-07 01:50:48 +00:00
2e3e2a006b
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
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pseudo instructions.
llvm-svn: 115840
2010-10-06 21:16:16 +00:00
233b3a2f95
Add a 'pattern' arg to the ARM PseudoNeonI class.
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llvm-svn: 115831
2010-10-06 20:36:55 +00:00
fae8305e2b
Nuke the rest of the :comment references
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llvm-svn: 115373
2010-10-01 23:21:38 +00:00
1969887fc6
Fix scheduling infor for vmovn and vshrn which I broke accidentially.
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llvm-svn: 115354
2010-10-01 21:48:06 +00:00
2a5d764858
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
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llvm-svn: 115344
2010-10-01 20:50:58 +00:00
Jim Grosbach