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573 Commits

Author SHA1 Message Date
James Molloy 547d4c0662 Improve generated code for extending loads and some trunc stores on ARM. 
Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32.

llvm-svn: 150956
 2012-02-20 09:24:05 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Lang Hames 876f24f706 Third time's the charm...? 
llvm-svn: 150447
 2012-02-14 00:34:30 +00:00
Lang Hames 185455df7e Unswap swap operands, partially reducing confusion. 
llvm-svn: 150444
 2012-02-14 00:17:12 +00:00
Lang Hames aef4ca78c5 Make operands for VSWP read-modify-write. 
llvm-svn: 150433
 2012-02-13 23:37:19 +00:00
Jim Grosbach 086cbfac7d NEON VLD4(all lanes) assembly parsing and encoding. 
llvm-svn: 148884
 2012-01-25 00:01:08 +00:00
Jim Grosbach ccb6d55dae Tidy up. Rename VLD4DUP patterns for consistency. 
llvm-svn: 148883
 2012-01-24 23:47:07 +00:00
Jim Grosbach b78403ce48 NEON VLD3(all lanes) assembly parsing and encoding. 
llvm-svn: 148882
 2012-01-24 23:47:04 +00:00
Jim Grosbach 8e2722cdb0 NEON VST4(one lane) assembly parsing and encoding. 
llvm-svn: 148836
 2012-01-24 18:53:13 +00:00
Jim Grosbach 14952a0e32 NEON VLD4(one lane) assembly parsing and encoding. 
llvm-svn: 148832
 2012-01-24 18:37:25 +00:00
Jim Grosbach 3cfef8d467 NEON Two-operand assembly aliases for VSRA. 
llvm-svn: 148821
 2012-01-24 17:55:36 +00:00
Jim Grosbach 7ae12cc546 NEON Two-operand assembly aliases for VSLI. 
llvm-svn: 148819
 2012-01-24 17:49:15 +00:00
Jim Grosbach 7b6f0f67aa NEON Two-operand assembly aliases for VSRI. 
llvm-svn: 148818
 2012-01-24 17:46:58 +00:00
Jim Grosbach 681db34eae NEON add correct predicates for some asm aliases. 
llvm-svn: 148815
 2012-01-24 17:23:29 +00:00
Jim Grosbach da70eac268 NEON VST4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148764
 2012-01-24 00:58:13 +00:00
Jim Grosbach ed561fc850 NEON VLD4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148762
 2012-01-24 00:43:17 +00:00
Jim Grosbach 17bacab475 Fix typo. 
llvm-svn: 148757
 2012-01-24 00:12:39 +00:00
Jim Grosbach d3d36d9315 NEON VST3(single element from one lane) assembly parsing. 
llvm-svn: 148755
 2012-01-24 00:07:41 +00:00
Jim Grosbach 1a74724fc9 NEON VST3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148748
 2012-01-23 23:45:44 +00:00
Jim Grosbach ac2af3ffab NEON VLD3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148745
 2012-01-23 23:20:46 +00:00
Jim Grosbach a8b444b08b NEON VLD3 lane-indexed assembly parsing and encoding. 
llvm-svn: 148734
 2012-01-23 21:53:26 +00:00
Jim Grosbach d28ef9ac46 Simplify some NEON assembly pseudo definitions. 
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
 2012-01-23 19:39:08 +00:00
Anton Korobeynikov 5482b9f535 Add fused multiple+add instructions from VFPv4. 
Patch by Ana Pazos!

llvm-svn: 148658
 2012-01-22 12:07:33 +00:00
Bob Wilson 6c7aaec077 ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651> 
We have patterns for vector sext and zext operations but were missing
anyext.  Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.

llvm-svn: 148568
 2012-01-20 20:59:56 +00:00
Jim Grosbach 90f5780fc1 VST2 four-register w/ update pseudos for fixed/register update. 
rdar://10724489

llvm-svn: 148560
 2012-01-20 19:16:00 +00:00
Jim Grosbach a9d36fbca7 NEON use vmov.i32 to splat some f32 values into vectors. 
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
 2012-01-20 18:09:51 +00:00
Jim Grosbach 74ac7d50a1 ARM updating VST2 pseudo-lowering fixed vs. register update. 
rdar://10663487

llvm-svn: 147876
 2012-01-10 21:11:12 +00:00
Jim Grosbach 2b80dad572 ARM NEON mnemonic aliase for vrecpeq. 
llvm-svn: 147109
 2011-12-21 23:52:37 +00:00
Jim Grosbach 260b4b336a ARM NEON optional data type on VSWP instructions. 
llvm-svn: 147103
 2011-12-21 23:09:28 +00:00
Jim Grosbach a50e24fcb3 ARM NEON mnemonic aliases for vzipq and vswpq. 
llvm-svn: 147102
 2011-12-21 23:04:33 +00:00
Jim Grosbach c80a264386 ARM NEON assmebly parsing for VLD2 to all lanes instructions. 
llvm-svn: 147069
 2011-12-21 19:40:55 +00:00
Jim Grosbach c5af54ec89 ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
llvm-svn: 147025
 2011-12-21 00:38:54 +00:00
Jim Grosbach 2c59052984 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
llvm-svn: 146990
 2011-12-20 20:46:29 +00:00
Jim Grosbach 75e2ab5db2 ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
llvm-svn: 146983
 2011-12-20 19:21:26 +00:00
Jim Grosbach 045b6c71a6 ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates. 
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"

rdar://10603913

llvm-svn: 146925
 2011-12-19 23:51:07 +00:00
Jim Grosbach 64f4de29e0 ARM NEON two-operand aliases for VPADD. 
rdar://10602276

llvm-svn: 146895
 2011-12-19 19:51:03 +00:00
Jim Grosbach 9ae4fc035b ARM NEON implied destination aliases for VMAX/VMIN. 
llvm-svn: 146885
 2011-12-19 18:57:38 +00:00
Jim Grosbach cef98cddbe ARM NEON relax parse time diagnostics for alignment specifiers. 
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

llvm-svn: 146884
 2011-12-19 18:31:43 +00:00
Jim Grosbach a7d2421603 Tidy up. 
llvm-svn: 146882
 2011-12-19 18:11:17 +00:00
Jim Grosbach 4a29971f02 ARM NEON aliases for vmovq.f* 
llvm-svn: 146714
 2011-12-16 00:12:22 +00:00
Jim Grosbach a47294e24d ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
llvm-svn: 146699
 2011-12-15 22:56:33 +00:00
Jim Grosbach 4a5c887370 ARM NEON VTBL/VTBX assembly parsing and encoding. 
llvm-svn: 146691
 2011-12-15 22:27:11 +00:00
Jim Grosbach da51104282 ARM NEON better assembly operand range checking for lane indices of VLD/VST. 
llvm-svn: 146608
 2011-12-14 23:35:06 +00:00
Jim Grosbach a8aa30b620 ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. 
llvm-svn: 146605
 2011-12-14 23:25:46 +00:00
Jim Grosbach bb18fb4f52 ARM NEON fix alignment encoding for VST2 w/ writeback. 
Add tests for w/ writeback instruction parsing and encoding.

llvm-svn: 146594
 2011-12-14 21:49:24 +00:00
Jim Grosbach 8e987f5e25 Nuke old code. Missed in last commit. 
llvm-svn: 146590
 2011-12-14 21:41:32 +00:00
Jim Grosbach 88ac761aa4 ARM NEON refactor VST2 w/ writeback instructions. 
In addition to improving the representation, this adds support for assembly
parsing of these instructions.

llvm-svn: 146588
 2011-12-14 21:32:11 +00:00
Jim Grosbach b7ec06c5c9 ARM NEON improve factoring a bit. No functional change. 
llvm-svn: 146585
 2011-12-14 20:59:15 +00:00
Jim Grosbach 8d24618975 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

llvm-svn: 146579
 2011-12-14 19:35:22 +00:00
Jim Grosbach 4b0844e191 ARM NEON two-operand aliases for VQDMULH. 
llvm-svn: 146514
 2011-12-13 20:40:37 +00:00
Jim Grosbach 9227f39c53 ARM add more 'gas' compatibility aliases for NEON instructions. 
llvm-svn: 146507
 2011-12-13 20:08:32 +00:00
Jim Grosbach 8be2f6577e ARM add some pre-UAL VFP mnemonics for convenience when porting old code. 
llvm-svn: 146296
 2011-12-09 23:34:09 +00:00
Jim Grosbach ea1b353e67 ARM NEON data type aliases for VBIC(register). 
llvm-svn: 146281
 2011-12-09 21:46:04 +00:00
Jim Grosbach d146a02c79 ARM assembly parsing and encoding for VLD2 with writeback. 
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.

llvm-svn: 146278
 2011-12-09 21:28:25 +00:00
Jim Grosbach 8a4009dab2 Tidy up. Better base class factoring. 
llvm-svn: 146267
 2011-12-09 19:07:20 +00:00
Jim Grosbach b076e6f3d5 Tidy up. Better base class factoring. 
llvm-svn: 146266
 2011-12-09 18:54:11 +00:00
Jim Grosbach db731be7b8 ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough. 
llvm-svn: 146194
 2011-12-08 22:19:04 +00:00
Jim Grosbach ba7d6ed05d ARM VSHR implied destination operand form aliases. 
llvm-svn: 146192
 2011-12-08 22:06:06 +00:00
Jim Grosbach ab9c8bb45b ARM VSUB implied destination operand form aliases. 
llvm-svn: 146182
 2011-12-08 20:56:26 +00:00
Jim Grosbach 66c9ad7642 ARM VQADD implied destination operand form aliases. 
llvm-svn: 146179
 2011-12-08 20:49:43 +00:00
Jim Grosbach e9ee1092e1 ARM a few more VMUL implied destination operand form aliases. 
llvm-svn: 146177
 2011-12-08 20:42:35 +00:00
Jim Grosbach 00326406d4 ARM NEON two-operand aliases for VSHL(immediate). 
llvm-svn: 146125
 2011-12-08 01:30:04 +00:00
Jim Grosbach f10a635eb4 ARM NEON two-operand aliases for VSHL(register). 
llvm-svn: 146123
 2011-12-08 01:12:35 +00:00
Jim Grosbach 0dd1bc9c79 Fix copy/past-o. 
llvm-svn: 146120
 2011-12-08 01:02:26 +00:00
Jim Grosbach 31a462c02c ARM NEON two-operand aliases for VMUL. 
llvm-svn: 146119
 2011-12-08 00:59:47 +00:00
Jim Grosbach 6600f520b0 ARM optional destination operand variants for VEXT instructions. 
llvm-svn: 146114
 2011-12-08 00:43:47 +00:00
Jim Grosbach 90d961250b ARM two-operand aliases for VAND/VEOR/VORR instructions. 
llvm-svn: 146095
 2011-12-07 23:08:12 +00:00
Jim Grosbach 3744a7febb ARM two-operand aliases for VADDW instructions. 
llvm-svn: 146093
 2011-12-07 23:01:10 +00:00
Jim Grosbach 552691556c ARM two-operand aliases for VADD instructions. 
llvm-svn: 146091
 2011-12-07 22:52:54 +00:00
Jim Grosbach 721042fa3a ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
llvm-svn: 146039
 2011-12-07 17:51:15 +00:00
Jim Grosbach 2cf294a213 ARM tidy up and remove no longer needed InstAlias definitions. 
The TokenAlias handling of data type suffices renders these unnecessary.

llvm-svn: 146010
 2011-12-07 01:50:36 +00:00
Jim Grosbach d4b8249434 ARM: NEON SHLL instruction immediate operand range checking. 
llvm-svn: 146003
 2011-12-07 01:07:24 +00:00
Jim Grosbach 47c24c2084 ARM: Parameterize the immediate operand type for NEON VSHLL. 
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.

llvm-svn: 145994
 2011-12-07 00:02:17 +00:00
Jim Grosbach fdf9e1587a ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.

llvm-svn: 145846
 2011-12-05 20:29:59 +00:00
Jim Grosbach 9e90c5cde3 Fix previous commit. Oops. 
llvm-svn: 145844
 2011-12-05 20:12:26 +00:00
Jim Grosbach 2b37e4fc80 Tidy up. No functional change. 
llvm-svn: 145843
 2011-12-05 20:09:44 +00:00
Jim Grosbach 0a978ef715 ARM assmebler parsing for two-operand VMUL instructions. 
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.

rdar://10522016

llvm-svn: 145842
 2011-12-05 19:55:46 +00:00
Jim Grosbach 9dff9f4c41 ARM NEON VEXT aliases for data type suffices. 
llvm-svn: 145726
 2011-12-02 23:34:39 +00:00
Jim Grosbach 2635f54cb6 ARM VEXT tighten up operand classes a bit. 
llvm-svn: 145722
 2011-12-02 22:57:57 +00:00
Jim Grosbach eb53822f5a ARM VST1 single lane assembly parsing. 
llvm-svn: 145718
 2011-12-02 22:34:51 +00:00
Jim Grosbach dda976b804 ARM VLD1 single lane assembly parsing. 
llvm-svn: 145712
 2011-12-02 22:01:52 +00:00
Jim Grosbach e7dcbc8691 Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

llvm-svn: 145693
 2011-12-02 18:52:30 +00:00
Jim Grosbach 04945c42c6 ARM start parsing VLD1 single lane instructions. 
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.

llvm-svn: 145655
 2011-12-02 00:35:16 +00:00
Jim Grosbach a68c9a847e ARM parsing for VLD1 all lanes, with writeback. 
llvm-svn: 145510
 2011-11-30 19:35:44 +00:00
Jim Grosbach 3ecf976ca9 ARM parsing for VLD1 two register all lanes, no writeback. 
llvm-svn: 145504
 2011-11-30 18:21:25 +00:00
Jim Grosbach cd6f5e757c ARM parsing aliases for VLD1 single register all lanes. 
llvm-svn: 145464
 2011-11-30 01:09:44 +00:00
Jim Grosbach 182b6a077e Tidy up a bit. 
llvm-svn: 145458
 2011-11-29 23:51:09 +00:00
Jim Grosbach ae672f8118 Add comment. 
llvm-svn: 145456
 2011-11-29 23:33:40 +00:00
Jim Grosbach e1154eef0b ARM parsing aliases for data-size suffices on VST1. 
llvm-svn: 145454
 2011-11-29 23:21:31 +00:00
Jim Grosbach 5ee209ce3a ARM assembly parsing and encoding for four-register VST1. 
llvm-svn: 145450
 2011-11-29 22:58:48 +00:00
Jim Grosbach 98d032fd67 ARM assembly parsing and encoding for three-register VST1. 
llvm-svn: 145442
 2011-11-29 22:38:04 +00:00
Jim Grosbach 003cea6011 ARM assembly parsing for data type suffices on NEON VMOV aliases. 
llvm-svn: 144722
 2011-11-15 22:54:42 +00:00
Jim Grosbach 131b45e632 ARM alternate size suffices for VTRN instructions. 
rdar://10435076

llvm-svn: 144694
 2011-11-15 20:49:46 +00:00
Owen Anderson 0ac9058f89 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. 
llvm-svn: 144683
 2011-11-15 19:55:00 +00:00
Jim Grosbach 2aabaa704a ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions. 
rdar://10435076

llvm-svn: 144650
 2011-11-15 17:49:59 +00:00
Evan Cheng 7ca4b6eb5c Add vmov.f32 to materialize f32 immediate splats which cannot be handled by 
integer variants. rdar://10437054

llvm-svn: 144608
 2011-11-15 02:12:34 +00:00
Jim Grosbach 29cdcda80d ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions. 
rdar://10435076

llvm-svn: 144606
 2011-11-15 01:46:57 +00:00
Jim Grosbach a498af2b1d ARM parsing datatype suffix variants for non-writeback VST1 instructions. 
rdar://10435076

llvm-svn: 144593
 2011-11-14 23:43:46 +00:00
Jim Grosbach 72838a0345 ARM parsing datatype suffix variants for non-writeback VLD1 instructions. 
rdar://10435076

llvm-svn: 144592
 2011-11-14 23:32:59 +00:00
Jim Grosbach 750de7a399 Add explanatory comment. 
llvm-svn: 144589
 2011-11-14 23:21:09 +00:00
Jim Grosbach 3d6c0e0bb2 ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions. 
rdar://10435076

llvm-svn: 144587
 2011-11-14 23:11:19 +00:00
Jim Grosbach 8ca13deecf Re-apply 144430, this time with the associated isel and disassmbler bits. 
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'

llvm-svn: 144437
 2011-11-12 00:31:53 +00:00
Jim Grosbach 155763b630 Oops. Missed the isel half of this. revert while I sort that out. 
llvm-svn: 144431
 2011-11-11 23:51:31 +00:00
Jim Grosbach 28f721a2b4 ARM assembly parsing for VST1 two-register encoding. 
llvm-svn: 144430
 2011-11-11 23:45:47 +00:00
Jim Grosbach 05df460269 ARM VST1 w/ writeback assembly parsing and encoding. 
llvm-svn: 143369
 2011-10-31 21:50:31 +00:00
Owen Anderson 409b694c6c Specify that the high bit of the alignment field is fixed to 0 on these instructions. 
llvm-svn: 143220
 2011-10-28 20:43:24 +00:00
Jim Grosbach 17ec1a19e5 ARM assembly parsing and encoding for VLD1 with writeback. 
Four entry register lists.

llvm-svn: 142882
 2011-10-25 00:14:01 +00:00
Jim Grosbach 30c39c8bf2 Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction. 
llvm-svn: 142877
 2011-10-24 23:40:46 +00:00
Jim Grosbach 92fd05ecdc ARM assembly parsing and encoding for VLD1 w/ writeback. 
Three entry register list variation.

llvm-svn: 142876
 2011-10-24 23:26:05 +00:00
Jim Grosbach 3ea0657d54 ARM assembly parsing and encoding for VLD1 w/ writeback. 
One and two length register list variants.

llvm-svn: 142861
 2011-10-24 22:16:58 +00:00
Jim Grosbach 2098cb1e6f ARM refactor am6offset usage for VLD1. 
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.

llvm-svn: 142853
 2011-10-24 21:45:13 +00:00
Jim Grosbach 11c0b347c6 Assembly parsing for 4-register sequential variant of VLD2. 
llvm-svn: 142704
 2011-10-21 23:58:57 +00:00
Jim Grosbach 118b38cbf1 Assembly parsing for 2-register sequential variant of VLD2. 
llvm-svn: 142691
 2011-10-21 22:21:10 +00:00
Jim Grosbach 846bcff7c7 Assembly parsing for 4-register variant of VLD1. 
llvm-svn: 142682
 2011-10-21 20:35:01 +00:00
Jim Grosbach c4360fe575 Assembly parsing for 3-register variant of VLD1. 
llvm-svn: 142675
 2011-10-21 20:02:19 +00:00
Jim Grosbach 2f2e3c4737 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
 2011-10-21 18:54:25 +00:00
Jim Grosbach e3013dd62d Remove some outdated comments. 
llvm-svn: 142653
 2011-10-21 16:14:12 +00:00
Jim Grosbach 9036c5cf2b ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
llvm-svn: 142583
 2011-10-20 15:04:25 +00:00
Jim Grosbach 8db25984a9 ARM VTBX (one register) assembly parsing and encoding. 
llvm-svn: 142581
 2011-10-20 14:48:50 +00:00
Jim Grosbach ad47cfcef9 ARM VTBL (one register) assembly parsing and encoding. 
llvm-svn: 142441
 2011-10-18 23:02:30 +00:00
Jim Grosbach 6918617e32 Yet more ARM NEON assembly parsing for the lane index operand. 
llvm-svn: 142416
 2011-10-18 20:21:17 +00:00
Jim Grosbach e9f204c197 ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142413
 2011-10-18 20:14:56 +00:00
Jim Grosbach 712f3670fd ARM vmov assembly parsing for the lane index operand. 
llvm-svn: 142412
 2011-10-18 20:10:47 +00:00
Jim Grosbach 611450071c ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142389
 2011-10-18 18:27:07 +00:00
Jim Grosbach c8eff0327a ARM vqdmulh assembly parsing for the lane index operand. 
llvm-svn: 142386
 2011-10-18 18:12:09 +00:00
Jim Grosbach e6fbca3a61 ARM vmul assembly parsing for the lane index operand. 
llvm-svn: 142381
 2011-10-18 18:01:52 +00:00
Jim Grosbach af26d7e280 ARM vqdmlal assembly parsing for the lane index operand. 
llvm-svn: 142365
 2011-10-18 17:16:30 +00:00
Jim Grosbach e4454e0de2 ARM assembly parsing and encoding for VMOV.i64. 
llvm-svn: 142356
 2011-10-18 16:18:11 +00:00
Jim Grosbach 8211c051ca ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
llvm-svn: 142321
 2011-10-18 00:22:00 +00:00
Jim Grosbach cda32ae372 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. 
llvm-svn: 142303
 2011-10-17 23:09:09 +00:00
Jim Grosbach 741cd73aab ARM NEON "vmov.i8" immediate assembly parsing and encoding. 
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.

llvm-svn: 142293
 2011-10-17 22:26:03 +00:00
Jim Grosbach 2ad0dee309 Tidy up organization. 
llvm-svn: 142248
 2011-10-17 21:00:11 +00:00
Jim Grosbach d0637bfc68 ARM NEON assembly parsing and encoding for VDUP(scalar). 
llvm-svn: 141446
 2011-10-07 23:56:00 +00:00
Chad Rosier 61f92efb5c Remove the VMOVQQ pseudo instruction. 
llvm-svn: 138177
 2011-08-20 00:52:40 +00:00
Chad Rosier baf5538da9 Remove VMOVQQQQ pseudo instruction. 
llvm-svn: 138174
 2011-08-20 00:40:14 +00:00
Owen Anderson a6201f0a72 Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness. 
llvm-svn: 137686
 2011-08-15 23:38:54 +00:00
Owen Anderson b9d82f411c Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
llvm-svn: 137635
 2011-08-15 18:44:44 +00:00
Owen Anderson e0152a73c2 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
 2011-08-09 20:55:18 +00:00
Bob Wilson 8de11bab76 Add missing register constraint for some VLD3/VLD4 pseudo instructions. 
<rdar://problem/9878189>

llvm-svn: 136962
 2011-08-05 07:24:09 +00:00
Owen Anderson 454e1c7abb Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler. 
llvm-svn: 135290
 2011-07-15 18:46:47 +00:00
Owen Anderson 9cf6f8a9b8 Remove unnecessary duplicate instruction definitions that simply overloaded the type of VEXT. This can be achieved with a Pat definition, and is much more disassembler friendly. 
llvm-svn: 135283
 2011-07-15 17:48:05 +00:00
Jim Grosbach 7ef7ddd2df Clean up a few 80 column violations. 
llvm-svn: 132946
 2011-06-13 22:54:22 +00:00
Tanya Lattner f0759ef271 Fix encoding for VEXTdf. 
llvm-svn: 132486
 2011-06-02 21:25:24 +00:00
Mon P Wang 92ff16b7bb Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32 
llvm-svn: 131085
 2011-05-09 17:47:27 +00:00
Mon P Wang 27f3330132 Fixed encoding for VEXTqf 
llvm-svn: 129101
 2011-04-07 19:56:12 +00:00
Owen Anderson abda3caf67 Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler. 
llvm-svn: 128587
 2011-03-30 23:45:29 +00:00
Cameron Zwarich 53dd03d537 Add a ARM-specific SD node for VBSL so that forms with a constant first operand 
can be recognized. This fixes <rdar://problem/9183078>.

llvm-svn: 128584
 2011-03-30 23:01:21 +00:00
Owen Anderson d6c5a741b5 Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist. 
llvm-svn: 128461
 2011-03-29 16:45:53 +00:00
Jim Grosbach 59eea670f8 ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same 
as for VDUP32d and VDUP32q, respectively.

llvm-svn: 127489
 2011-03-11 20:44:08 +00:00
Jim Grosbach c77dea7f55 ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q 
and VDUPLN32d, respectively.

llvm-svn: 127486
 2011-03-11 20:31:17 +00:00