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10 Commits

Author SHA1 Message Date
Craig Topper 46e8970817 [RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions. 
Some microarchitectures treat rs1=x1/x5 on jalr as a hint to pop
the return-address stack. We should avoid using x5 on jalr
instructions since we aren't using x5 as an alternate link register.

Differential Revision: https://reviews.llvm.org/D105875
 2021-07-13 09:46:21 -07:00
Matt Arsenault 20c43d6bd5 OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
Matt Arsenault 06c192d454 OpaquePtr: Bulk update tests to use typed byval 
Upgrade of the IR text tests should be the only thing blocking making
typed byval mandatory. Partially done through regex and partially
manual.
 2020-11-20 14:00:46 -05:00
Andrew Wei 4ca753f4e3 [RISCV] Implement mayBeEmittedAsTailCall for tail call optimization 
Implement TargetLowering callback mayBeEmittedAsTailCall for riscv in CodeGenPrepare,
which will duplicate return instructions to enable tailcall optimization.

Differential Revision: https://reviews.llvm.org/D73699
 2020-02-18 23:56:42 +08:00
Reid Kleckner 9c2b72821b Move tail call disabling code to target independent code 
When the "disable-tail-calls" attribute was added, checks were added for
it in various backends. Now this code has proliferated, and it is
something the target is responsible for checking. Move that
responsibility back to the ISels (fast, global, and SD).

There's no major functionality change, except for targets that never
implemented this check.

This LLVM attribute was originally added in
d9699bc7bd (2015).

Reviewers: echristo, MaskRay

Differential Revision: https://reviews.llvm.org/D72118
 2020-01-03 11:27:41 -08:00
Hiroshi Yamauchi ed50e6060b [PGO][PGSO] Enable size optimizations in code gen / target passes for cold code. 
Summary: Split off of D67120.

Reviewers: davidxl

Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71288
 2019-12-13 11:01:19 -08:00
Jim Lin b77aa1d248 [RISCV] Enable tail call opt for variadic function 
Summary: Tail call opt can treat variadic function call the same as normal function call

Reviewers: mgrang, asb, lenary, lewis-revill

Reviewed By: lenary

Subscribers: luismarques, pzheng, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66278

llvm-svn: 370835
 2019-09-04 02:03:36 +00:00
Alex Bradbury 5dabe03b41 [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 
r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives.

llvm-svn: 361493
 2019-05-23 12:43:13 +00:00
Ana Pazos 2baa767455 [RISCV] Fixed test case failure due to r338047 
llvm-svn: 338341
 2018-07-31 00:36:28 +00:00
Mandeep Singh Grang ddcb95664e [RISCV] Lower the tail pseudoinstruction 
This patch lowers the tail pseudoinstruction. This has been modeled after ARM's
tail call opt.

llvm-svn: 333137
 2018-05-23 22:44:08 +00:00