maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
399,073 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

6 Commits

Author SHA1 Message Date
Jim Lin 242ddd5089 [RISCV][NFC] Add a single space after comma for VType 
In most of cases, it has a single space after comma in assembly operands.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103790
 2021-06-09 11:18:22 +08:00
Craig Topper fdf10e6197 [RISCV] Use X0 as destination of inserted vsetvli when possible. 
We aren't going to connect the result to anything so we might
as well avoid allocating a register.

Reviewed By: frasercrmck, HsiangKai

Differential Revision: https://reviews.llvm.org/D102031
 2021-05-26 13:08:51 -07:00
Jessica Clarke d63d662d3c [RISCV] Remove --riscv-no-aliases from RVV tests 
This serves no useful purpose other than to clutter things up. Diff
summary as the real diff is extremely unwieldy:

   24844 -; CHECK-NEXT:    jalr zero, 0(ra)
   24844 +; CHECK-NEXT:    ret
       8 -; CHECK-NEXT:    vl4re8.v v28, (a0)
       8 +; CHECK-NEXT:    vl4r.v v28, (a0)
      64 -; CHECK-NEXT:    vl8re8.v v24, (a0)
      64 +; CHECK-NEXT:    vl8r.v v24, (a0)
     392 -; RUN:   --riscv-no-aliases < %s | FileCheck %s
     392 +; RUN:   < %s | FileCheck %s
       1 -; RUN:   -verify-machineinstrs --riscv-no-aliases < %s \
       1 +; RUN:   -verify-machineinstrs < %s \

As discussed in D103004.
 2021-05-26 17:59:38 +01:00
Craig Topper 5a9a8c7cd4 [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 
This confirms we handle most instrutions gracefully. We do
currently fail for vslide1up and vslide1down though.
 2021-04-01 20:34:28 -07:00
Zakk Chen 9049cf77e3 [RISCV] Add constraint for RVV indexed loads. 
Add the constraint when destination EEW not equals the source EEW for
correctness.

The RVV spec has three register overlap rules and I implement the first
stricter constraint because the others are difficult to enforce.

Reviewed By: frasercrmck, craig.topper

Differential Revision: https://reviews.llvm.org/D98920
 2021-03-26 07:23:24 -07:00
ShihPo Hung 976cf53cc7 [RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0 
Add unordered indexed load: vluxei

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D95028
 2021-01-21 18:38:49 -08:00