242ddd5089
[RISCV][NFC] Add a single space after comma for VType
...
In most of cases, it has a single space after comma in assembly operands.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D103790
2021-06-09 11:18:22 +08:00
fdf10e6197
[RISCV] Use X0 as destination of inserted vsetvli when possible.
...
We aren't going to connect the result to anything so we might
as well avoid allocating a register.
Reviewed By: frasercrmck, HsiangKai
Differential Revision: https://reviews.llvm.org/D102031
2021-05-26 13:08:51 -07:00
d63d662d3c
[RISCV] Remove --riscv-no-aliases from RVV tests
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This serves no useful purpose other than to clutter things up. Diff
summary as the real diff is extremely unwieldy:
24844 -; CHECK-NEXT: jalr zero, 0(ra)
24844 +; CHECK-NEXT: ret
8 -; CHECK-NEXT: vl4re8.v v28, (a0)
8 +; CHECK-NEXT: vl4r.v v28, (a0)
64 -; CHECK-NEXT: vl8re8.v v24, (a0)
64 +; CHECK-NEXT: vl8r.v v24, (a0)
392 -; RUN: --riscv-no-aliases < %s | FileCheck %s
392 +; RUN: < %s | FileCheck %s
1 -; RUN: -verify-machineinstrs --riscv-no-aliases < %s \
1 +; RUN: -verify-machineinstrs < %s \
As discussed in D103004.
2021-05-26 17:59:38 +01:00
0187c3a45c
[RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC
2021-04-01 17:08:20 -07:00
6e360460f1
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
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The maximum LMUL is 8. We need 16 vector registers for two LMUL-8
arguments. The modification follows the proposal of psABI in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171
Differential Revision: https://reviews.llvm.org/D95134
2021-01-22 07:55:24 +08:00
9cf511aa08
[RISCV] Add intrinsics for vector AMO operations
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Add vamoswap, vamoadd, vamoxor, vamoand, vamoor,
vamomin, vamomax, vamominu, vamomaxu intrinsics.
Reviewed By: craig.topper, khchen
Differential Revision: https://reviews.llvm.org/D94589
2021-01-18 23:11:10 -08:00
Jim Lin