Commit Graph

206 Commits

Author SHA1 Message Date
Andrew Trick 310190e21f mi-sched: bypass heuristic checks when regpressure tracking is disabled.
llvm-svn: 189988
2013-09-04 21:00:02 +00:00
Andrew Trick b6e74712b6 Added -misched-regpressure option.
Register pressure tracking is half the complexity of the
scheduler. It's useful to be able to turn it off for compile time and
performance comparisons.

llvm-svn: 189987
2013-09-04 20:59:59 +00:00
Andrew Trick 2c4f8b7ee8 Fix my previous checkin to updatePressureDiffs.
There was one case that we could hit a DebugValue where I didn't think
to check. DebugValues are evil. No checkinable test case, sorry. It's
an obvious fix.

llvm-svn: 189717
2013-08-31 05:17:58 +00:00
Andrew Trick 2bc74c2887 mi-sched: update PressureDiffs on-the-fly for liveness.
This removes all expensive pressure tracking logic from the scheduling
critical path of node comparison.

llvm-svn: 189643
2013-08-30 04:36:57 +00:00
Andrew Trick b1a45b6c61 mi-sched: improve the generic register pressure comparison.
Only compare pressure within the same set. When multiple sets are
affected, we prioritize the most constrained set.

llvm-svn: 189641
2013-08-30 04:27:29 +00:00
Andrew Trick 1a8313458f mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness later.
Created SUPressureDiffs array to hold the per node PDiff computed during DAG building.

Added a getUpwardPressureDelta API that will soon replace the old
one. Compute PressureDelta here from the precomputed PressureDiffs.

Updating for liveness will come next.

llvm-svn: 189640
2013-08-30 03:49:48 +00:00
Andrew Trick ef80f50058 comment typo
llvm-svn: 189635
2013-08-30 02:02:12 +00:00
Andrew Trick 483f4199f3 Comment and revise the cyclic critical path code.
This should be much more clear now. It's still disabled pending testing.

llvm-svn: 189597
2013-08-29 18:04:49 +00:00
Andrew Trick c01b00400d Adds cyclic critical path computation and heuristics, temporarily disabled.
Estimate the cyclic critical path within a single block loop. If the
acyclic critical path is longer, then the loop will exhaust OOO
resources after some number of iterations. If lag between the acyclic
critical path and cyclic critical path is longer the the time it takes
to issue those loop iterations, then aggressively schedule for
latency.

llvm-svn: 189120
2013-08-23 17:48:43 +00:00
Andrew Trick a53e101627 mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr count.
This fixes a pathological compile time problem with very large blocks
and lots of scheduling boundaries.

llvm-svn: 189116
2013-08-23 17:48:33 +00:00
Andrew Trick 2f7667e018 Confusing comment typo.
llvm-svn: 187895
2013-08-07 17:20:32 +00:00
Andrew Trick 9c17eab761 MI Sched: Track live-thru registers.
When registers must be live throughout the scheduling region, increase
the limit for the register class. Once we exceed the original limit,
they will be spilled, and there's no point further reducing pressure.

This isn't a perfect heuristics but avoids a situation where the
scheduler could become trapped by trying to achieve the impossible.

llvm-svn: 187436
2013-07-30 19:59:12 +00:00
Andrew Trick d9761776bc MI Sched fix: assert "Disconnected LRG within the scheduling region."
llvm-svn: 187435
2013-07-30 19:59:08 +00:00
Andrew Trick 401b6959ae MI Sched: Register pressure heuristics.
Consider which set is being increased or decreased before comparing.

llvm-svn: 187110
2013-07-25 07:26:35 +00:00
Andrew Trick 9706496b0d Dump LIS before regalloc. MI sched changes them.
llvm-svn: 187107
2013-07-25 07:26:26 +00:00
Alexey Samsonov 64c391dbe4 Fix uninitialized memory read found by MemorySanitizer: always set output parameter of ConvergingScheduler::SchedBoundary::getOtherResourceCount
llvm-svn: 186658
2013-07-19 08:55:18 +00:00
Andrew Trick b13ef17a14 MI Sched: Update the way resources are tracked so the current heuristics make more sense.
llvm-svn: 186632
2013-07-19 00:20:07 +00:00
Andrew Trick b55db58edf MI-Sched: cleanup DEBUG output.
llvm-svn: 184565
2013-06-21 18:33:01 +00:00
Andrew Trick 736dd9a255 MI-Sched: Adjust regpressure limits for reserved regs.
llvm-svn: 184564
2013-06-21 18:32:58 +00:00
Andrew Trick 71f08a3e74 Give RegMax higher priority.
llvm-svn: 184133
2013-06-17 21:45:13 +00:00
Andrew Trick 3c3a40e4c6 Remove compareRPDelta.
A complex, expensive heuristic with little value in the current design.

llvm-svn: 184132
2013-06-17 21:45:11 +00:00
Andrew Trick 7e63046ce9 MI-Sched: Remove another heuristic that is sensitive to queue order.
llvm-svn: 184130
2013-06-17 21:45:07 +00:00
Andrew Trick d40d0f2c1b MI-Sched: Track multiple candidates with the same priority level.
This eliminates the MultiPressure scheduling "reason". It was
sensitive to queue order. We don't like being sensitive to queue
order.

llvm-svn: 184129
2013-06-17 21:45:05 +00:00
Andrew Trick 8e8415f5ab Missing NDEBUGs.
llvm-svn: 184039
2013-06-15 05:46:47 +00:00
Andrew Trick f78e7fa140 MI-Sched: heuristics using the new latency and machine model.
llvm-svn: 184038
2013-06-15 05:39:19 +00:00
Andrew Trick de2109eb4c Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

llvm-svn: 184032
2013-06-15 04:49:57 +00:00
Andrew Trick e2ff575bb8 MI-Sched: Rename IssueCount to CurrMOps.
"Counts" refer to scaled resource counts within a region. CurrMOps is
simply the number of micro-ops to be issue in the current cycle.

llvm-svn: 184031
2013-06-15 04:49:49 +00:00
Andrew Trick 0cd8afc547 MI-Sched: Remove the temporary EnableCopyConstrain flag.
llvm-svn: 184030
2013-06-15 04:49:46 +00:00
Andrew Trick f5b8ef2690 MI-Sched: added tracking of dependent latency for better heuristics.
Heuristics compare the critical path in the scheduled code, called
ExpectedLatency, with the latency of instructions remaining to be
scheduled. There are two ways to look at remaining latency:

(1) Dependent latency includes the latency between unscheduled and
scheduled instructions.

(2) Independent latency is simply the height (bottom-up) or depth
(top-down) of instructions currently in the ready Q.

llvm-svn: 184029
2013-06-15 04:49:44 +00:00
Andrew Trick 5580e5ca80 MI-Sched: DEBUG: print critical resource.
llvm-svn: 184028
2013-06-15 04:49:42 +00:00
Jakub Staszak 80df8b837f Move #include from .h to .cpp file.
llvm-svn: 183960
2013-06-14 00:00:13 +00:00
Andrew Trick dd77014acc MI Sched: revert a minor heuristic that snuck in with -misched-vcopy.
I'll fix the heuristic in a general way in a follow-up commit.

llvm-svn: 180815
2013-04-30 22:10:59 +00:00
Andrew Trick 2e87517144 Fix for r180193 - MI Sched: eliminate local vreg.
Fixes PR15838. Need to check for blocks with nothing but dbg.value.

I'm not sure how to force this situation with a unit test. I tried to
reduce the test case in PR15838 (1k lines of metadata) but gave up.

llvm-svn: 180227
2013-04-24 23:19:56 +00:00
Andrew Trick 85a1d4cbc0 MI Sched: eliminate local vreg copies.
For now, we just reschedule instructions that use the copied vregs and
let regalloc elliminate it. I would really like to eliminate the
copies on-the-fly during scheduling, but we need a complete
implementation of repairIntervalsInRange() first.

The general strategy is for the register coalescer to eliminate as
many global copies as possible and shrink live ranges to be
extended-basic-block local. The coalescer should not have to worry
about resolving local copies (e.g. it shouldn't attemp to reorder
instructions). The scheduler is a much better place to deal with local
interference. The coalescer side of this equation needs work.

llvm-svn: 180193
2013-04-24 15:54:43 +00:00
Andrew Trick 7c791a3dc4 MI Sched: regpressure tracing.
llvm-svn: 180191
2013-04-24 15:54:36 +00:00
Andrew Trick 1f0bb69b6c MI-Sched: DEBUG formatting.
llvm-svn: 179452
2013-04-13 06:07:49 +00:00
Andrew Trick e833e1cd6e MI-Sched: schedule physreg copies.
The register allocator expects minimal physreg live ranges. Schedule
physreg copies accordingly. This is slightly tricky when they occur in
the middle of the scheduling region. For now, this is handled by
rescheduling the copy when its associated instruction is
scheduled. Eventually we may instead bundle them, but only if we can
preserve the bundles as parallel copies during regalloc.

llvm-svn: 179449
2013-04-13 06:07:40 +00:00
Andrew Trick 80e66ce0b4 RegisterPressure heuristics currently require signed comparisons.
llvm-svn: 178823
2013-04-05 00:31:34 +00:00
Andrew Trick 96ce3848d6 Disable DFSResult for ConvergingScheduler.
For now, just save the compile time since the ConvergingScheduler
heuristics don't use this analysis. We'll probably enable it later
after compile-time investigation.

llvm-svn: 178822
2013-04-05 00:31:31 +00:00
Andrew Trick 419d491747 MachineScheduler: format DEBUG output.
I'm getting more serious about tuning and enabling on x86/ARM. Start
by making the trace readable.

llvm-svn: 178821
2013-04-05 00:31:29 +00:00
Matt Arsenault 4ab769f4b3 Fix missing std::. Not sure how this compiles for anyone else.
llvm-svn: 177620
2013-03-21 00:57:21 +00:00
Jakub Staszak df17ddd56b Cleanup #includes.
llvm-svn: 176787
2013-03-10 13:11:23 +00:00
Andrew Trick 48f2a72435 Add -verify-misched option.
This verifies live intervals both before and after scheduling. It's
useful for anyone hacking on live interval update.

Note that we don't yet pass verification all the time. We don't yet
handle updating nonallocatable live intervals perfectly.

llvm-svn: 176685
2013-03-08 05:40:34 +00:00
Jakub Staszak 87609f5a29 Use const reference instead of vector object when passing an argument to
updateScheduledPressure method.

llvm-svn: 175362
2013-02-16 15:47:26 +00:00
Andrew Trick 553e0fe365 MIsched: HazardRecognizers are created for each DAG. Free them.
llvm-svn: 175067
2013-02-13 19:22:27 +00:00
Andrew Trick 399c9bfcc0 MIsched: cleanup code. Use isBoundaryNode().
llvm-svn: 173775
2013-01-29 06:26:35 +00:00
Jakub Staszak c641adae19 Use const reference instead of vector copying.
llvm-svn: 173497
2013-01-25 21:44:27 +00:00
Andrew Trick 54b2ce3812 MIsched: Print block name. No functionality.
llvm-svn: 173433
2013-01-25 07:45:31 +00:00
Andrew Trick ea9fd951a0 MachineScheduler support for viewGraph.
llvm-svn: 173432
2013-01-25 07:45:29 +00:00
Andrew Trick e2c3f5c982 MIsched: Improve the interface to SchedDFS analysis (subtrees).
Allow the strategy to select SchedDFS. Allow the results of SchedDFS
to affect initialization of the scheduler state.

llvm-svn: 173425
2013-01-25 06:33:57 +00:00
Andrew Trick 44f750a3e5 MISched: Add SchedDFSResult to ScheduleDAGMI to formalize the
interface and allow other strategies to select it.

llvm-svn: 173413
2013-01-25 04:01:04 +00:00
Andrew Trick 92da42406e MachineScheduler: enable biasCriticalPath for all DAGs.
llvm-svn: 173318
2013-01-24 02:09:57 +00:00
Andrew Trick 5907292dfd Follow-up typo correction from building the wrong branch.
llvm-svn: 172224
2013-01-11 17:51:16 +00:00
Andrew Trick ae182ce4fc Fix typo from r170452. Affects -enable-misched heuristics.
llvm-svn: 172223
2013-01-11 17:46:50 +00:00
Andrew Trick 9f0b95f260 MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.

I converted some in-order scheduling tests to A2. Hal is working on
more test cases.

llvm-svn: 171946
2013-01-09 03:36:49 +00:00
Andrew Trick ef23569858 MISched: Cleanup, redundant statement.
llvm-svn: 170453
2012-12-18 20:52:58 +00:00
Andrew Trick d6d5ad3d7b MISched: Heuristics, compare latency more precisely. It matters more for some targets.
llvm-svn: 170452
2012-12-18 20:52:56 +00:00
Andrew Trick 44f54d97a4 MISched: Remove SchedRemainder::IsResourceLimited. I don't know how to compute it.
llvm-svn: 170451
2012-12-18 20:52:54 +00:00
Andrew Trick 493b867b5d MISched: cleanup, use the proper iterator type.
llvm-svn: 170450
2012-12-18 20:52:52 +00:00
Andrew Trick ffb6168e85 MISched: minor improvement, initialize remaining resources before the first scheduling decision.
llvm-svn: 170449
2012-12-18 20:52:49 +00:00
Chandler Carruth ed0881b2a6 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Andrew Trick b767d1eba8 misched: Fix RegisterPressureTracker handling of DebugVals.
Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker").
rdar://12790302.

llvm-svn: 169072
2012-12-01 01:22:49 +00:00
Andrew Trick e7ea8aa48a misched: fix RegionBegin when DebugValues get shuffled to the top.
assert (RemainingInstrs == 0 && "Instruction count mismatch!")

rdar://12776937.

llvm-svn: 169069
2012-12-01 01:22:38 +00:00
Benjamin Kramer aa598b3be6 misched: Recompute priority queue when DFSResults are updated.
This was found by MSVC10's STL debug mode on a test from the test suite. Sadly
std::is_heap isn't standard so there is no way to assert this without writing
our own heap verify, which looks like overkill to me.

llvm-svn: 168885
2012-11-29 14:36:26 +00:00
Andrew Trick 48d392e81e misched: Analysis that partitions the DAG into subtrees.
This is a simple, cheap infrastructure for analyzing the shape of a
DAG. It recognizes uniform DAGs that take the shape of bottom-up
subtrees, such as the included matrix multiplication example. This is
useful for heuristics that balance register pressure with ILP. Two
canonical expressions of the heuristic are implemented in scheduling
modes: -misched-ilpmin and -misched-ilpmax.

llvm-svn: 168773
2012-11-28 05:13:28 +00:00
Andrew Trick cd1c2f9fb1 misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.
llvm-svn: 168772
2012-11-28 05:13:24 +00:00
Andrew Trick cf7e6971e8 misched: Debug output fix. Use an always valid iterator.
llvm-svn: 168767
2012-11-28 03:42:47 +00:00
Andrew Trick 108c88c5b7 misched: Allow subtargets to enable misched and dependent options.
This allows me to begin enabling (or backing out) misched by default
for one subtarget at a time. To run misched we typically want to:
- Disable SelectionDAG scheduling (use the source order scheduler)
- Enable more aggressive coalescing (until we decide to always run the coalescer this way)
- Enable MachineScheduler pass itself.

Disabling PostRA sched may follow for some subtargets.

llvm-svn: 167826
2012-11-13 08:47:29 +00:00
Andrew Trick ec369d5316 misched: rename interfaceto avoid gcc warnings
llvm-svn: 167753
2012-11-12 21:28:10 +00:00
Andrew Trick 263280248a misched: Target-independent support for MacroFusion.
Uses the infrastructure from r167742 to support clustering instructure
that the target processor can "fuse". e.g. cmp+jmp.

Next step: target hook implementations with test cases, and enable.

llvm-svn: 167744
2012-11-12 19:52:20 +00:00
Andrew Trick a7714a0ff9 misched: Target-independent support for load/store clustering.
This infrastructure is generally useful for any target that wants to
strongly prefer two instructions to be adjacent after scheduling.

A following checkin will add target-specific hooks with unit
tests. Then this feature will be enabled by default with misched.

llvm-svn: 167742
2012-11-12 19:40:10 +00:00
Andrew Trick f1ff84c64e misched: Infrastructure for weak DAG edges.
This adds support for weak DAG edges to the general scheduling
infrastructure in preparation for MachineScheduler support for
heuristics based on weak edges.

llvm-svn: 167738
2012-11-12 19:28:57 +00:00
Benjamin Kramer c280f41864 Silence GCC warning about falling off the end of a non-void function.
llvm-svn: 167618
2012-11-09 15:45:22 +00:00
Andrew Trick 3ca33acb95 misched: Heuristics based on the machine model.
misched is disabled by default. With -enable-misched, these heuristics
balance the schedule to simultaneously avoid saturating processor
resources, expose ILP, and minimize register pressure. I've been
analyzing the performance of these heuristics on everything in the
llvm test suite in addition to a few other benchmarks. I would like
each heuristic check to be verified by a unit test, but I'm still
trying to figure out the best way to do that. The heuristics are still
in considerable flux, but as they are refined we should be rigorous
about unit testing the improvements.

llvm-svn: 167527
2012-11-07 07:05:09 +00:00
Andrew Trick 4d1fa712ac misched: Rename RemainingCount to avoid confusion with remaining resources.
llvm-svn: 167443
2012-11-06 07:10:34 +00:00
Andrew Trick d9d4be0d57 misched: Added handleMove support for updating all kill flags, not just for allocatable regs.
This is a medium term workaround until we have a more robust solution
in the form of a register liveness utility for postRA passes.

llvm-svn: 166001
2012-10-16 00:22:51 +00:00
Andrew Trick 90f711da9a misched: ILP scheduler for experimental heuristics.
llvm-svn: 165950
2012-10-15 18:02:27 +00:00
Andrew Trick dd79f0fcea misched: Use the TargetSchedModel interface wherever possible.
Allows the new machine model to be used for NumMicroOps and OutputLatency.

Allows the HazardRecognizer to be disabled along with itineraries.

llvm-svn: 165603
2012-10-10 05:43:09 +00:00
Andrew Trick 984d98bf6a misched: avoid scheduling an instruction twice.
llvm-svn: 165416
2012-10-08 18:53:53 +00:00
Andrew Trick a2733e9549 misched: add a hook for custom DAG postprocessing.
llvm-svn: 163915
2012-09-14 17:22:42 +00:00
Manman Ren 19f49ac624 Release build: guard dump functions with
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)"

No functional change. Update r163339.

llvm-svn: 163653
2012-09-11 22:23:19 +00:00
Andrew Trick 7a8e10042f Reorganize MachineScheduler interfaces and publish them in the header.
The Hexagon target decided to use a lot of functionality from the
target-independent scheduler. That's fine, and other targets should be
able to do the same. This reorg and API update makes that easy.

For the record, ScheduleDAGMI was not meant to be subclassed. Instead,
new scheduling algorithms should be able to implement
MachineSchedStrategy and be done. But if need be, it's nice to be
able to extend ScheduleDAGMI, so I also made that easier. The target
scheduler is somewhat more apt to break that way though.

llvm-svn: 163580
2012-09-11 00:39:15 +00:00
Manman Ren 742534c4dc Release build: guard dump functions with "ifndef NDEBUG"
No functional change.

llvm-svn: 163339
2012-09-06 19:06:06 +00:00
Andrew Trick ae53561b0c Simplify the computeOperandLatency API.
The logic for recomputing latency based on a ScheduleDAG edge was
shady. This bypasses the problem by requiring the client to provide
operand indices. This ensures consistent use of the machine model's
API.

llvm-svn: 162420
2012-08-23 00:39:43 +00:00
Craig Topper a538d831e6 Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
llvm-svn: 162347
2012-08-22 06:07:19 +00:00
Sylvestre Ledru 35521e2310 Fix a typo (the the => the)
llvm-svn: 160621
2012-07-23 08:51:15 +00:00
Andrew Trick 87255e340e I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

llvm-svn: 159891
2012-07-07 04:00:00 +00:00
Andrew Trick 2f26b34806 misched: allow NULL InstrItineraries.
llvm-svn: 159599
2012-07-02 21:55:12 +00:00
Andrew Trick 8c9e6728b3 misched: avoid scheduling instructions that can't be dispatched.
llvm-svn: 159408
2012-06-29 03:23:24 +00:00
Andrew Trick ce27bb999d misched: count micro-ops toward the issue limit.
llvm-svn: 159407
2012-06-29 03:23:22 +00:00
Benjamin Kramer b9f84bb0ce Guard private fields that are unused in Release builds with #ifndef NDEBUG.
llvm-svn: 158608
2012-06-16 21:48:13 +00:00
Andrew Trick 05ff4667eb Move RegisterClassInfo.h.
Allow targets to access this API. It's required for RegisterPressure.

llvm-svn: 158102
2012-06-06 20:29:31 +00:00
Andrew Trick 88517f608c Move RegisterPressure.h.
Make it a general utility for use by Targets.

llvm-svn: 158097
2012-06-06 19:47:35 +00:00
Andrew Trick 4544606c71 misched: API for minimum vs. expected latency.
Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.

llvm-svn: 158021
2012-06-05 21:11:27 +00:00
Andrew Trick d36adece50 misched: comments from code review.
llvm-svn: 157975
2012-06-05 03:44:26 +00:00
Andrew Trick 4e7f6a7702 misched: trace formatting
llvm-svn: 157455
2012-05-25 02:02:39 +00:00
Kaelyn Uhrain 85d8f0cba8 Silence unused variable warnings from when assertions are disabled.
llvm-svn: 157438
2012-05-24 23:37:49 +00:00
Andrew Trick a306a8a844 misched: Use the same scheduling heuristics with -misched-topdown/bottomup.
(except the part about choosing direction)

llvm-svn: 157437
2012-05-24 23:11:17 +00:00
Andrew Trick 79d3eecbb4 misched: Trace regpressure.
llvm-svn: 157429
2012-05-24 22:11:14 +00:00
Andrew Trick a8ad5f7c7b misched: Give each ReadyQ a unique ID
llvm-svn: 157428
2012-05-24 22:11:12 +00:00