Commit Graph

11 Commits

Author SHA1 Message Date
Duraid Madina 2f2312575b * add the shladd instruction
* fold left shifts of 1, 2, 3 or 4 bits into adds

  This doesn't save much now, but should get a serious workout once
  multiplies by constants get converted to shift/add/sub sequences.
  Hold on! :)

llvm-svn: 21282
2005-04-13 06:12:04 +00:00
Chris Lattner 6b91767b77 Make sure to realize that calls use their argument regs
llvm-svn: 21248
2005-04-12 15:12:19 +00:00
Duraid Madina fb43ef78c5 assorted fixes:
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
  * fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
  * fix nasty thinko - didn't use two-address form of conditional add
    for extending bools to integers, so occasionally there would be
    garbage in the result. it's amazing how often zeros are just
    sitting around in registers ;) - this should fix a bunch of tests.

llvm-svn: 21221
2005-04-11 05:55:56 +00:00
Duraid Madina 41ff502549 fix bogus division-by-power-of-2 (was wrong for negative input, adds extr insn)
fix hack in division (clean up frcpa instruction)

llvm-svn: 21153
2005-04-08 10:01:48 +00:00
Duraid Madina b484f7c55e add immediate forms of add, sub, shift
llvm-svn: 21129
2005-04-07 12:32:24 +00:00
Duraid Madina 03c530786c add fms instruction
llvm-svn: 21112
2005-04-06 09:54:09 +00:00
Duraid Madina dbc810022b add implicit use op
llvm-svn: 21074
2005-04-04 04:50:57 +00:00
Duraid Madina 0ccac38ed3 add fnegabs op
llvm-svn: 21022
2005-04-02 10:06:27 +00:00
Duraid Madina 0720dc14ed add support FNEG and FABS
llvm-svn: 21012
2005-04-02 05:18:38 +00:00
Duraid Madina 73c2777a0e add what we need to fudge a 'floating point conditional move', this is
used to get FP div-by-zero working properly (shunt the right answer
depending on how frcpa sets its predicate output)

llvm-svn: 20954
2005-03-31 07:32:32 +00:00
Duraid Madina 91ed0a11cf and so it begins...
PHASE 1: write instruction selector
PHASE 2: ???
PHASE 3: profit!

llvm-svn: 20652
2005-03-17 18:17:03 +00:00