Commit Graph

18208 Commits

Author SHA1 Message Date
Duraid Madina dfbbcc098b oops, this stopped us turning movl r4=0xFFFFFFFF;; and rX, r4 into zxt4
llvm-svn: 21299
2005-04-14 10:06:35 +00:00
Nate Begeman 53d3eccbe2 Implement multi-way branches through logical ops on condition registers.
This can generate considerably shorter code, reducing the size of crafty
by almost 1%.  Also fix the printing of mcrf.  The code is currently
disabled until it gets a bit more testing, but should work as-is.

llvm-svn: 21298
2005-04-14 09:45:08 +00:00
Nate Begeman 80c095f422 Add a couple missing transforms in getSetCC that were triggering assertions
in the PPC Pattern ISel

llvm-svn: 21297
2005-04-14 08:56:52 +00:00
Duraid Madina f6b666fb06 we have zextloads, not sextloads!
llvm-svn: 21296
2005-04-14 08:37:32 +00:00
Nate Begeman 65a82c562e Add the necessary support to codegen condition register logical ops with
register allocated condition registers.  Make sure that the printed
  output is gas compatible.

llvm-svn: 21295
2005-04-14 03:20:38 +00:00
Nate Begeman be21011911 Start allocating condition registers. Almost all explicit uses of CR0 are
now gone.  Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.

llvm-svn: 21294
2005-04-13 23:15:44 +00:00
Nate Begeman dd1bb81d04 Implement the fold shift X, zext(Y) -> shift X, Y at the target level,
where it is safe to do so.

llvm-svn: 21293
2005-04-13 22:14:14 +00:00
Nate Begeman 04ae873648 Add CodeGen tests for the recent SelectionDAG transforms
llvm-svn: 21292
2005-04-13 21:45:13 +00:00
Nate Begeman 4ddd81657b Disbale the broken fold of shift + sz[ext] for now
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
  always produces zero or one.

llvm-svn: 21291
2005-04-13 21:23:31 +00:00
Chris Lattner 56d177a344 fix an infinite loop
llvm-svn: 21289
2005-04-13 20:06:29 +00:00
Chris Lattner e3d17d8225 fix some serious miscompiles on ia64, alpha, and ppc
llvm-svn: 21288
2005-04-13 19:53:40 +00:00
Chris Lattner 8c3d409dc7 avoid work when possible, perhaps fix the problem nate and andrew are seeing
with != 0 comparisons vanishing.

llvm-svn: 21287
2005-04-13 19:41:05 +00:00
Andrew Lenharth 93341a0f82 WOW, function calls still seem to work after this.
llvm-svn: 21286
2005-04-13 17:17:28 +00:00
Andrew Lenharth c3621316ee prepare for func call optimization
llvm-svn: 21285
2005-04-13 16:19:50 +00:00
Andrew Lenharth c2ff402c84 regression case for faster call sequence
llvm-svn: 21284
2005-04-13 16:16:01 +00:00
Andrew Lenharth 714dd6a0ec check that casts still use zap
llvm-svn: 21283
2005-04-13 13:00:16 +00:00
Duraid Madina 2f2312575b * add the shladd instruction
* fold left shifts of 1, 2, 3 or 4 bits into adds

  This doesn't save much now, but should get a serious workout once
  multiplies by constants get converted to shift/add/sub sequences.
  Hold on! :)

llvm-svn: 21282
2005-04-13 06:12:04 +00:00
Andrew Lenharth c7287c8eda add matches for SxADDL and company, as well as simplify the SxADDQ code
llvm-svn: 21281
2005-04-13 05:19:55 +00:00
Chris Lattner e69ad5fd12 Implement expansion of unsigned i64 -> FP.
Note that this probably only works for little endian targets, but is enough
to get siod working :)

llvm-svn: 21280
2005-04-13 05:09:42 +00:00
Duraid Madina e7ef27bcfe * if ANDing with a constant of the form:
0x00000..00FFF..FF
      ^      ^
      ^      ^
    any number of
    0's followed by
    some number of
    1's

    then we use dep.z to just paste zeros over the input. For the special
    cases where this is zxt1/zxt2/zxt4, we use those instructions instead,
    because we're all about readability!!!
    that's what it's about!! readability!

  *twitch* ;D

llvm-svn: 21279
2005-04-13 04:50:54 +00:00
Andrew Lenharth 5cee4ef049 added s4addl matching test
llvm-svn: 21277
2005-04-13 04:41:06 +00:00
Andrew Lenharth 8eb82fb524 added all flavors of zap for anding
llvm-svn: 21276
2005-04-13 03:47:03 +00:00
Chris Lattner 0efd77eda7 Make expansion of uint->fp cast assert out instead of infinitely recurse.
llvm-svn: 21275
2005-04-13 03:42:14 +00:00
Chris Lattner 60c23bd169 Fix some mysteriously missing {}'s which cause the miscompilation of
Olden/mst, Ptrdist/bc, Obsequi, etc.

llvm-svn: 21274
2005-04-13 03:29:53 +00:00
Chris Lattner b1f25ac188 add back the optimization that Nate added for shl X, (zext_inreg y)
llvm-svn: 21273
2005-04-13 02:58:13 +00:00
Chris Lattner 39844ac337 Oops, remove these too.
llvm-svn: 21272
2005-04-13 02:47:57 +00:00
Chris Lattner e0efd1fa72 remove one more occurance of this that snuck in
llvm-svn: 21271
2005-04-13 02:46:17 +00:00
Chris Lattner 857624f47a Remove support for ZERO_EXTEND_INREG. This pessimizes code, genering stuff
like this:

        ldah $1,1($31)
        lda $1,-1($1)
        and $0,$1,$24

instead of this:

        zap $0,252,$24

To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.

llvm-svn: 21270
2005-04-13 02:43:40 +00:00
Chris Lattner 7f4c4179a6 Remove special handling of ZERO_EXTEND_INREG. This pessimizes code, causing
things like this:

       mov r9 = 65535;;
       and r8 = r8, r9;;

To be emitted instead of:

        zxt2 r8 = r8;;

To get this back, the selector for ISD::AND should recognize this case.

llvm-svn: 21269
2005-04-13 02:41:52 +00:00
Chris Lattner 83075510ee Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.

llvm-svn: 21268
2005-04-13 02:40:26 +00:00
Chris Lattner 248fe6bda2 Z_E_I is gone
llvm-svn: 21267
2005-04-13 02:39:05 +00:00
Chris Lattner 0e852afb4c Instead of making ZERO_EXTEND_INREG nodes, use the helper method in
SelectionDAG to do the job with AND.  Don't legalize Z_E_I anymore as
it is gone

llvm-svn: 21266
2005-04-13 02:38:47 +00:00
Chris Lattner 2b4e3fca38 Remove all foldings of ZERO_EXTEND_INREG, moving them to work for AND nodes
instead.  OVerall, this increases the amount of folding we can do.

llvm-svn: 21265
2005-04-13 02:38:18 +00:00
Chris Lattner 50b63f7015 Add a new helper method which returns the and that is equivalent to what
ZERO_EXTEND_INREG was.

llvm-svn: 21264
2005-04-13 02:37:19 +00:00
Chris Lattner 71886d95d5 Remove the ZERO_EXTEND_INREG node which is redundant with AND
llvm-svn: 21263
2005-04-13 02:36:41 +00:00
Nate Begeman ca916ba4a0 Fold shift x, [sz]ext(y) -> shift x, y
llvm-svn: 21262
2005-04-12 23:32:28 +00:00
Nate Begeman af1c0f7a00 Fold shift by size larger than type size to undef
Make llvm undef values generate ISD::UNDEF nodes

llvm-svn: 21261
2005-04-12 23:12:17 +00:00
Nate Begeman 818eb6ddd2 Implement setcc op, -1 sequences
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm

llvm-svn: 21260
2005-04-12 21:22:28 +00:00
Chris Lattner 0b73a6d8bc promote extload i1 -> extload i8
llvm-svn: 21258
2005-04-12 20:30:10 +00:00
Chris Lattner 9daef352e9 add an argument to allow avoiding deleting phi nodes.
llvm-svn: 21255
2005-04-12 18:52:14 +00:00
Chris Lattner eb958b0e45 add an argument.
llvm-svn: 21254
2005-04-12 18:51:53 +00:00
Chris Lattner 95f16a3ac4 Get rid of this for_each loop
llvm-svn: 21253
2005-04-12 18:51:33 +00:00
Duraid Madina fd469bddac * OK, after changing to use liveIn/liveOut instead of IDEFs,
to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.

FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:

out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127

and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)

llvm-svn: 21252
2005-04-12 18:42:59 +00:00
Andrew Lenharth 740f93ca10 Get rid of idefs for arguments (oops)
llvm-svn: 21251
2005-04-12 17:47:57 +00:00
Andrew Lenharth 10c6eb4be2 Get rid of idefs for arguments
llvm-svn: 21250
2005-04-12 17:35:16 +00:00
Chris Lattner 14f72885dd Put out* into the allocation order, allowing the register allocator to
coallesce moves into outgoing args.

llvm-svn: 21249
2005-04-12 15:12:51 +00:00
Chris Lattner 6b91767b77 Make sure to realize that calls use their argument regs
llvm-svn: 21248
2005-04-12 15:12:19 +00:00
Duraid Madina b6dfb227b7 stop emitting IDEFs for args - change to using liveIn/liveOut
llvm-svn: 21247
2005-04-12 14:54:44 +00:00
Nate Begeman f67f3bf627 Initial support for allocation condition registers
llvm-svn: 21246
2005-04-12 07:04:16 +00:00
Chris Lattner 6febe5ef40 Fix a crash analyzing MultiSource/Benchmarks/MallocBench/gs
llvm-svn: 21245
2005-04-12 03:59:27 +00:00