Commit Graph

4717 Commits

Author SHA1 Message Date
Brian Gaeke aa91eae6af lib/Target/X86/InstSelectSimple.cpp: Add visitCallInst, visitCastInst.
llvm-svn: 4821
2002-11-22 11:07:01 +00:00
Chris Lattner d2b1b2c8ac Make testcase more interesting
llvm-svn: 4820
2002-11-21 23:30:08 +00:00
Chris Lattner e5330c4adf Handle cmp Reg, 0 correctly
llvm-svn: 4819
2002-11-21 23:30:00 +00:00
Chris Lattner f435afc268 Printing support for more stuff
llvm-svn: 4818
2002-11-21 22:49:46 +00:00
Chris Lattner 174a94007d Don't add implicit operands
llvm-svn: 4817
2002-11-21 22:49:20 +00:00
Chris Lattner b35341ee25 Fix off by one bug
llvm-svn: 4816
2002-11-21 22:48:15 +00:00
Chris Lattner af7bd2c6b5 Add fixme
llvm-svn: 4815
2002-11-21 22:48:01 +00:00
Chris Lattner 1c80d37765 Minor code cleanups
llvm-svn: 4814
2002-11-21 21:04:50 +00:00
Chris Lattner 4fbd8a2f78 Implement printing of store instructions
llvm-svn: 4813
2002-11-21 21:03:39 +00:00
Chris Lattner 61fafd35f5 The big change here is to handle printing/emission of X86II::MRMSrcMem
instructions.  Right now the only users are load instructions, and Misha's
spill code

llvm-svn: 4812
2002-11-21 20:44:15 +00:00
Chris Lattner cf7c225e06 Remove implicit information from instruction selector
llvm-svn: 4811
2002-11-21 18:54:29 +00:00
Chris Lattner e8885d949a Add printing information for MUL and DIV
llvm-svn: 4810
2002-11-21 18:54:14 +00:00
Chris Lattner 5e50475adb Fix a bug that prevented compilation of multiple functions
llvm-svn: 4809
2002-11-21 17:26:58 +00:00
Chris Lattner 3d8fc7fc85 Move test
llvm-svn: 4808
2002-11-21 17:20:32 +00:00
Chris Lattner 61574bb7ad Shuffle testcases around
llvm-svn: 4807
2002-11-21 17:20:12 +00:00
Chris Lattner 76116fae3e New testcase
llvm-svn: 4806
2002-11-21 17:18:37 +00:00
Chris Lattner 7939ecc8eb Remove opcode information for instructions that are completely defined now
llvm-svn: 4805
2002-11-21 17:12:55 +00:00
Chris Lattner 1f9530508b Add printing support for sahf & setcc
llvm-svn: 4804
2002-11-21 17:10:57 +00:00
Chris Lattner c868841ad6 Add printing support for /0 /1 type instructions
llvm-svn: 4803
2002-11-21 17:09:01 +00:00
Chris Lattner a6eb52fcf7 Add support for /0 /1, etc type instructions
llvm-svn: 4802
2002-11-21 17:08:49 +00:00
Chris Lattner 903a25d225 User defined operators are not supposed to live beyond the lifetime of the
pass.  Detect and flag them.

llvm-svn: 4801
2002-11-21 16:54:22 +00:00
Chris Lattner 41e2d4cdcf Rename the SetCC X86 instructions to reflect the fact that they are the
register versions

llvm-svn: 4800
2002-11-21 16:19:42 +00:00
Chris Lattner 45ddd59da5 Simplify setcc code a bit
llvm-svn: 4799
2002-11-21 15:52:38 +00:00
Chris Lattner 177e928a46 Support Registers of the form (B8+ rd) for example
llvm-svn: 4798
2002-11-21 02:00:20 +00:00
Chris Lattner 3a3ac9d225 Dont' set flags
llvm-svn: 4797
2002-11-21 01:59:50 +00:00
Chris Lattner 6985c19b61 Implement printing more, implement opcode output more
llvm-svn: 4796
2002-11-21 01:33:44 +00:00
Chris Lattner dfbfd81217 Huge diff do to reindeinting comments.
Basically just adds OpSize flags for instructions that need them.

llvm-svn: 4795
2002-11-21 01:33:28 +00:00
Chris Lattner c48d0fa9a2 Add new prefix flag
llvm-svn: 4794
2002-11-21 01:32:55 +00:00
Chris Lattner f03132f014 Print another class of instructions correctly, giving us: xorl EDX, EDX
for example.

llvm-svn: 4793
2002-11-21 00:30:01 +00:00
Misha Brukman 95e6287734 Booleans are types too. And they get stored in bytes. And InstructionSelection
doesn't assert fail. And everyone's happy. Yay!

llvm-svn: 4792
2002-11-21 00:25:56 +00:00
Chris Lattner 185972c7e6 Checkin testcases for bugpoint
llvm-svn: 4791
2002-11-20 22:30:02 +00:00
Chris Lattner 12caa7a9cf Build bugpoint
llvm-svn: 4790
2002-11-20 22:28:18 +00:00
Chris Lattner 73a6bdd958 Initial checkin of bugpoint
llvm-svn: 4789
2002-11-20 22:28:10 +00:00
Chris Lattner e4dbb1af42 Initial checkin of Module cloning support stuff
llvm-svn: 4788
2002-11-20 20:47:41 +00:00
Chris Lattner a35d7412c6 Cloning stuff doesn't modify the source module
llvm-svn: 4787
2002-11-20 20:22:58 +00:00
Chris Lattner c4841a7738 X86 target builds fine now
llvm-svn: 4786
2002-11-20 20:17:03 +00:00
Chris Lattner 8016a16ed0 Fix symbol table problem
llvm-svn: 4785
2002-11-20 19:32:43 +00:00
Misha Brukman 53d2de923a Add definitions for function headers from MRegisterInfo.h:
Some functions are in X86RegisterInfo.cpp, others, because of the data they
need, are in X86RegisterClasses.cpp, which also defines some register classes:
byte, short, and int.

llvm-svn: 4784
2002-11-20 18:59:43 +00:00
Misha Brukman 6e5d493e0f Check not only for MO_VirtualRegister, but MO_MachineRegister as well when
printing out assembly. After all, we want the real thing too.

llvm-svn: 4783
2002-11-20 18:56:41 +00:00
Misha Brukman d5b111a10c Initialize the SSARegMap.
llvm-svn: 4782
2002-11-20 18:55:27 +00:00
Misha Brukman 45f6b8410e MRegisterInfo.h - Added prototypes for functions we need to map a register to
an appropriate TargetRegisterClass, also adds TargetRegisterClass definition.
TargetMachine.h - speling.

llvm-svn: 4781
2002-11-20 18:54:53 +00:00
Chris Lattner 55d5f15a40 Don't build X86 target yet
llvm-svn: 4780
2002-11-20 18:37:37 +00:00
Chris Lattner 98cf1f5d64 - Eliminated the deferred symbol table stuff in Module & Function, it really
wasn't an optimization and it was causing lots of bugs.

llvm-svn: 4779
2002-11-20 18:36:02 +00:00
Chris Lattner 7c6d9d9eac Fix minor bugs
llvm-svn: 4778
2002-11-20 18:32:31 +00:00
Chris Lattner b251c3d727 Eliminate the concept of a deferred symbol table. The optimization really isn't,
and it causes obscure bugs to show up in passes.

llvm-svn: 4777
2002-11-20 18:07:48 +00:00
Misha Brukman eaaceb1210 Add mapping in MachineFunction from SSA regs to Register Classes. Also,
uncovered a bug where registers were not being put in a map if they were not
found...

llvm-svn: 4776
2002-11-20 00:58:23 +00:00
Misha Brukman ade1143692 Sigh. Fixed some speling.
llvm-svn: 4775
2002-11-20 00:56:42 +00:00
Misha Brukman a5381b4932 SSARegMap -- the mapping between SSARegisters and their RegisterClasses, which
imply types of SSA Registers. This is on a per-function basis, so the
MachineFunction contains the SSARegMap, and has accessor functions to it.

llvm-svn: 4774
2002-11-20 00:53:10 +00:00
Misha Brukman 310afc5f8c Thanks to the R8, R16, and R32 macros, I can now deal with registers that
belong to different register classes easier.

llvm-svn: 4773
2002-11-20 00:47:40 +00:00
Chris Lattner 84dd0f4767 Remove unneccesary #include
llvm-svn: 4772
2002-11-19 23:12:53 +00:00