02b5a1b50f
[AVX-512] Replace masked 16-bit element variable shift intrinsics with new unmasked versions and selects.
...
The same thing was done to 32-bit and 64-bit element sizes previously.
This will allow us to support these shuffls in InstCombineCalls along with the other variable shift intrinsics.
llvm-svn: 287312
2016-11-18 05:04:44 +00:00
b110e04851
[AVX-512] Remove masked pmovzx/pmovsx builtins and autoupgrade them to selects and native zext/sext.
...
This mostly reuses earlier autoupgrade support for the sse and avx equivalents. Just needed to add the code to add the select.
llvm-svn: 286092
2016-11-07 02:12:57 +00:00
7e545335d6
[AVX-512] Remove 128/256 masked pshufb intrinsics. Autoupgrade them to legacy intrinsics and a select.
...
llvm-svn: 286089
2016-11-07 00:13:39 +00:00
af9b3fe752
[AVX-512] Remove intrinsics for 128/256-bit masked shift by immediate. Instead upgrade them to a select and the older SSE/AVX2 intrinsic.
...
llvm-svn: 286072
2016-11-06 16:29:14 +00:00
c9467ed31e
[AVX-512] Remove intrinsics for 128/256-bit masked shift by single element in xmm. Instead upgrade them to a select and the older SSE/AVX2 intrinsic.
...
llvm-svn: 286070
2016-11-06 16:29:08 +00:00
8ec5c7326d
[AVX-512] Remove masked pmin/pmax intrinsics and autoupgrade to native IR.
...
Clang patch to replace 512-bit vector and 64-bit element versions with native IR will follow.
llvm-svn: 284955
2016-10-24 04:04:16 +00:00
61403201ea
[X86,AVX-512] Use INSERT_SUBREG instead of SUBREG_TO_REG when the input is not the output of an instruction.
...
SUBREG_TO_REG is supposed to indicate that the super register has been zeroed, but we can't prove that if we don't know where it came from.
llvm-svn: 281885
2016-09-19 02:53:43 +00:00
af0d63d2e7
[AVX-512] Remove masked integer add/sub/mull intrinsics and upgrade to native IR.
...
llvm-svn: 280611
2016-09-04 02:09:53 +00:00
6daefcf626
X86-FMA3: Implemented commute transformation for EVEX/AVX512 FMA3 opcodes.
...
This helped to improved memory-folding and register coalescing optimizations.
Also, this patch fixed the tracker #17229 .
Reviewer: Craig Topper.
Differential Revision: https://reviews.llvm.org/D23108
llvm-svn: 278431
2016-08-11 22:07:33 +00:00
dca03bebd3
AVX-512: Changed lowering of BITCAST between i1 vectors and i8/i16/i32 integer values
...
Optimized lowering of BITCAST node. The BITCAST node can be replaced with COPY_TO_REG instead of KMOV.
It allows to suppress two opposite BITCAST operations and avoid redundant "movs".
Differential Revision: https://reviews.llvm.org/D23247
llvm-svn: 277958
2016-08-07 13:05:58 +00:00
4c53e60360
[AVX512] Add VLX packed move instructions to the execution dependency fix pass and update tests.
...
llvm-svn: 277304
2016-07-31 20:20:01 +00:00
318e40b6f7
[AVX512] Add some additional patterns so that we can fold broadcast loads in the first argument of an FMADD/FMSUB/FNMADD/FNMSUB/FMADDSUB/FMSUBADD node. Also add patterns to support all combinations of the broadcast input and the preserved input for masked versions.
...
llvm-svn: 276614
2016-07-25 07:20:31 +00:00
6bcbf5338c
[AVX512] Cleanup FMA operand order in patterns to match the VEX versions and to really be 213, 231, and 132.
...
llvm-svn: 276613
2016-07-25 07:20:28 +00:00
f4151bea72
[AVX512] Add initial support for the Execution Domain fixing pass to change some EVEX instructions.
...
llvm-svn: 276393
2016-07-22 05:00:52 +00:00
d6ca1dc45e
[AVX512] Give priority to EVEX encoded PSHUFB over the VEX versions.
...
llvm-svn: 275942
2016-07-19 02:00:38 +00:00
5c913e84df
[AVX512] Use VMOVAPSZ128rr/VMOVAPS256rr for VR128X/VR256X physreg moves when VLX is supported.
...
Ideally we would use VEX encoded moves instead of EVEX if the high 16 registers aren't referenced, but this a good first step.
llvm-svn: 275763
2016-07-18 06:14:34 +00:00
152e7c8b12
VirtRegMap: Replace some identity copies with KILL instructions.
...
An identity COPY like this:
%AL = COPY %AL, %EAX<imp-def>
has no semantic effect, but encodes liveness information: Further users
of %EAX only depend on this instruction even though it does not define
the full register.
Replace the COPY with a KILL instruction in those cases to maintain this
liveness information. (This reverts a small part of r238588 but this
time adds a comment explaining why a KILL instruction is useful).
llvm-svn: 274952
2016-07-09 00:19:07 +00:00
4e96fbf3c1
[X86][AVX512] Autoupgrade the BROADCAST intrinsics
...
llvm-svn: 274550
2016-07-05 13:58:47 +00:00
68f438a036
[X86][AVX512] Add support for PMOVZX masked shuffle comments
...
llvm-svn: 274461
2016-07-03 13:33:28 +00:00
597aa42fec
[AVX512] Remove masked unpack intrinsics and autoupgrade to vectorshuffle and selects.
...
llvm-svn: 273543
2016-06-23 07:37:33 +00:00
283418fbb6
[AVX512] Add patterns for any-extending a mask that use the def of KMOVW/KMOVB without going through an EXTRACT_SUBREG and a MOVZX.
...
llvm-svn: 273253
2016-06-21 07:37:32 +00:00
0a0fb0fda1
[AVX512] Remove the masked vpcmpeq/vcmpgt intrinsics and autoupgrade them to native icmps.
...
llvm-svn: 273240
2016-06-21 03:53:24 +00:00
13cf7cac07
[AVX512] Remove maksed pshufd, pshuflw, and phufhw intrinsics and autoupgrade them to selects and shufflevector.
...
llvm-svn: 272527
2016-06-13 02:36:48 +00:00
89c1761474
[AVX512] Fix shuffle comment printing to handle the masked versions of some shuffles. Previously we were printing the mask operands as the register names.
...
llvm-svn: 272367
2016-06-10 04:48:05 +00:00
f635367e2b
[AVX512] Remove masked_move/blendm intrinsic from back-end.
...
This is complement patch to D21060.
Differential Revision: http://reviews.llvm.org/D21174
llvm-svn: 272257
2016-06-09 11:46:55 +00:00
6f7288dc44
[AVX512] Fix shuffle decode printing for several instructions with write masks. There are still more bugs here with UNPCK and PALIGN for sure. But these were the easiest ones to fix.
...
llvm-svn: 272252
2016-06-09 07:49:08 +00:00
33350cc406
[AVX512] Remove masked palignr intrinsics and auto-upgrade them to native IR of vector shuffle and select.
...
llvm-svn: 271872
2016-06-06 06:12:54 +00:00
e7ae106147
[AVX512] Ensure EVEX vpshufd, vpshuflw, and vpshufhw have isel priority over the VEX encoded ones.
...
llvm-svn: 271629
2016-06-03 05:31:04 +00:00
01f53b1773
[AVX512] Fix shuffle comment printing for EVEX encoded PSHUFD, PSHUFHW, and PSHUFLW.
...
llvm-svn: 271628
2016-06-03 05:31:00 +00:00
f10fbfa738
[AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead.
...
The intrinsics will be autoupgraded to the same generic masked loads.
llvm-svn: 271478
2016-06-02 04:19:36 +00:00
4f2d5a68d3
Revert r271362 "[AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead."
...
Looks like something isn't quite right still. Also forgot to move the test cases to an autoupgrade test.
llvm-svn: 271363
2016-06-01 05:57:55 +00:00
dacd9d2bac
[AVX512] Remove masked load intrinsics. Clang now emits generic masked load intrinsics instead.
...
The intrinsics will be autoupgraded to the same generic masked loads.
llvm-svn: 271362
2016-06-01 05:35:16 +00:00
50f85c22c5
[AVX512] Remove masked store intrinsics. Clang now emits generic masked store intrinsics instead.
...
The intrinsics will be autoupgraded to the same generic masked stores.
llvm-svn: 271245
2016-05-31 01:50:02 +00:00
23c2090606
[llvm][AVX512][intrinsics] Fix vperm{b|w|d|q|ps|pd} intrinsics. Index is second argument to buildin function but it is first instruction operand.
...
Differential Revision: http://reviews.llvm.org/D20515
llvm-svn: 270548
2016-05-24 11:06:22 +00:00
1a23a521bb
[AVX512] Use update_llc_test_checks to update some tests so we can see all the instruction encodings and ensure everything is with EVEX.
...
llvm-svn: 270315
2016-05-21 05:46:58 +00:00
d8a9c0d120
[AVX512] Fix types for pshufd intrinsics. The immediate is the second argument and the mask is the 4th argument. Also move the 128/256 tests to the right test file.
...
Prior to this the immediate was a strange 16-bits and the 512-bit intrinsic couldn't receive the full 16 mask bits it needs.
llvm-svn: 269526
2016-05-14 00:47:18 +00:00
217b886b10
[X86][AVX512] Moved CHECKs inside functions to stop update_llc_test_checks going haywire
...
I'm not going to regenerate these anytime soon but do have some diffs to apply that I'd like to do with update_llc_test_checks
llvm-svn: 269420
2016-05-13 14:47:55 +00:00
b6da65403a
[AVX512] VPACKUSWB/VPACKSSWB should not be encoded with EVEX.W=1. While there fix the execution domain for VPACKSSDW/VPACKUSDW.
...
llvm-svn: 268200
2016-05-01 17:38:32 +00:00
e430de8be6
[AVX512] Prefer AVX512 VPACK instructions over AVX/AVX2 instructions when VLX and BWI are supported.
...
llvm-svn: 268189
2016-05-01 06:52:19 +00:00
8f9e26964a
fix CHECK_LABEL -> CHECK-LABEL
...
llvm-svn: 264671
2016-03-28 21:56:48 +00:00
a1e5ef624c
trailing whitespace
...
llvm-svn: 264670
2016-03-28 21:52:53 +00:00
c4d054fa4a
[LLVM][AVX512] PSRLWI Chnage imm8 to int
...
Differential Revision: http://reviews.llvm.org/D17753
llvm-svn: 262592
2016-03-03 08:54:05 +00:00
927fdaee88
[LLVM][AVX512]PSRAWI Change imm8 to int.
...
Differential Revision: http://reviews.llvm.org/D17705
llvm-svn: 262480
2016-03-02 12:05:07 +00:00
96836fc81c
[AVX512][PSLLW ][PSLLV] Change imm8 to int
...
Differential Revision: http://reviews.llvm.org/D17684
llvm-svn: 262176
2016-02-28 07:32:10 +00:00
a1f2d27da2
[LLVM][AVX512][PSHUFHW ][PSHUFLW ] Change imm8 to int
...
Differential Revision: http://reviews.llvm.org/D17538
llvm-svn: 261725
2016-02-24 08:39:05 +00:00
0aeda37464
AVX512: VPBROADCASTB/W/D/Q from GPR intrinsics implementation.
...
Differential Revision: http://reviews.llvm.org/D16813
llvm-svn: 260024
2016-02-07 08:30:50 +00:00
0acc32a3b3
[X86][AVX512] Added support for VPMOVZX shuffle decoding.
...
llvm-svn: 260007
2016-02-06 19:51:21 +00:00
86528270b9
AVX-512: Fixed a bug in FMA instruction selection on KNL
...
The FMA instruction was selected from AVX2 set instead of AVX-512
Differential Revision: http://reviews.llvm.org/D16884
llvm-svn: 259792
2016-02-04 15:11:11 +00:00
1bd7f993fc
[AVX512] Adding PTESTNMB/D/W/Q instruction
...
Differential Revision: http://reviews.llvm.org/D16520
llvm-svn: 258688
2016-01-25 14:43:23 +00:00
19670d479a
[AVX512] Adding PTESTMB/W/D/Q instruction
...
Differential Revision: http://reviews.llvm.org/D16519
llvm-svn: 258686
2016-01-25 13:27:32 +00:00
Craig Topper