Commit Graph

28051 Commits

Author SHA1 Message Date
Vladimir Medic 435cf8a415 [Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions.
llvm-svn: 226652
2015-01-21 10:47:36 +00:00
Craig Topper 620b50cc23 [X86] Convert all the i8imm used by SSE and AVX instructions to u8imm.
This makes the assembler check their size and removes a hack from the disassembler to avoid sign extending the immediate.

llvm-svn: 226645
2015-01-21 08:15:54 +00:00
Craig Topper f38dea1cfa [x86] Add assembly parser bounds checking to the immediate value for cmpss/cmpsd/cmpps/cmppd.
llvm-svn: 226642
2015-01-21 06:07:53 +00:00
Adrian Prantl 34bcbeed03 Make DIExpression::Verify() stricter by checking that the number of
elements and the ordering is sane and cleanup the accessors.

llvm-svn: 226627
2015-01-21 00:59:20 +00:00
Simon Pilgrim f5dcc1cbe6 [X86][AVX] Simplified diff between AVX1 and SSE42 fp stack folding tests. NFC.
Changed the AVX1 tests register spill tail call to return a xmm like the SSE42 version - makes doing diffs between them a lot easier without affecting the spills themselves.

llvm-svn: 226623
2015-01-21 00:02:13 +00:00
Simon Pilgrim 0177fa3d8c [X86][SSE] Added SSE/AVX1 integer stack folding tests.
Some folding patterns + tests are missing (marked as TODO) - these will be added in a future patch for review.

llvm-svn: 226622
2015-01-20 23:54:17 +00:00
Simon Pilgrim ffddc01b00 [X86][SSE] Added SSE fp stack folding tests.
Some folding patterns + tests are missing (marked as TODO) - these will be added in a future patch for review.

llvm-svn: 226621
2015-01-20 23:50:18 +00:00
Simon Pilgrim 0d68d98bd5 [X86][AVX] Renamed AVX1 fp stack folding tests. NFC.
The SSE42 version of the AVX1 float stack folding tests will be added shortly, this renames the AVX1 file so that the files will be near each other in a directory listing to help ensure they are kept in sync.

llvm-svn: 226620
2015-01-20 23:45:50 +00:00
Adrian Prantl de200dfad2 DebugLocs without a scope should fail the verification.
Follow-up to r226588.

llvm-svn: 226616
2015-01-20 22:37:25 +00:00
Kevin Enderby 98da6136d0 For llvm-objdump, hook up existing options to work when using -macho (the Mach-O parser).
llvm-svn: 226612
2015-01-20 21:47:46 +00:00
Colin LeMahieu 988c68f2a7 [Hexagon] Adding intrinsics for doubleword ALU operations.
llvm-svn: 226606
2015-01-20 20:45:05 +00:00
Colin LeMahieu 734001c0a6 [Hexagon] Removing unnecessary clutter in intrinsic tests.
llvm-svn: 226602
2015-01-20 19:46:07 +00:00
Daniel Jasper 6b77455f81 Prevent binary-tree deterioration in sparse switch statements.
This addresses part of llvm.org/PR22262. Specifically, it prevents
considering the densities of sub-ranges that have fewer than
TLI.getMinimumJumpTableEntries() elements. Those densities won't help
jump tables.

This is not a complete solution but works around the most pressing
issue.

Review: http://reviews.llvm.org/D7070
llvm-svn: 226600
2015-01-20 19:43:33 +00:00
Ramkumar Ramachandra be10ece5ed [GC] Verify-pass void vararg functions in gc.statepoint
With the appropriate Verifier changes, exactracting the result out of a
statepoint wrapping a vararg function crashes. However, a void vararg
function works fine: commit this first step.

Differential Revision: http://reviews.llvm.org/D7071

llvm-svn: 226599
2015-01-20 19:42:46 +00:00
Adrian Prantl 565cc18d8f Reapply: Teach SROA how to update debug info for fragmented variables.
This reapplies r225379.

ChangeLog:
- The assertion that this commit previously ran into about the inability
  to handle indirect variables has since been removed and the backend
  can handle this now.
- Testcases were upgrade to the new MDLocation format.
- Instead of keeping a DebugDeclares map, we now use
  llvm::FindAllocaDbgDeclare().

Original commit message follows.

Debug info: Teach SROA how to update debug info for fragmented variables.
This allows us to generate debug info for extremely advanced code such as

 typedef struct { long int a; int b;} S;

 int foo(S s) {
   return s.b;
 }

which at -O1 on x86_64 is codegen'd into

 define i32 @foo(i64 %s.coerce0, i32 %s.coerce1) #0 {
   ret i32 %s.coerce1, !dbg !24
 }

with this patch we emit the following debug info for this

 TAG_formal_parameter [3]
   AT_location( 0x00000000
                0x0000000000000000 - 0x0000000000000006: rdi, piece 0x00000008, rsi, piece 0x00000004
                0x0000000000000006 - 0x0000000000000008: rdi, piece 0x00000008, rax, piece 0x00000004 )
                AT_name( "s" )
                AT_decl_file( "/Volumes/Data/llvm/_build.ninja.release/test.c" )

Thanks to chandlerc, dblaikie, and echristo for their feedback on all
previous iterations of this patch!

llvm-svn: 226598
2015-01-20 19:42:22 +00:00
Tom Stellard 021053f500 R600/SI: Fix simple-loop.ll test
llvm-svn: 226596
2015-01-20 19:33:02 +00:00
Jozef Kolek 0d49117769 Reverted revision 226577.
llvm-svn: 226595
2015-01-20 19:29:28 +00:00
Tom Stellard 8255af45cb R600/SI: Add kill flag when copying scratch offset to a register
This allows us to re-use the same register for the scratch offset
when accessing large private arrays.

llvm-svn: 226585
2015-01-20 17:49:45 +00:00
Tom Stellard 8058069529 R600/SI: Don't store scratch buffer frame index in MUBUF offset field
We don't have a good way of legalizing this if the frame index offset
is more than the 12-bits, which is size of MUBUF's offset field, so
now we store the frame index in the vaddr field.

llvm-svn: 226584
2015-01-20 17:49:43 +00:00
Jozef Kolek 45f7f9c1ab [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B
Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514

llvm-svn: 226577
2015-01-20 16:45:27 +00:00
Kai Nacke e7a647886a [mips] Add registers and ALL check prefix to octeon test case.
No functional change.

Reviewed by D. Sanders

llvm-svn: 226574
2015-01-20 16:14:02 +00:00
Kai Nacke 63072f81b3 [mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132
This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132.
It also includes patterns for instruction selection and test cases.

Reviewed by D. Sanders

llvm-svn: 226573
2015-01-20 16:10:51 +00:00
Evgeniy Stepanov c5b974e6d2 [msan] Optimize -msan-check-constant-shadow.
The new code does not create new basic blocks in the case when shadow is a
compile-time constant; it generates either an unconditional __msan_warning
call or nothing instead.

llvm-svn: 226569
2015-01-20 15:21:35 +00:00
Chandler Carruth aaf0b4cd57 [PM] Port LoopInfo to the new pass manager, adding both a LoopAnalysis
pass and a LoopPrinterPass with the expected associated wiring.

I've added a RUN line to the only test case (!!!) we have that actually
prints loops. Everything seems to be working.

This is somewhat exciting as this is the first analysis using another
analysis to go in for the new pass manager. =D I also believe it is the
last analysis necessary for porting instcombine, but of course I may yet
discover more.

llvm-svn: 226560
2015-01-20 10:58:50 +00:00
Karthik Bhat 0b0f4660fa Fix Operandreorder logic in SLPVectorizer to generate longer vectorizable chain.
This patch fixes 2 issues in reorderInputsAccordingToOpcode
1) AllSameOpcodeLeft and AllSameOpcodeRight was being calculated incorrectly resulting in code not being vectorized in few cases.
2) Adds logic to reorder operands if we get longer chain of consecutive loads enabling vectorization. Handled the same for cases were we have AltOpcode.
Thanks Michael for inputs and review.
Review: http://reviews.llvm.org/D6677

llvm-svn: 226547
2015-01-20 06:11:00 +00:00
David Majnemer 3087b22e1a Bitcode: Don't create comdats when autoupgrading macho bitcode
Don't infer COMDAT groups from older bitcode if the target is macho,
it doesn't have COMDATs.

llvm-svn: 226546
2015-01-20 05:58:07 +00:00
Frederic Riss e4a6fef98f [dsymutil] Add the detected target triple to the debug map.
It will be needed to instantiate the Target object that we will
use to create all the MC objects for the dwarf emission.

llvm-svn: 226525
2015-01-19 23:33:14 +00:00
Duncan P. N. Exon Smith 13890af51c AsmParser: Fix error location for missing fields
llvm-svn: 226524
2015-01-19 23:32:36 +00:00
Simon Pilgrim 20bc37c7db [X86][AVX] Missing AVX1 memory folding float instructions
Now that we can create much more exhaustive X86 memory folding tests, this patch adds the missing AVX1/F16C floating point instruction stack foldings we can easily test for including the scalar intrinsics (add, div, max, min, mul, sub), conversions float/int to double, half precision conversions, rounding, dot product and bit test. The patch also adds a couple of obviously missing SSE instructions (more to follow once we have full SSE testing).

Now that scalar folding is working it broke a very old test (2006-10-07-ScalarSSEMiscompile.ll) - this test appears to make no sense as its trying to ensure that a scalar subtraction isn't folded as it 'would zero the top elts of the loaded vector' - this test just appears to be wrong to me.

Differential Revision: http://reviews.llvm.org/D7055

llvm-svn: 226513
2015-01-19 22:40:45 +00:00
Rafael Espindola 2658554aec Add r224985 back with fixes.
The fixes are to note that AArch64 has additional restrictions on when local
relocations can be used. In particular, ld64 requires that relocations to
cstring/cfstrings use linker visible symbols.

Original message:

In an assembly expression like

bar:
  .long L0 + 1

the intended semantics is that bar will contain a pointer one byte past L0.

In sections that are merged by content (strings, 4 byte constants, etc), a
single position in the section doesn't give the linker enough information.
For example, it would not be able to tell a relocation must point to the
end of a string, since that would look just like the start of the next.

The solution used in ELF to use relocation with symbols if there is a non-zero
addend.

In MachO before this patch we would just keep all symbols in some sections.

This would miss some cases (only cstrings on x86_64 were implemented) and was
inefficient since most relocations have an addend of 0 and can be represented
without the symbol.

This patch implements the non-zero addend logic for MachO too.

llvm-svn: 226503
2015-01-19 21:11:14 +00:00
Colin LeMahieu 0ee02fc9fe [Hexagon] Updating muxir/ri/ii intrinsics. Setting predicate registers as compatible with i32 rather than doing custom type conversion.
llvm-svn: 226500
2015-01-19 20:31:18 +00:00
Colin LeMahieu fcd4569af6 [Hexagon] Converting intrinsics combine imm/imm, simple shifts and extends.
llvm-svn: 226483
2015-01-19 18:56:19 +00:00
Colin LeMahieu 9327bdad2f [Hexagon] Converting remaining ALU32/ALU intrinsics.
llvm-svn: 226480
2015-01-19 18:33:58 +00:00
Colin LeMahieu 663419b008 [Hexagon] Converting ALU32/ALU intrinsics to new patterns.
llvm-svn: 226478
2015-01-19 18:22:19 +00:00
Adrian Prantl 5883af3faa Remove support for DIVariable's FlagIndirectVariable and expect
frontends to use a DIExpression with a DW_OP_deref instead.

This is not only a much more natural place for this informationl; there
is also a technical reason: The FlagIndirectVariable is used to mark a
variable that is turned into a reference by virtue of the calling
convention; this happens for example to aggregate return values.
The inliner, for example, may actually need to undo this indirection to
correctly represent the value in its new context. This is impossible to
implement because the DIVariable can't be safely modified. We can however
safely construct a new DIExpression on the fly.

llvm-svn: 226476
2015-01-19 17:57:29 +00:00
Greg Fitzgerald fa78d08675 [AArch64] Implement GHC calling convention
Original patch by Luke Iannini.  Minor improvements and test added by
Erik de Castro Lopo.

Differential Revision: http://reviews.llvm.org/D6877

From: Erik de Castro Lopo <erikd@mega-nerd.com>
llvm-svn: 226473
2015-01-19 17:40:05 +00:00
Colin LeMahieu 310bad8b7e [Hexagon] Converting halfword to double accumulating multiply intrinsics.
llvm-svn: 226472
2015-01-19 17:36:32 +00:00
Rafael Espindola c569ac46eb Produce errors when an assignment expression would use a common symbol.
An assignment will produce a symbol with a given section and offset. There is
no way to represent something like "1 byte after a common symbol".

This matches the behavior of GNU as.

Part of PR22217.

llvm-svn: 226470
2015-01-19 17:30:24 +00:00
Bradley Smith 3131e85edd [ARM] SSAT/USAT with an 'asr #32' shift should result in an undefined encoding rather than unpredictable
llvm-svn: 226469
2015-01-19 16:37:17 +00:00
Bradley Smith 30057b245e [ARM] Fixup sign extend instruction availability w.r.t. DSP extension
llvm-svn: 226468
2015-01-19 16:36:02 +00:00
Rafael Espindola 12ca34f53f Bring r226038 back.
No change in this commit, but clang was changed to also produce trivial comdats when
needed.

Original message:

Don't create new comdats in CodeGen.

This patch stops the implicit creation of comdats during codegen.

Clang now sets the comdat explicitly when it is required. With this patch clang and gcc
now produce the same result in pr19848.

llvm-svn: 226467
2015-01-19 15:16:06 +00:00
Michael Kuperstein 54c61edee7 [MIScheduler] Slightly better handling of constrainLocalCopy when both source and dest are local
This fixes PR21792.

Differential Revision: http://reviews.llvm.org/D6823

llvm-svn: 226433
2015-01-19 07:30:47 +00:00
Hal Finkel af51993ee1 [PowerPC] Add r2 as an operand for all calls under both PPC64 ELF V1 and V2
Our PPC64 ELF V2 call lowering logic added r2 as an operand to all direct call
instructions in order to represent the dependency on the TOC base pointer
value. Restricting this to ELF V2, however, does not seem to make sense: calls
under ELF V1 have the same dependence, and indirect calls have an r2 dependence
just as direct ones. Make sure the dependence is noted for all calls under both
ELF V1 and ELF V2.

llvm-svn: 226432
2015-01-19 07:20:27 +00:00
Matt Arsenault 4843f193ad R600: Remove redundant test
This is already covered in ftrunc.ll

llvm-svn: 226412
2015-01-18 19:30:32 +00:00
Daniel Sanders 01dce6c931 [mips] 'CHECK :' is not a valid check directive. Fixed.
llvm-svn: 226409
2015-01-18 18:43:10 +00:00
Daniel Sanders 0cb9dc6e68 [mips] Make whitespace in disassembler tests more consistent. NFC.
The tests for the ISA's should now be approximately diffable. That is, the
output of 'diff valid-mips1.txt valid-mips2.txt' should be emit the lines
for instructions that were added/removed to/from MIPS-I by MIPS-II. This
doesn't work perfectly at the moment due to ordering differences but it
should be close.

llvm-svn: 226408
2015-01-18 18:38:36 +00:00
Daniel Sanders 46ad7cbfce [mips] Make whitespace of disassembler tests more consistent by removing blank lines. NFC.
llvm-svn: 226407
2015-01-18 18:21:19 +00:00
Simon Pilgrim 4cf275eab2 [X86][SSE] Added scalar min/max folding tests. NFC.
llvm-svn: 226406
2015-01-18 18:06:23 +00:00
Simon Pilgrim 1d6dcdcacb [X86][SSE] Added float extract and xmm extract/insert stack folding tests. NFC.
llvm-svn: 226405
2015-01-18 17:04:32 +00:00
Simon Pilgrim cd26d0b611 [X86][SSE] Added scalar conversion stack folding tests. NFC.
llvm-svn: 226404
2015-01-18 16:22:15 +00:00