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Commit Graph

Author	SHA1	Message	Date
Pengxuan Zheng	85aff8a4e4	[RISCV] Update debug scratch register names Summary: The RISC-V debug register was named dscratch in a previous draft of the RISC-V debug mode spec. The number of registers has been increased to 2 in the latest ratified version of the debug mode spec and the registers were named dscratch0 and dscratch1. We still support using the old register name "dscratch", but it would be disassembled as "dscratch0" with this change. Reviewers: apazos, asb, lenary, luismarques Reviewed By: asb Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78764	2020-05-05 08:46:07 -07:00
Ana Pazos	9d6c55323f	[RISCV] Support named operands for CSR instructions. Reviewers: asb, mgrang Reviewed By: asb Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones Differential Revision: https://reviews.llvm.org/D46759 llvm-svn: 343822	2018-10-04 21:50:54 +00:00

Author

SHA1

Message

Date

Pengxuan Zheng

85aff8a4e4

[RISCV] Update debug scratch register names

Summary:
The RISC-V debug register was named dscratch in a previous draft of the RISC-V
debug mode spec. The number of registers has been increased to 2 in the latest
ratified version of the debug mode spec and the registers were named dscratch0
and dscratch1. We still support using the old register name "dscratch", but it
would be disassembled as "dscratch0" with this change.

Reviewers: apazos, asb, lenary, luismarques

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78764

2020-05-05 08:46:07 -07:00

Ana Pazos

9d6c55323f

[RISCV] Support named operands for CSR instructions.

Reviewers: asb, mgrang

Reviewed By: asb

Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones

Differential Revision: https://reviews.llvm.org/D46759

llvm-svn: 343822

2018-10-04 21:50:54 +00:00

2 Commits