llvm-project

Commit Graph

Author	SHA1	Message	Date
Nico Rieck	78199518c4	Rename inst_range() to instructions() for consistency. NFC llvm-svn: 244248	2015-08-06 19:10:45 +00:00
Hao Liu	b41c0b44af	[InterleavedAccess] Fix failures "undefined type 'llvm::raw_ostream'" on windows. llvm-svn: 240760	2015-06-26 04:38:21 +00:00
Hao Liu	1c1e0c9e71	[InterleavedAccess] Add a pass InterleavedAccess to identify interleaved memory accesses and transform into target specific intrinsics. E.g. An interleaved load (Factor = 2): %wide.vec = load <8 x i32>, <8 x i32>* %ptr %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6> %v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7> It can be transformed into a ld2 intrinsic in AArch64 backend or a vld2 intrinsic in ARM backend. E.g. An interleaved store (Factor = 3): %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11> store <12 x i32> %i.vec, <12 x i32>* %ptr It can be transformed into a st3 intrinsic in AArch64 backend or a vst3 intrinsic in ARM backend. Differential Revision: http://reviews.llvm.org/D10533 llvm-svn: 240751	2015-06-26 02:10:27 +00:00

Author

SHA1

Message

Date

Nico Rieck

78199518c4

Rename inst_range() to instructions() for consistency. NFC

llvm-svn: 244248

2015-08-06 19:10:45 +00:00

Hao Liu

b41c0b44af

[InterleavedAccess] Fix failures "undefined type 'llvm::raw_ostream'" on windows.

llvm-svn: 240760

2015-06-26 04:38:21 +00:00

Hao Liu

1c1e0c9e71

[InterleavedAccess] Add a pass InterleavedAccess to identify interleaved memory accesses and transform into target specific intrinsics.

E.g. An interleaved load (Factor = 2):
        %wide.vec = load <8 x i32>, <8 x i32>* %ptr
        %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6>
        %v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7>
It can be transformed into a ld2 intrinsic in AArch64 backend or a vld2 intrinsic in ARM backend.

E.g. An interleaved store (Factor = 3):
        %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
        store <12 x i32> %i.vec, <12 x i32>* %ptr
It can be transformed into a st3 intrinsic in AArch64 backend or a vst3 intrinsic in ARM backend.

Differential Revision: http://reviews.llvm.org/D10533

llvm-svn: 240751

2015-06-26 02:10:27 +00:00

3 Commits