Commit Graph

148869 Commits

Author SHA1 Message Date
Serge Guelton 1b421c259f Remove now useless trailing nullptr in StructType::get
llvm-svn: 302779
2017-05-11 08:46:02 +00:00
Diana Picus 657bfd3302 [ARM][GlobalISel] Support for G_ANYEXT
G_ANYEXT can be introduced by the legalizer when widening scalars. Add
support for it in the register bank info (same mapping as everything
else) and in the instruction selector.

When selecting it, we treat it as a COPY, just like G_TRUNC. On this
occasion we get rid of some assertions in selectCopy so we can reuse it.
This shouldn't be a problem at the moment since we're not supporting any
complicated cases (e.g. FPR, different register banks). We might want to
separate the paths when we do.

llvm-svn: 302778
2017-05-11 08:28:31 +00:00
Igor Breger c7b5977bb1 [GlobalISel][X86] G_ICMP support.
Summary: support G_ICMP for scalar types i8/i16/i64.

Reviewers: zvi, guyblank

Reviewed By: guyblank

Subscribers: rovka, kristof.beyls, llvm-commits, krytarowski

Differential Revision: https://reviews.llvm.org/D32995

llvm-svn: 302774
2017-05-11 07:17:40 +00:00
Craig Topper c59ced36aa [APInt] Remove an unneeded extra temporary APInt from toString.
Turns out udivrem can write its output to the same location as one of its inputs so the extra temporary isn't needed.

llvm-svn: 302772
2017-05-11 07:10:43 +00:00
Craig Topper b3c1f56737 [APInt] Use negate() instead of copying an APInt to negate it and then writing back over the original value.
llvm-svn: 302770
2017-05-11 07:02:04 +00:00
Craig Topper e3e1a35f68 [SCEV] Reduce possible APInt allocations a bit.
llvm-svn: 302769
2017-05-11 06:48:54 +00:00
Craig Topper 6694a4e6d6 [SCEV] Remove unneeded 'using namespace APIntOps'.
llvm-svn: 302768
2017-05-11 06:48:51 +00:00
Igor Breger db75455990 [X86] Move getX86ConditionCode() from X86FastISel.cpp to X86InstrInfo.cpp. NFC
Summary:
Move getX86ConditionCode() from X86FastISel.cpp to X86InstrInfo.cpp so it can be used by GloabalIsel instruction selector.
This is a pre-commit for a patch I'm working on to support G_ICMP. NFC.

Reviewers: zvi, guyblank, delena

Reviewed By: guyblank, delena

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33038

llvm-svn: 302767
2017-05-11 06:36:37 +00:00
NAKAMURA Takumi cf84800ea0 SupportTests: Suppress ParallelTests on mingw for now. Investigating.
llvm-svn: 302766
2017-05-11 06:35:51 +00:00
Paul Robinson a1f97d7c38 Remove redundant initialization. NFC
Post-commit review of r301940 by David Blaikie.

llvm-svn: 302756
2017-05-11 02:07:08 +00:00
Eric Fiselier a0c06c3365 Add temporary workaround to allow in-tree libc++ builds on Windows
llvm-svn: 302753
2017-05-11 01:44:30 +00:00
Zachary Turner 7a2d56813d Final (hopefully) fix for the build bots.
This time it actually occurred to me to change the #defines
to actually test the pre-processed out codepath.  Hopefully
this time it works.

llvm-svn: 302752
2017-05-11 00:22:18 +00:00
Zachary Turner 20c8e9192d Try again to fix the buildbots.
TaskGroup and Latch need to be in llvm::parallel::detail, not
in llvm::detail.

llvm-svn: 302751
2017-05-11 00:18:52 +00:00
Zachary Turner bfb8e189d2 Fix build errors with Parallel.
llvm-svn: 302749
2017-05-11 00:09:30 +00:00
Zachary Turner 3a57fbd6db [Support] Move Parallel algorithms from LLD to LLVM.
Differential Revision: https://reviews.llvm.org/D33024

llvm-svn: 302748
2017-05-11 00:03:52 +00:00
Kostya Serebryany ae0317e4a9 [libFuzzer] fix a compiler warning
llvm-svn: 302747
2017-05-10 23:59:03 +00:00
David L. Jones bbd97d273b Revert "[SDAG] Relax conditions under stores of loaded values can be merged"
This reverts r302712.

The change fails with ASAN enabled:

ERROR: AddressSanitizer: use-after-poison on address ... at ...
READ of size 2 at ... thread T0
  #0 ... in llvm::SDNode::getNumValues() const <snip>/include/llvm/CodeGen/SelectionDAGNodes.h:855:42
  #1 ... in llvm::SDNode::hasAnyUseOfValue(unsigned int) const <snip>/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:7270:3
  #2 ... in llvm::SDValue::use_empty() const <snip> include/llvm/CodeGen/SelectionDAGNodes.h:1042:17
  #3 ... in (anonymous namespace)::DAGCombiner::MergeConsecutiveStores(llvm::StoreSDNode*) <snip>/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:12944:7

Reviewers: niravd

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33081

llvm-svn: 302746
2017-05-10 23:56:21 +00:00
Eugene Zelenko ff9b0e2df2 [IR] Rollback changes in r302744 which caused buildbots failures.
llvm-svn: 302745
2017-05-10 23:53:40 +00:00
Eugene Zelenko eba7e4ec55 [IR] Fix some Clang-tidy modernize-use-using warnings; other minor fixes (NFC).
llvm-svn: 302744
2017-05-10 23:41:30 +00:00
Davide Italiano 1e8c59a8ac [PHIElimination] Use the same name for DEBUG_TYPE and pass name.
In an attempt to reduce the confusion.

llvm-svn: 302742
2017-05-10 23:13:26 +00:00
Sanjay Patel 40a87a909b [InstCombine] remove fold that swaps xor/or with constants; NFCI
// (X ^ C1) | C2 --> (X | C2) ^ (C1&~C2)

This canonicalization was added at:
https://reviews.llvm.org/rL7264 

By moving xors out/down, we can more easily combine constants. I'm adding
tests that do not change with this patch, so we can verify that those kinds
of transforms are still happening.

This is no-functional-change-intended because there's a later fold:
// (X^C)|Y -> (X|Y)^C iff Y&C == 0
...and demanded-bits appears to guarantee that any fold that would have
hit the fold we're removing here would be caught by that 2nd fold.

Similar reasoning was used in:
https://reviews.llvm.org/rL299384

The larger motivation for removing this code is that it could interfere with 
the fix for PR32706:
https://bugs.llvm.org/show_bug.cgi?id=32706

Ie, we're not checking if the 'xor' is actually a 'not', so we could reverse
a 'not' optimization and cause an infinite loop by altering an 'xor X, -1'. 

Differential Revision: https://reviews.llvm.org/D33050

llvm-svn: 302733
2017-05-10 21:33:55 +00:00
Matt Arsenault 3c5e4237c6 AMDGPU: Make some packed shuffles free
VOP3P instructions can encode access to either
half of the register.

llvm-svn: 302730
2017-05-10 21:29:33 +00:00
Matt Arsenault acdc7659cc AMDGPU: Add new subtarget features for gfx9 flat instructions
Flat instructions gain an immediate offset, and 2 new
sets of segment specific flat instructions are added.

llvm-svn: 302729
2017-05-10 21:19:05 +00:00
Craig Topper c51d05369a [ConstantRange] Fix the early out in ConstantRange::multiply for positive numbers to really do what the comment says
r271020 added an early out to skip the signed multiply portion of ConstantRange::multiply. The comment says we don't need to do signed multiply if the range is only positive numbers, but the implemented check only ensures that the start of the range is positive. It doesn't look at the end of the range.

This patch checks the end of the range instead. Because Upper is one more than the end we have to see if its positive or if its one past the last positive number.

llvm-svn: 302717
2017-05-10 20:01:48 +00:00
Craig Topper ef0114c4f0 [APInt] Add negate helper method to implement twos complement. Use it to shorten code.
llvm-svn: 302716
2017-05-10 20:01:38 +00:00
Davide Italiano dc435325a8 [NewGVN] Introduce a definesNoMemory() helper and use it.
This is nice as is, but it will be used in my next patch to
fix a bug. Suggested by Daniel Berlin.

llvm-svn: 302714
2017-05-10 19:57:43 +00:00
Nirav Dave a38c049fc5 [SDAG] Relax conditions under stores of loaded values can be merged
Summary:

Allow consecutive stores whose values come from consecutive loads to
merged in the presense of other uses of the loads. Previously this was
disallowed as in general the merged load cannot be shared with the
other uses. Merging N stores into 1 may cause as many as N redundant
loads. However in the context of caching this should have neglible
affect on memory pressure and reduce instruction count making it
almost always a win.

Fixes PR32086.

Reviewers: spatel, jyknight, andreadb, hfinkel, efriedma

Reviewed By: efriedma

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30471

llvm-svn: 302712
2017-05-10 19:53:41 +00:00
Teresa Johnson 94624aca2a Ensure non-null ProfileSummaryInfo passed to ModuleSummaryIndex builder
This fixes a ubsan bot failure after r302597, which made getProfileCount
non-static, but ended up invoking it on a null ProfileSummaryInfo object
in some cases from buildModuleSummaryIndex.

Most testing passed because the non-static getProfileCount currently
doesn't access any member variables, but I found this when testing a
follow on patch (D32877) that adds a member variable access.

llvm-svn: 302705
2017-05-10 18:52:16 +00:00
Craig Topper ecb97da108 [APInt] Make toString use udivrem instead of calling the divide helper method directly. Do a better job of reusing allocations while looping. NFCI
This lets toString take advantage of the degenerate case checks in udivrem and is just generally cleaner.

One minor downside of this is that the divisor APInt now needs to be the same size as Tmp which requires an additional allocation. But we were doing a poor job of reusing allocations before so the new code should still be an improvement.

llvm-svn: 302704
2017-05-10 18:15:24 +00:00
Craig Topper 6271bc7146 [APInt] Use uint32_t instead of unsigned for the storage type throughout the divide code. Use Lo_32/Hi_32/Make_64 helpers instead of casts and shifts. NFCI
llvm-svn: 302703
2017-05-10 18:15:20 +00:00
Craig Topper f86b9d5063 [APInt] Use getRawData to slightly simplify some code.
llvm-svn: 302702
2017-05-10 18:15:17 +00:00
Craig Topper 93eabae4aa [APInt] Remove check for single word since single word was handled earlier in the function. NFC
llvm-svn: 302701
2017-05-10 18:15:14 +00:00
Craig Topper 9bbae50d83 [ConstantRange] Add test case showing a case where we pick too large of a range for multiply after r271020.
llvm-svn: 302700
2017-05-10 18:15:06 +00:00
Amaury Sechet 197685c6d8 Small refactoring in DAGCombine. NFC
llvm-svn: 302699
2017-05-10 17:58:28 +00:00
Sanjay Patel 0b24b7ef72 [InstSimplify, InstCombine] move 'or' simplification tests; NFC
Surprisingly, I don't think these are redundant for InstSimplify. 
They were just misplaced as InstCombine tests.

llvm-svn: 302684
2017-05-10 15:57:47 +00:00
Simon Pilgrim 3fc619a49c [X86][SSE] Check vec_set BUILD_VECTOR tests on both 32 and 64-bit targets
llvm-svn: 302683
2017-05-10 15:52:59 +00:00
Quentin Colombet 307e29124c [AArch64][RegisterBankInfo] Change the default mapping of fp stores.
For stores, check if the stored value is defined by a floating point
instruction and if yes, we return a default mapping with FPR instead
of GPR.

llvm-svn: 302679
2017-05-10 15:19:41 +00:00
Amara Emerson 816542ceb3 [AArch64] Enable use of reduction intrinsics.
The new experimental reduction intrinsics can now be used, so I'm enabling this
for AArch64. We will need this for SVE anyway, so it makes sense to do this for
NEON reductions as well.

The existing code to match shufflevector patterns are replaced with a direct
lowering of the reductions to AArch64-specific nodes. Tests updated with the
new, simpler, representation.

Differential Revision: https://reviews.llvm.org/D32247

llvm-svn: 302678
2017-05-10 15:15:38 +00:00
Sanjay Patel 30a7157372 [InstCombine] remove redundant tests
The first test in this file is duplicated exactly in and.ll -> test33.
We have commuted and vector variants there too.

The second test is a composite of 2 folds. The first fold is tested
independently in add.ll -> flip_and_mask (including vector variant).
After that transform fires, the IR is identical to the first transform.

llvm-svn: 302676
2017-05-10 14:54:49 +00:00
Sanjay Patel beac508fc9 [InstCombine] fix auto-generated FileCheck-captured variable refs
The script at utils/update_test_checks.py has (had?) a bug when variables
start with the same sequence of letters (clearly, not all of the time).

llvm-svn: 302674
2017-05-10 14:40:04 +00:00
Sanjay Patel 3d8905f3a0 [InstCombine] fix typo in test comment; NFC
llvm-svn: 302669
2017-05-10 14:25:23 +00:00
Ulrich Weigand 93b369ed11 [SystemZ] Add miscellaneous instructions
This adds a few missing instructions for the assembler and
disassembler.  Those should be the last missing general-
purpose (Chapter 7) instructions for the z10 ISA.

llvm-svn: 302667
2017-05-10 14:20:15 +00:00
Ulrich Weigand d3604dc72c [SystemZ] Add missing arithmetic instructions
This adds the remaining general arithmetic instructions
for assembler / disassembler use.  Most of these are not
useful for codegen; a few might be, and those are listed
in the README.txt for future improvements.

llvm-svn: 302665
2017-05-10 14:18:47 +00:00
Sam Clegg c0d76649d4 [llvm-readobj] Improve errors on invalid binary
The previous code was discarding the error message from
createBinary() by calling errorToErrorCode().
This meant that such error were always reported unhelpfully
as "Invalid data was encountered while parsing the file".

Other tools such as llvm-objdump already produce a more
the error message in this case.

Differential Revision: https://reviews.llvm.org/D32985

llvm-svn: 302664
2017-05-10 14:18:11 +00:00
Michael Zuckerman ff29879f2e chang type from 'int' to 'size_t'. This will fix revision number 302652
llvm-svn: 302660
2017-05-10 14:00:57 +00:00
Sanjay Patel 2e069f250a [InstCombine] add (ashr (shl i32 X, 31), 31), 1 --> and (not X), 1
This is another step towards favoring 'not' ops over random 'xor' in IR:
https://bugs.llvm.org/show_bug.cgi?id=32706

This transformation may have occurred in longer IR sequences using computeKnownBits,
but that could be much more expensive to calculate.

As the scalar result shows, we do not currently favor 'not' in all cases. The 'not'
created by the transform is transformed again (unnecessarily). Vectors don't have
this problem because vectors are (wrongly) excluded from several other combines.

llvm-svn: 302659
2017-05-10 13:56:52 +00:00
Serge Guelton 778ece82ae Use explicit false instead of casted nullptr. NFC.
llvm-svn: 302656
2017-05-10 13:24:17 +00:00
Serge Guelton c9668165d6 Use clang++-3.5 compatible initializer_list constructor
Otherwise, a warning is issued.

llvm-svn: 302655
2017-05-10 13:23:47 +00:00
Michael Zuckerman 1f1a912c60 [LLVM][inline-asm] Altmacro string escape character '!'
This patch is the fourth patch in a series of reviews for the Altmacro feature. 
This patch introduces a new escape character '!' and it depends on D32701.

according to https://sourceware.org/binutils/docs/as/Altmacro.html:
"single-character string escape
To include any single character literally in a string (even if the character would otherwise have some special meaning), you can prefix the character with !' (an exclamation mark). For example, you can write <4.3 !> 5.4!!>' to get the literal text `4.3 > 5.4!'. "

Differential Revision: https://reviews.llvm.org/D32792

llvm-svn: 302652
2017-05-10 13:08:11 +00:00
Simon Pilgrim cd4d913336 [DAGCombiner] Dropped explicit (sra 0, x) -> 0 and (sra -1, x) -> 0 folds.
These are both handled (and tested) by the earlier ComputeNumSignBits == EltSizeInBits fold.

llvm-svn: 302651
2017-05-10 13:06:26 +00:00
Mikael Holmen 21c867c26e [IfConversion] Add missing check in IfConversion/canFallThroughTo
Summary:
When trying to figure out if MBB could fallthrough to ToMBB (possibly by
falling through a bunch of other MBBs) we didn't actually check if there
was fallthrough between the last two blocks in the chain.

Reviewers: kparzysz, iteratee, MatzeB

Reviewed By: kparzysz, iteratee

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D32996

llvm-svn: 302650
2017-05-10 13:06:13 +00:00
Jonas Paulsson 11d251c05c [SystemZ] Implement getRepRegClassFor()
This method must return a valid register class, or the list-ilp isel
scheduler will crash. For MVT::Untyped nullptr was previously returned, but
now ADDR128BitRegClass is returned instead. This is needed just as long as
list-ilp (and probably also list-hybrid) is still there.

Review: Ulrich Weigand, A Trick
https://reviews.llvm.org/D32802

llvm-svn: 302649
2017-05-10 13:03:25 +00:00
Dmitry Preobrazhensky da61a7f9ef [AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in disassembler output
See bug 32927: https://bugs.llvm.org//show_bug.cgi?id=32927

Reviewers: vpykhtin, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D32913

llvm-svn: 302648
2017-05-10 13:00:28 +00:00
Igor Breger 8e5e40862a [GlobalISel][X86] Split test file. NFC
llvm-svn: 302647
2017-05-10 12:58:31 +00:00
Ulrich Weigand c7eb5a95b2 [SystemZ] Add decimal integer instructions
This adds the set of decimal integer (BCD) instructions for
assembler / disassembler use.

llvm-svn: 302646
2017-05-10 12:42:45 +00:00
Ulrich Weigand 33a441adf9 [SystemZ] Add crypto instructions
This adds the set of message-security assist instructions for
assembler / disassembler use.

llvm-svn: 302645
2017-05-10 12:42:00 +00:00
Ulrich Weigand 435cd1a3e4 [SystemZ] Add translate/convert instructions
This adds the set of character-set translate and convert instructions
for assembler / disassembler use.

llvm-svn: 302644
2017-05-10 12:41:12 +00:00
Ulrich Weigand eb17909536 [SystemZ] Add missing memory/string instructions
This adds a number of missing memory and string instructions
for assembler / disassembler use.

llvm-svn: 302643
2017-05-10 12:40:15 +00:00
Ulrich Weigand 52461726dd [SystemZ] Reformat assembler/disassembler tests
The assembler and disassmebler test cases started out formatted and
sorted in a particular way, but this got lost over time as patches
were added.  Reformat them again.  NFC.

llvm-svn: 302642
2017-05-10 12:39:11 +00:00
Simon Pilgrim c29af824bf [DAGCombiner] Add vector support to fold (shl/srl 0, x) -> 0
llvm-svn: 302641
2017-05-10 12:34:27 +00:00
Chandler Carruth f3bd8ddedb Revert r301950: SpeculativeExecution: Stop using whitelist for costs
This pass doesn't correctly handle testing for when it is legal to hoist
arbitrary instructions. The whitelist happens to make it safe, so before
it is removed the pass's legality checks will need to be enhanced.

Details have been added to the code review thread for the patch.

llvm-svn: 302640
2017-05-10 12:30:07 +00:00
Martin Storsjo 605b0466ea [AArch64] Fix a comment to match the code. NFC.
For the ELF case, the default/preferred form is the generic one, not
the short one as used for Apple - fix the comment to say so. Currently
it is a copy-paste typo.

Make the comments on the darwin default a bit more verbose.

Use enum names instead of literal 0/1 to further increase readability
and reduce fragility.

Differential Revision: https://reviews.llvm.org/D32963

llvm-svn: 302634
2017-05-10 10:51:32 +00:00
Amara Emerson 836b0f48c1 Add a late IR expansion pass for the experimental reduction intrinsics.
This pass uses a new target hook to decide whether or not to expand a particular
intrinsic to the shuffevector sequence.

Differential Revision: https://reviews.llvm.org/D32245

llvm-svn: 302631
2017-05-10 09:42:49 +00:00
Craig Topper a584af5c8e [APInt] Fix indentation of tcDivide. Combine variable declaration and initialization.
llvm-svn: 302626
2017-05-10 07:50:17 +00:00
Craig Topper 62de039bd1 [APInt] Use getNumWords function in udiv/urem/udivrem instead of reimplementinging it.
llvm-svn: 302625
2017-05-10 07:50:15 +00:00
Igor Breger fda31e64e0 [GlobalISel][X86] G_ZEXT i1 to i32/i64 support.
Summary: Support G_ZEXT i1 to i32/i64 instruction selection.

Reviewers: zvi, guyblank

Reviewed By: guyblank

Subscribers: rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D32965

llvm-svn: 302623
2017-05-10 06:52:58 +00:00
Mikael Holmen af14a21e50 [UnreachableBlockElim] Check return value of constrainRegClass().
Summary:
MachineRegisterInfo::constrainRegClass() can fail if two register classes
don't have a common subclass or if the register class doesn't contain
enough registers. Check the return value before trying to remove Phi nodes,
and if we can't constrain, we output a COPY instead of simply replacing
registers.

Reviewers: kparzysz, david2050, wmi

Reviewed By: kparzysz

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32999

llvm-svn: 302622
2017-05-10 06:33:43 +00:00
Ahmed Bougacha a09ff59cc2 [CodeGen] Don't require AA in TwoAddress at -O0.
This is a follow-up to r302611, which moved an -O0 computation of DT
from SDAGISel to TwoAddress.

Don't use it here either, and avoid computing it completely.  The only
use was forwarding the analysis as an optional argument to utility
functions.

Differential Revision: https://reviews.llvm.org/D32766

llvm-svn: 302612
2017-05-10 00:56:00 +00:00
Ahmed Bougacha 604526fe87 [CodeGen] Don't require AA in SDAGISel at -O0.
Before r247167, the pass manager builder controlled which AA
implementations were used, exporting them all in the AliasAnalysis
analysis group.

Now, AAResultsWrapperPass always uses BasicAA, but still uses other AA
implementations if made available in the pass pipeline.

But regardless, SDAGISel is required at O0, and really doesn't need to
be doing fancy optimizations based on useful AA results.

Don't require AA at CodeGenOpt::None, and only use it otherwise.

This does have a functional impact (and one testcase is pessimized
because we can't reuse a load).  But I think that's desirable no matter
what.

Note that this alone doesn't result in less DT computations: TwoAddress
was previously able to reuse the DT we computed for SDAG.  That will be
fixed separately.

Differential Revision: https://reviews.llvm.org/D32766

llvm-svn: 302611
2017-05-10 00:39:30 +00:00
Ahmed Bougacha 8c358e3016 [CodeGen] Compute DT/LI lazily in SafeStackLegacyPass. NFC.
We currently require SCEV, which requires DT/LI.  Those are expensive to
compute, but the pass only runs for functions that have the safestack
attribute.

Compute DT/LI to build SCEV lazily, only when the pass is actually going
to transform the function.

Differential Revision: https://reviews.llvm.org/D31302

llvm-svn: 302610
2017-05-10 00:39:25 +00:00
Ahmed Bougacha 00d6822278 [CodeGen] Split SafeStack into a LegacyPass and a utility. NFC.
This lets the pass focus on gathering the required analyzes, and the
utility class focus on the transformation.

Differential Revision: https://reviews.llvm.org/D31303

llvm-svn: 302609
2017-05-10 00:39:22 +00:00
Ahmed Bougacha bcb79e6386 [CodeGen] Add an -O0 backend pipeline test. NFC.
This should hopefully makes changes to the O0 pipeline obvious; it's
easy to require expensive passes, and this helps make informed
decisions.

Case in point: in the few weeks separating the time when I initially
wrote this patch to the time when I committed, the test regressed as
r302103 added another use of DT!

llvm-svn: 302608
2017-05-10 00:39:17 +00:00
Sam Clegg 41db519ba6 [WebAssembly] Fix build error in wasm YAML code
This warning didn't show up on my local build
but is causing the bots to fail.  Seems like a
bad idea to have types and variables with the
same name anyhow.

Differential Revision: https://reviews.llvm.org/D33022

llvm-svn: 302606
2017-05-10 00:14:04 +00:00
Sanjay Patel 4133d4a56e [InstCombine] add helper function for add X, C folds; NFCI
llvm-svn: 302605
2017-05-10 00:07:16 +00:00
Sam Clegg 2ffff5af85 [WebAssembly] Improve libObject support for wasm imports and exports
Previously we had only supported the importing and
exporting of functions and globals.

Also, add usefull overload of getWasmSymbol() and
getNumberOfSymbols() in support of lld port.

Differential Revision: https://reviews.llvm.org/D33011

llvm-svn: 302601
2017-05-09 23:48:41 +00:00
Sanjay Patel a06384f3d8 [InstCombine] add tests for andn; NFC
llvm-svn: 302599
2017-05-09 23:40:13 +00:00
Easwaran Raman f5f9160072 [ProfileSummary] Make getProfileCount a non-static member function.
This change is required because the notion of count is different for
sample profiling and getProfileCount will need to determine the
underlying profile type.

Differential revision: https://reviews.llvm.org/D33012

llvm-svn: 302597
2017-05-09 23:21:10 +00:00
Peter Collingbourne c3d677f9d9 FunctionImport: Simplify function llvm::thinLTOInternalizeModule. NFCI.
llvm-svn: 302595
2017-05-09 22:43:31 +00:00
Lang Hames c936ac7f37 [ExecutionEngine] Make RuntimeDyld::MemoryManager responsible for tracking EH
frames.

RuntimeDyld was previously responsible for tracking allocated EH frames, but it
makes more sense to have the RuntimeDyld::MemoryManager track them (since the
frames are allocated through the memory manager, and written to memory owned by
the memory manager). This patch moves the frame tracking into
RTDyldMemoryManager, and changes the deregisterFrames method on
RuntimeDyld::MemoryManager from:

void deregisterEHFrames(uint8_t *Addr, uint64_t LoadAddr, size_t Size);

to:

void deregisterEHFrames();

Separating this responsibility will allow ORC to continue to throw the
RuntimeDyld instances away post-link (saving a few dozen bytes per lazy
function) while properly deregistering frames when modules are unloaded.

This patch also updates ORC to call deregisterEHFrames when modules are
unloaded. This fixes a bug where an exception that tears down the JIT can then
unwind through dangling EH frames that have been deallocated but not
deregistered, resulting in UB.

For people using SectionMemoryManager this should be pretty much a no-op. For
people with custom allocators that override registerEHFrames/deregisterEHFrames,
you will now be responsible for tracking allocated EH frames.

Reviewed in https://reviews.llvm.org/D32829

llvm-svn: 302589
2017-05-09 21:32:18 +00:00
Keno Fischer 06f962c1e8 [GVN] Fix a crash on encountering non-integral pointers
Summary:
This fixes the immediate crash caused by introducing an incorrect inttoptr
before attempting the conversion. There may still be a legality
check missing somewhere earlier for non-integral pointers, but this change
seems necessary in any case.

Reviewers: sanjoy, dberlin

Reviewed By: dberlin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32623

llvm-svn: 302587
2017-05-09 21:07:20 +00:00
Stanislav Mekhanoshin 7e3794d5c3 [AMDGPU] Fixed typo in GCNRegPressure, NFC
VGRP -> VGPR, SGRP -> SGPR

llvm-svn: 302586
2017-05-09 20:50:04 +00:00
Sanjay Patel 608cde04ab [InstCombine] update test file to use FileCheck; NFC
llvm-svn: 302585
2017-05-09 20:46:12 +00:00
Zvi Rackover b483e28c77 DAGCombine: Combine shuffles of splat-shuffles
Summary: Reapply r299047, but this time handle correctly splat-masks with undef elements.

Reviewers: spatel, RKSimon, eli.friedman, andreadb

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31961

llvm-svn: 302583
2017-05-09 20:25:38 +00:00
Matthew Simpson 78fd46b230 [AArch64] Consider widening instructions in cost calculations
The AArch64 instruction set has a few "widening" instructions (e.g., uaddl,
saddl, uaddw, etc.) that take one or more doubleword operands and produce
quadword results. The operands are automatically sign- or zero-extended as
appropriate. However, in LLVM IR, these extends are explicit. This patch
updates TTI to consider these widening instructions as single operations whose
cost is attached to the arithmetic instruction. It marks extends that are part
of a widening operation "free" and applies a sub-target specified overhead
(zero by default) to the arithmetic instructions.

Differential Revision: https://reviews.llvm.org/D32706

llvm-svn: 302582
2017-05-09 20:18:12 +00:00
Sanjay Patel 7caaa79879 [InstCombine] clean up matchDeMorgansLaws(); NFCI
The motivation for getting rid of dyn_castNotVal is to allow fixing:
https://bugs.llvm.org/show_bug.cgi?id=32706

So this was supposed to be functional-change-intended for the case
of inverting constants and applying DeMorgan. However, I can't find 
any cases where that pattern will actually get to matchDeMorgansLaws()
because we have other folds in visitAnd/visitOr that do the same
thing. So this ends up just being a clean-up patch with slight efficiency
improvement, but no-functional-change-intended.

llvm-svn: 302581
2017-05-09 20:05:05 +00:00
Davide Italiano b7a6698ae9 [NewGVN] Simplify a DEBUG() statement. NFCI.
llvm-svn: 302579
2017-05-09 20:02:48 +00:00
Reid Kleckner b5fced7324 [codeview] Check for a DIExpression offset for local variables
Fixes inalloca parameters, which previously all pointed to the same
offset. Extend the test to use llvm-readobj so that we can test the
offset in a readable way.

llvm-svn: 302578
2017-05-09 19:59:29 +00:00
Adrian Prantl c10d0e5ccd Make it illegal for two Functions to point to the same DISubprogram
As recently discussed on llvm-dev [1], this patch makes it illegal for
two Functions to point to the same DISubprogram and updates
FunctionCloner to also clone the debug info of a function to conform
to the new requirement. To simplify the implementation it also factors
out the creation of inlineAt locations from the Inliner into a
general-purpose utility in DILocation.

[1] http://lists.llvm.org/pipermail/llvm-dev/2017-May/112661.html
<rdar://problem/31926379>

Differential Revision: https://reviews.llvm.org/D32975

This reapplies r302469 with a fix for a bot failure (reparentDebugInfo
now checks for the case the orig and new function are identical).

llvm-svn: 302576
2017-05-09 19:47:37 +00:00
Piotr Padlewski d979c1f806 NFC: refactor replaceDominatedUsesWith
Summary:
Since I will post patch with some changes to
replaceDominatedUsesWith, it would be good to avoid
duplicating code again.

Reviewers: davide, dberlin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32798

llvm-svn: 302575
2017-05-09 19:39:44 +00:00
Wolfgang Pieb 15fa44698c [DWARF] Fix a parsing issue with type unit headers.
Reviewers: dblaikie

Differential Revision: https://reviews.llvm.org/D32987

llvm-svn: 302574
2017-05-09 19:38:38 +00:00
Eric Beckmann 674deed94e Fix the Endianness bug by adding the little endian UTF marker.
Summary: Quick fix

Reviewers: zturner, uweigand

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33014

llvm-svn: 302573
2017-05-09 19:35:45 +00:00
Serge Guelton e38003f839 Suppress all uses of LLVM_END_WITH_NULL. NFC.
Use variadic templates instead of relying on <cstdarg> + sentinel.
This enforces better type checking and makes code more readable.

Differential Revision: https://reviews.llvm.org/D32541

llvm-svn: 302571
2017-05-09 19:31:13 +00:00
Jacques Pienaar 0dbcc34f6b [lanai] Add computeKnownBitsForTargetNode for Lanai.
Summary: computeKnownBitsForTargetNode was not defined for Lanai which resulted in additional AND's with 0x1 for the output of SETCC instructions.

Reviewers: eliben, majnemer

Reviewed By: majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29605

llvm-svn: 302568
2017-05-09 18:35:26 +00:00
Davide Italiano 63998ec3c8 [NewGVN] Explain why sorting by pointer values doesn't introduce non-determinism.
Thanks to Eli for pointing out in a post-commit review comment.

llvm-svn: 302566
2017-05-09 18:29:37 +00:00
Ulrich Weigand d94e6d9ac1 [SystemZ] Support missing relocation types in RuntimeDyldELF
Handle some more relocation types in
RuntimeDyldELF::resolveSystemZRelocation

This fixes a number of failing LLDB test cases.

llvm-svn: 302565
2017-05-09 18:27:39 +00:00
Sam Clegg a0efcfe92b [WebAssembly] Fix validation of start function
The check for valid start function was inverted.  Added a new
test in test/Object to check this case and fixed the existing
tests in for ObjectYAML.

Differential Revision: https://reviews.llvm.org/D32986

llvm-svn: 302560
2017-05-09 17:51:38 +00:00
Krzysztof Parzyszek fd5a81594e [RegScavenger] Rangify a loop, NFC
llvm-svn: 302554
2017-05-09 17:16:52 +00:00
Puyan Lotfi a22c5a7bc8 Adding VSCode syntax colorizer to utils (generated from textmate colorizer).
--This line, and those below, will be igored--

A    utils/vscode
A    utils/vscode/README
A    utils/vscode/tablegen
A    utils/vscode/tablegen/.vscode
A    utils/vscode/tablegen/.vscode/launch.json
A    utils/vscode/tablegen/CHANGELOG.md
A    utils/vscode/tablegen/README.md
A    utils/vscode/tablegen/language-configuration.json
A    utils/vscode/tablegen/package.json
A    utils/vscode/tablegen/syntaxes
A    utils/vscode/tablegen/syntaxes/TableGen.tmLanguage
A    utils/vscode/tablegen/vsc-extension-quickstart.md

llvm-svn: 302553
2017-05-09 17:13:37 +00:00
Davide Italiano d6bb8cab03 [NewGVN] Fix a consistent order for phi nodes operands.
The way we currently define congruency for two PHIExpression(s) is:

1) The operands to the phi functions are congruent
2) The PHIs are defined in the same BasicBlock.

NewGVN works under the assumption that phi operands are in predecessor
order, or at least in some consistent order. OTOH, is valid IR:

patatino:
  %meh = phi i16 [ %0, %winky ], [ %conv1, %tinky ]
  %banana = phi i16 [ %0, %tinky ], [ %conv1, %winky ]
  br label %end

and the in-memory representations of the two SSA registers have an
inconsistent order. This violation of NewGVN assumptions results into
two PHIs found congruent when they're not. While we think it's useful
to have always a consistent order enforced, let's fix this in NewGVN
sorting uses in predecessor order before creating a PHI expression.

Differential Revision:  https://reviews.llvm.org/D32990

llvm-svn: 302552
2017-05-09 16:58:28 +00:00
Craig Topper 0acb6654d3 [APInt] Remove return value from tcFullMultiply.
The description says it returns the number of words needed to represent the results. But the way it was coded it always returns (lhsWords + rhsWords) or (lhsWords + rhsWords - 1). But the result could be even smaller than that and it wouldn't tell you.

No one uses the result today so rather than try to fix it, just remove it.

llvm-svn: 302551
2017-05-09 16:47:33 +00:00
Daniel Berlin 6604a2ffbb NewGVN: Make all of symbolic evaluation logically const.
llvm-svn: 302550
2017-05-09 16:40:04 +00:00
Craig Topper f893d49f0c [X86] Add more patterns for BZHI isel
This patch adds more patterns that a reasonable person might write that can be compiled to BZHI.

This adds support for

(~0U >> (32 - b)) & a;

and

a << (32 - b) >> (32 - b);

This was inspired by the code in APInt::clearUnusedBits.

This can pass an index of 32 to the bzhi instruction which a quick test of Haswell hardware shows will not mask any bits. Though the description text in the Intel manual says the "index is saturated to OperandSize-1". The pseudocode in the same manual indicates no bits will be zeroed for this case.

I think this is still missing cases where the subtract portion is an 8-bit operation.

Differential Revision: https://reviews.llvm.org/D32616

llvm-svn: 302549
2017-05-09 16:32:11 +00:00
Sanjay Patel 6844e21f59 [InstCombineCasts] Fix checks in sext->lshr->trunc pattern.
The comment says to avoid the case where zero bits are shifted into the truncated value, 
but the code checks that the shift is smaller than the truncated value instead of the 
number of bits added by the sign extension. Fixing this allows a shift by more than the 
value size to be introduced, which is undefined behavior, so the shift is capped at the 
value size minus one, which has the expected behavior of filling the value with the sign 
bit.

Patch by Jacob Young!

Differential Revision: https://reviews.llvm.org/D32285

llvm-svn: 302548
2017-05-09 16:24:59 +00:00
Guy Blank 0c42d8c35b VX512] Only look at lower bit in constant scalar masks
for scalar masked instructions only the lower bit of the mask is relevant. so for constant masks we should either do an unmasked operation or no operation, depending on the value of the lower bit.
This patch handles cases where the lower bit is '1'.

Differential Revision: https://reviews.llvm.org/D32805

llvm-svn: 302546
2017-05-09 16:16:48 +00:00
Reid Kleckner 3a363fff7e Re-land "Use the frame index side table for byval and inalloca arguments"
This re-lands r302483. It was not the cause of PR32977.

llvm-svn: 302544
2017-05-09 16:02:20 +00:00
Reid Kleckner 84075fddff Re-land "Don't add DBG_VALUE instructions for static allocas in dbg.declare"
This re-lands commit r302461. It was not the cause of PR32977.

llvm-svn: 302543
2017-05-09 16:01:47 +00:00
Tim Shen 04de70d3a7 [Atomic] Remove IsStore/IsLoad in the interface, and pass the instruction instead. NFC.
Now both emitLeadingFence and emitTrailingFence take the instruction
itself, instead of taking IsLoad/IsStore pairs.
Instruction::mayReadFromMemory and Instrucion::mayWriteToMemory are used
for determining those two booleans.

The instruction argument is also useful for later D32763, in
emitTrailingFence. For emitLeadingFence, it seems to have cleaner
interface with the proposed change.

Differential Revision: https://reviews.llvm.org/D32762

llvm-svn: 302539
2017-05-09 15:27:17 +00:00
Aaron Ballman 3234647df6 Amend r302535; ifndef and ifdef are different, as it turns out.
llvm-svn: 302537
2017-05-09 15:12:03 +00:00
Aaron Ballman 06297e839a ARMRegisterBankInfo.h requires LLVM_BUILD_GLOBAL_ISEL to be defined. If it is not defined, then ARMGenRegisterBank.inc is not table generated and the inclusion of this header causes the build to fail.
llvm-svn: 302535
2017-05-09 14:59:48 +00:00
Hans Wennborg 66fb0d9768 Revert r302469 "Make it illegal for two Functions to point to the same DISubprogram"
This caused PR32977.

Original commit message:

> Make it illegal for two Functions to point to the same DISubprogram
>
> As recently discussed on llvm-dev [1], this patch makes it illegal for
> two Functions to point to the same DISubprogram and updates
> FunctionCloner to also clone the debug info of a function to conform
> to the new requirement. To simplify the implementation it also factors
> out the creation of inlineAt locations from the Inliner into a
> general-purpose utility in DILocation.
>
> [1] http://lists.llvm.org/pipermail/llvm-dev/2017-May/112661.html
> <rdar://problem/31926379>
>
> Differential Revision: https://reviews.llvm.org/D32975

llvm-svn: 302533
2017-05-09 14:44:15 +00:00
Anna Thomas 0691483435 [LV] Fix insertion point for shuffle vectors in first order recurrence
Summary:
In first order recurrence vectorization, when the previous value is a phi node, we need to
set the insertion point to the first non-phi node.
We can have the previous value being a phi node, due to the generation of new
IVs as part of trunc optimization [1].

[1] https://reviews.llvm.org/rL294967

Reviewers: mssimpso, mkuper

Subscribers: mzolotukhin, llvm-commits

Differential Revision: https://reviews.llvm.org/D32969

llvm-svn: 302532
2017-05-09 14:29:33 +00:00
Aaron Ballman f22f885b66 Removing a file that is not necessary (and was causing link diagnostics with MSVC 2015); NFC.
llvm-svn: 302531
2017-05-09 14:22:48 +00:00
Guy Blank 31b37297de [X86][AVX512] Refine some avx512er intrinsics tests. NFC.
The modified tests should test the masked intrinsics.
Currently the mask is constant, which with a future patch (https://reviews.llvm.org/D32805) will cause the intrinsics to be replaced with an unmasked version.
This patch changes the constant mask to be a variable one.

llvm-svn: 302529
2017-05-09 14:03:51 +00:00
Serge Pavlov d526b13e61 Add extra operand to CALLSEQ_START to keep frame part set up previously
Using arguments with attribute inalloca creates problems for verification
of machine representation. This attribute instructs the backend that the
argument is prepared in stack prior to  CALLSEQ_START..CALLSEQ_END
sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size
stored in CALLSEQ_START in this case does not count the size of this
argument. However CALLSEQ_END still keeps total frame size, as caller can
be responsible for cleanup of entire frame. So CALLSEQ_START and
CALLSEQ_END keep different frame size and the difference is treated by
MachineVerifier as stack error. Currently there is no way to distinguish
this case from actual errors.

This patch adds additional argument to CALLSEQ_START and its
target-specific counterparts to keep size of stack that is set up prior to
the call frame sequence. This argument allows MachineVerifier to calculate
actual frame size associated with frame setup instruction and correctly
process the case of inalloca arguments.

The changes made by the patch are:
- Frame setup instructions get the second mandatory argument. It
  affects all targets that use frame pseudo instructions and touched many
  files although the changes are uniform.
- Access to frame properties are implemented using special instructions
  rather than calls getOperand(N).getImm(). For X86 and ARM such
  replacement was made previously.
- Changes that reflect appearance of additional argument of frame setup
  instruction. These involve proper instruction initialization and
  methods that access instruction arguments.
- MachineVerifier retrieves frame size using method, which reports sum of
  frame parts initialized inside frame instruction pair and outside it.

The patch implements approach proposed by Quentin Colombet in
https://bugs.llvm.org/show_bug.cgi?id=27481#c1.
It fixes 9 tests failed with machine verifier enabled and listed
in PR27481.

Differential Revision: https://reviews.llvm.org/D32394

llvm-svn: 302527
2017-05-09 13:35:13 +00:00
Simon Dardis 659c43f11a Revert "[MIPS] Add support to match more patterns for DINS instruction"
This reverts commit rL302512. This broke the mips buildbots.

llvm-svn: 302526
2017-05-09 13:18:48 +00:00
Simon Pilgrim ca3a63a849 [X86][SSE42] Lower v2i64/v4i64 ASHR(X, 63) as PCMPGTQ(0, X)
Similar to what we do for vXi8 ASHR(X, 7), use SSE42's PCMPGTQ to splat the sign instead of using the PSRAD+PSHUFD.

Avoiding bitcasts this improves combines that utilize computeNumSignBits, permits memory folding and reduces pipe pressure. Although it does require a second register, given that this is a (cheap) zero register the impact is minimal.

Differential Revision: https://reviews.llvm.org/D32973

llvm-svn: 302525
2017-05-09 13:14:40 +00:00
Diana Picus e8da53f4e0 Revert "[Dwarf] Disable reference verification for now (PR32972)"
This reverts commit r302520 because it break the unit tests.

llvm-svn: 302524
2017-05-09 13:05:43 +00:00
Renato Golin 94d6c8fb36 [Dwarf] Disable reference verification for now (PR32972)
There is no other explanation about why this only started happening
now, even though it crashes on old code (supposedly reachable from
here).

The only common factor between the failing bots is that they use GCC
(4.9 and 5.3) to compile Clang, while the others use Clang 3.8, but the
failure is while building the tests, as an assertion, on Clang.

Commenting it out for now in hope the bots will go back green, but we
should keep looking for the real cause, and update bugzilla.

llvm-svn: 302520
2017-05-09 12:36:50 +00:00
Guy Blank 5995802911 [X86][AVX512] Add test for masking of scalar instructions.
llvm-svn: 302519
2017-05-09 12:32:48 +00:00
Amara Emerson cf9daa33a7 Introduce experimental generic intrinsics for horizontal vector reductions.
- This change allows targets to opt-in to using them instead of the log2
  shufflevector algorithm.
- The SLP and Loop vectorizers have the common code to do shuffle reductions
  factored out into LoopUtils, and now have a unified interface for generating
  reductions regardless of the preference of the target. LoopUtils now uses TTI
  to determine what kind of reductions the target wants to handle.
- For CodeGen, basic legalization support is added.

Differential Revision: https://reviews.llvm.org/D30086

llvm-svn: 302514
2017-05-09 10:43:25 +00:00
Nikolai Bozhenov b7bf386e80 [X86] Clang option -fuse-init-array has no effect when generating for MCU target
Reviewers: Eugene.Zelenko, dschuff, craig.topper

Reviewed By: craig.topper

Subscribers: ahatanak, aaboud, DavidKreitzer, llvm-commits, cfe-commits

Differential Revision: https://reviews.llvm.org/D32543
Patch by AndreiGrischenko <andrei.l.grischenko@intel.com>

llvm-svn: 302513
2017-05-09 10:14:03 +00:00
Strahinja Petrovic 27ae4c3259 [MIPS] Add support to match more patterns for DINS instruction
This patch adds support for recognizing patterns to match
DINS instruction.

Differential Revision: https://reviews.llvm.org/D31465

llvm-svn: 302512
2017-05-09 10:02:00 +00:00
Diana Picus 95640a1c4d [ARM GlobalISel] Remove hand-written G_FADD selection
Remove the code selecting G_FADD - now that TableGen can handle more
opcodes, it's not needed anymore.

llvm-svn: 302511
2017-05-09 08:32:42 +00:00
Craig Topper ef02803bed [ConstantRange] Rewrite shl to avoid repeated calls to getUnsignedMax and avoid creating the min APInt until we're sure we need it. Use inplace shift operations.
llvm-svn: 302510
2017-05-09 07:04:04 +00:00
Craig Topper 79b7666f02 [ConstantRange] Combine the two adds max+1 in lshr into a single addition.
llvm-svn: 302509
2017-05-09 07:04:02 +00:00
Craig Topper 61729fd036 [ConstantRange] Use APInt::isNullValue in place of comparing with 0. The compiler should be able to generate slightly better code for the former. NFC
llvm-svn: 302508
2017-05-09 05:01:29 +00:00
Reid Kleckner 41bb94233b Revert "Don't add DBG_VALUE instructions for static allocas in dbg.declare"
This reverts commit r302461.

It appears to be causing failures compiling gtest with debug info on the
Linux sanitizer bot. I was unable to reproduce the failure locally,
however.

llvm-svn: 302504
2017-05-09 01:57:44 +00:00
Teresa Johnson 720d9b4111 Fix code section prefix for proper layout
Summary:
r284533 added hot and cold section prefixes based on profile
information, to enable grouping of hot/cold functions at link time.
However, it used "cold" as the prefix for cold sections, but gold only
recognizes "unlikely" (which is used by gcc for cold sections).
Therefore, cold sections were not properly being grouped. Switch to
using "unlikely"

Reviewers: danielcdh, davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32983

llvm-svn: 302502
2017-05-09 01:43:24 +00:00
Tom Stellard ea139eccc1 Revert "Revert "CMake: Move sphinx detection into AddSphinxTarget.cmake""
This reverts commit r302054.

Re-commit now that I have fixes for clang/lld.

llvm-svn: 302499
2017-05-09 01:41:28 +00:00
Kostya Serebryany b068087bd8 [libFuzzer] update docs on -print_coverage/-dump_coverage
llvm-svn: 302498
2017-05-09 01:34:27 +00:00
Kostya Serebryany fe4ed9bd85 [libFuzzer] make sure the input data is not overwritten in the fuzz target (if it is -- report an error)
llvm-svn: 302494
2017-05-09 01:17:29 +00:00
Reid Kleckner 9f29914d40 Revert "Use the frame index side table for byval and inalloca arguments"
This reverts r302483 and it's follow up fix.

llvm-svn: 302493
2017-05-09 01:14:39 +00:00
Craig Topper 3369f8cc4a [APInt] Use default constructor instead of explicitly creating a 1-bit APInt in udiv and urem. NFC
The default constructor does the same thing.

llvm-svn: 302487
2017-05-08 23:49:54 +00:00
Craig Topper 24ae69515b [APInt] Remove 'else' after 'return' in udiv and urem. NFC
llvm-svn: 302486
2017-05-08 23:49:49 +00:00
Evgeniy Stepanov f7e8acf0fc Ignore !associated metadata with null argument.
Fixes PR32577 (comment 10).
Such metadata may legitimately appear in LTO.

llvm-svn: 302485
2017-05-08 23:46:20 +00:00
Reid Kleckner 918e8157d8 Relax Dwarf filecheck test for 32-bit hosts
llvm-svn: 302484
2017-05-08 23:27:52 +00:00
Reid Kleckner 45efcf0c96 Use the frame index side table for byval and inalloca arguments
Summary:
For inalloca functions, this is a very common code pattern:

  %argpack = type <{ i32, i32, i32 }>
  define void @f(%argpack* inalloca %args) {
  entry:
    %a = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 0
    %b = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 1
    %c = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 2
    tail call void @llvm.dbg.declare(metadata i32* %a, ... "a")
    tail call void @llvm.dbg.declare(metadata i32* %c, ... "b")
    tail call void @llvm.dbg.declare(metadata i32* %b, ... "c")

Even though these GEPs can be simplified to a constant offset from EBP
or RSP, we don't do that at -O0, and each GEP is computed into a
register. Registers used to compute argument addresses are typically
spilled and clobbered very quickly after the initial computation, so
live debug variable tracking loses information very quickly if we use
DBG_VALUE instructions.

This change moves processing of dbg.declare between argument lowering
and basic block isel, so that we can ask if an argument has a frame
index or not. If the argument lives in a register as is the case for
byval arguments on some targets, then we don't put it in the side table
and during ISel we emit DBG_VALUE instructions.

Reviewers: aprantl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32980

llvm-svn: 302483
2017-05-08 23:20:27 +00:00
Sanjoy Das 9c52c7656c Add basic test case for -instnamer
llvm-svn: 302482
2017-05-08 23:18:46 +00:00
Sanjoy Das 76bbdd1a16 [InstNamer] Use range-for
llvm-svn: 302481
2017-05-08 23:18:43 +00:00
Sanjoy Das 0ac3bf1cc8 [InstNamer] Don't check type of arguments (they're never void)
llvm-svn: 302480
2017-05-08 23:18:39 +00:00
Sanjoy Das 7be961b081 Delete trailing whitespace
llvm-svn: 302479
2017-05-08 23:18:36 +00:00
Sanjay Patel 2a895ce134 [InstCombine] add tests from D32285 to show current problems; NFC
llvm-svn: 302475
2017-05-08 22:33:20 +00:00
Greg Clayton 58a2e0d90b Add const to "DWARFDie &Die" in a few functions as they can't change the DWARFDie.
llvm-svn: 302471
2017-05-08 21:29:17 +00:00
Eugene Zemtsov 3b52dbd934 Fix typo
llvm-svn: 302470
2017-05-08 21:20:53 +00:00
Adrian Prantl 200a5ef526 Make it illegal for two Functions to point to the same DISubprogram
As recently discussed on llvm-dev [1], this patch makes it illegal for
two Functions to point to the same DISubprogram and updates
FunctionCloner to also clone the debug info of a function to conform
to the new requirement. To simplify the implementation it also factors
out the creation of inlineAt locations from the Inliner into a
general-purpose utility in DILocation.

[1] http://lists.llvm.org/pipermail/llvm-dev/2017-May/112661.html
<rdar://problem/31926379>

Differential Revision: https://reviews.llvm.org/D32975

llvm-svn: 302469
2017-05-08 21:17:08 +00:00
Matthias Braun d0c4676f39 STLExtras: Fix enumerate() documentation
llvm-svn: 302467
2017-05-08 21:10:58 +00:00
Greg Clayton 5404f114d3 Fix typo "veify" to "verify".
llvm-svn: 302466
2017-05-08 20:53:00 +00:00
Sanjay Patel a1c8814891 [InstCombine] add folds for not-of-shift-right
This is another step towards getting rid of dyn_castNotVal, 
so we can recommit:
https://reviews.llvm.org/rL300977

As the tests show, we were missing the lshr case for constants
and both ashr/lshr vector splat folds. The ashr case with constant
was being performed inefficiently in 2 steps. It's also possible
there was a latent bug in that case because we can't do that fold
if the constant is positive:
http://rise4fun.com/Alive/Bge

llvm-svn: 302465
2017-05-08 20:49:59 +00:00
Davide Italiano aa42a10051 [PartialInlining] Capture by reference rather than by value.
llvm-svn: 302464
2017-05-08 20:44:01 +00:00
Tim Northover c48c993b75 ARM: use divmod libcalls on embedded MachO platforms too.
The separated libcalls are implemented in terms of __divmodsi4 and __udivmodsi4
anyway, so we should always use them if possible.

llvm-svn: 302462
2017-05-08 20:00:14 +00:00