Commit Graph

148869 Commits

Author SHA1 Message Date
Simon Pilgrim ded23a7fb1 [X86][SSE] Test showing inability of ComputeNumSignBits to resolve shuffles
llvm-svn: 302992
2017-05-13 17:41:07 +00:00
Craig Topper 9fe357971c [ValueTracking] Remove const_casts on several calls to computeKnownBits and ComputeSignBit. NFC
llvm-svn: 302991
2017-05-13 17:22:16 +00:00
Justin Bogner 3a3e115e81 MSan: Mark MemorySanitizer tests that use x86 intrinsics as REQUIRES: x86
Tests that use target intrinsics are inherently target specific. Mark
them as such.

llvm-svn: 302990
2017-05-13 16:24:38 +00:00
Simon Pilgrim ef46c2762a [x86, SSE] AVX1 PR28129 (256-bit all-ones rematerialization)
Further perf tests on Jaguar indicate that:

vxorps  %ymm0, %ymm0, %ymm0
vcmpps  $15, %ymm0, %ymm0, %ymm0

is consistently faster (by about 9%) than:

vpcmpeqd  %xmm0, %xmm0, %xmm0
vinsertf128  $1, %xmm0, %ymm0, %ymm0

Testing equivalent code on a SandyBridge (E5-2640) puts it slightly (~3%) faster as well.

Committed on behalf of @dtemirbulatov

Differential Revision: https://reviews.llvm.org/D32416

llvm-svn: 302989
2017-05-13 13:42:35 +00:00
Simon Pilgrim 7d62e4b455 [LoopOptimizer][Fix]PR32859, PR24738
The Loop vectorizer pass introduced undef value while it is fixing output of LCSSA form.
Here it is:

before: %e.0.ph = phi i32 [ 0, %for.inc.2.i ]
after: %e.0.ph = phi i32 [ 0, %for.inc.2.i ], [ undef, %middle.block ]

and after this change we have:

%e.0.ph = phi i32 [ 0, %for.inc.2.i ]
%e.0.ph = phi i32 [ 0, %for.inc.2.i ], [ 0, %middle.block ]

Committed on behalf of @dtemirbulatov

Differential Revision: https://reviews.llvm.org/D33055

llvm-svn: 302988
2017-05-13 13:25:57 +00:00
Vivek Pandya 1d12790f37 This reverts r302984
llvm-svn: 302985
2017-05-13 10:59:05 +00:00
Vivek Pandya d20de87fd5 Simplify MIR Output used for Codegen Testing
- MIRYamlMapping: Default value provided for fields which have optional
mappings. Implemented == operators for required classes. When a field's value is
same as default value specified YAML IO class will not print it.

- MIRPrinter: Above mentioned behaviour is not on by default. If -simplify-mir
option not specified, then make yaml::Output to print fields with default values
too.

Differential Revision: https://reviews.llvm.org/D32304

llvm-svn: 302984
2017-05-13 08:55:43 +00:00
Craig Topper 2c9a70661c [APInt] Use Lo_32/Hi_32/Make_64 in a few more places in the divide code. NFCI
llvm-svn: 302983
2017-05-13 07:14:17 +00:00
Craig Topper 935f7b050f [InstCombine] Prevent InstCombine from triggering an extra iteration if something changed in the initial Worklist creation
Summary:
If the Worklist build causes an IR change this change flag currently factors into the flag for running another iteration of the iteration loop. But only changes during processing should trigger another loop.

This patch captures the worklist creation change flag into the outside the loop flag currently used for DbgDeclares and only sends that flag up to the caller. Rerunning the loop only depends on IC.run() now.

This uses the debug output of InstCombine to determine if one or two iterations run. I couldn't think of a better way to detect it since the second spurious iteration shoudn't make any visible changes. Just wasted computation.

I can do a pre-commit of the test case with the CHECK-NOT as a CHECK if this is an ok way to check this.

This is a subset of D31678 as I'm still not sure how to verify the analysis behavior for that.

Reviewers: davide, majnemer, spatel, chandlerc

Reviewed By: davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32453

llvm-svn: 302982
2017-05-13 06:56:04 +00:00
Justin Bogner d2a10ad761 ConstProp: Split x86 SSE intrinsic tests out of calls.ll
This allows us to mark this as `REQUIRES: x86`, since it uses x86
target specific intrinsics.

llvm-svn: 302980
2017-05-13 05:52:17 +00:00
Justin Bogner 3c6fbad388 InstCombine: Move tests that use target intrinsics into subdirectories
Tests with target intrinsics are inherently target specific, so it
doesn't actually make sense to run them if we've excluded their
target.

llvm-svn: 302979
2017-05-13 05:39:46 +00:00
NAKAMURA Takumi 5057086a35 Disable llvm/test/Transforms/NewGVN/pr32934.ll while Davide is investigating.
llvm-svn: 302977
2017-05-13 03:05:38 +00:00
Davide Italiano d580dcd4da [NewGVN] XFAIL a flaky test until I find out what's going on.
I bet the change is correct but this test seems to expose some underlying
problem that manifest only on some buildbots, and I'm not able to reproduce
locally. Unfortunately I can't debug right now but I don't want to annoy
people with spurious failures, so I'll XFAIL until I can take a look (over
the weekend).

llvm-svn: 302976
2017-05-13 02:45:47 +00:00
Craig Topper 4b83b4d560 [APInt] Fix typo in comment. NFC
llvm-svn: 302974
2017-05-13 00:35:30 +00:00
Dylan McKay 0c4debc123 [AVR] When lowering Select8/Select16, put newly generated MBBs in the same spot
Contributed by Dr. Gergő Érdi.

Fixes a bug.

Raised from (https://github.com/avr-rust/rust/issues/49).

llvm-svn: 302973
2017-05-13 00:22:34 +00:00
Justin Bogner b713266331 AA: Use generic intrinsics for tests instead of target specific ones
Update a few tests to use llvm.masked.load/store instead of arm neon
vector loads and stores, and move the tests that are actually specific
to those arm intrinsics to their own files. This lets us mark the
tests that use target specific intrinsics as requiring those targets.

llvm-svn: 302972
2017-05-13 00:12:52 +00:00
Justin Bogner bce6d327be [CodeView] Silence some -Wsign-compare warnings
llvm-svn: 302971
2017-05-13 00:11:39 +00:00
Dylan McKay 0c707da6ac [AVR] Remove an unused variable
llvm-svn: 302970
2017-05-13 00:00:26 +00:00
Xinliang David Li 66bdfca77a [PartialInlining] Profile based cost analysis
Implemented frequency based cost/saving analysis
and related options.

The pass is now in a state ready to be turne on
in the pipeline (in follow up).

Differential Revision: http://reviews.llvm.org/D32783

llvm-svn: 302967
2017-05-12 23:41:43 +00:00
Aditya Nandakumar 2a735421d1 [GISel]: Add a getConstantFPVRegVal utility
This might be useful across various GISel Passes

https://reviews.llvm.org/D33051

llvm-svn: 302964
2017-05-12 22:54:52 +00:00
Aditya Nandakumar 479ddd20fc [GISel]: Fix undefined behavior while accessing DefaultAction map
We end up dereferencing the end iterator here when the Aspect doesn't exist in the DefaultAction map.
Change the API to return Optional<LLT> and return None when not found.
Also update the callers to handle the None case

llvm-svn: 302963
2017-05-12 22:43:58 +00:00
Eugene Zelenko 0cd7948876 [IR] Fix some Clang-tidy modernize-use-using warnings; other minor fixes (NFC).
llvm-svn: 302961
2017-05-12 22:25:07 +00:00
Andrew Kaylor b01e94ee8d [TLI] Add mapping for various '__<func>_finite' forms of the math routines to SVML routines
Patch by Chris Chrulski

Differential Revision: https://reviews.llvm.org/D31789

llvm-svn: 302957
2017-05-12 22:11:26 +00:00
Andrew Kaylor f7c864f89c [ConstantFolding] Add folding for various math '__<func>_finite' routines generated from -ffast-math
Patch by Chris Chrulski

Differential Revision: https://reviews.llvm.org/D31788

llvm-svn: 302956
2017-05-12 22:11:20 +00:00
Andrew Kaylor 3cd8c16d7f [TLI] Add declarations for various math header file routines from math-finite.h that create '__<func>_finite as functions
Patch by Chris Chrulski

Differential Revision: https://reviews.llvm.org/D31787

llvm-svn: 302955
2017-05-12 22:11:12 +00:00
Craig Topper b1a71cac4b [APInt] Add early outs for a division by 1 to udiv/urem/udivrem
We already counted the number of bits in the RHS so its pretty cheap to just check if the RHS is 1.

Differential Revision: https://reviews.llvm.org/D33154

llvm-svn: 302953
2017-05-12 21:45:50 +00:00
Craig Topper 2579c7c69f [APInt] In udivrem, remember the bit width in a local variable so we don't reread it from the LHS which might be aliased with Quotient or Remainder.
This helped the compiler generate better code for the single word case. It was able to remember that the bit width was still a single word when it created the Remainder APInt and not create code for it possibly being multiword.

llvm-svn: 302952
2017-05-12 21:45:44 +00:00
Adrian Prantl 1fa362f811 LTO: Don't verify modules twice in verifyMergedModuleOnce
Differential Revision: https://reviews.llvm.org/D33140

llvm-svn: 302951
2017-05-12 21:38:32 +00:00
Sanjay Patel 2413af2174 [Doc] Document "Splat" in the lexicon
Patch by Wei-Ren Chen (陳韋任)!

Differential Revision: https://reviews.llvm.org/D32964

llvm-svn: 302950
2017-05-12 21:30:31 +00:00
Sanjay Patel 1b8589407b [x86] add vector tests for demanded bits; NFC
llvm-svn: 302949
2017-05-12 20:53:48 +00:00
Changpeng Fang 161e8c39af AMDGPU/SI: Don't promote to vector if the load/store is volatile.
Summary:
  We should not change volatile loads/stores in promoting alloca to vector.

Reviewers:
  arsenm

Differential Revision:
  http://reviews.llvm.org/D33107

llvm-svn: 302943
2017-05-12 20:31:12 +00:00
Simon Pilgrim a1978aaefd [NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
This fixes 47 of the 75 NVPTX '-verify-machineinstrs with EXPENSIVE_CHECKS' errors in PR32146.

Differential Revision: https://reviews.llvm.org/D33147

llvm-svn: 302942
2017-05-12 19:56:43 +00:00
Teresa Johnson 4cd12ce9a0 Remove ignore-empty-index-file option
Summary:
As discussed in the D32195 review thread and on IRC, remove this option
and replace with parameter, which will be set to true when invoked
from clang in the context of a ThinLTO distributed backend.

Reviewers: pcc

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D33133

llvm-svn: 302939
2017-05-12 19:32:11 +00:00
Dehao Chen 65dd23e273 Add LiveRangeShrink pass to shrink live range within BB.
Summary: LiveRangeShrink pass moves instruction right after the definition with the same BB if the instruction and its operands all have more than one use. This pass is inexpensive and guarantees optimal live-range within BB.

Reviewers: davidxl, wmi, hfinkel, MatzeB, andreadb

Reviewed By: MatzeB, andreadb

Subscribers: hiraditya, jyknight, sanjoy, skatkov, gberry, jholewinski, qcolombet, javed.absar, krytarowski, atrick, spatel, RKSimon, andreadb, MatzeB, mehdi_amini, mgorny, efriedma, davide, dberlin, llvm-commits

Differential Revision: https://reviews.llvm.org/D32563

llvm-svn: 302938
2017-05-12 19:29:27 +00:00
Tim Shen 10c64e6aea [PPC] Move the combine "a << (b % (sizeof(a) * 8)) -> (PPCshl a, b)" to the backend. NFC.
Summary:
Eli pointed out that it's unsafe to combine the shifts to ISD::SHL etc.,
because those are not defined for b > sizeof(a) * 8, even after some of
the combiners run.

However, PPCISD::SHL defines that behavior (as the instructions themselves).
Move the combination to the backend.

The tests in shift_mask.ll still pass.

Reviewers: echristo, hfinkel, efriedma, iteratee

Subscribers: nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D33076

llvm-svn: 302937
2017-05-12 19:25:37 +00:00
Zachary Turner dd3a739d52 [CodeView] Add a random access type visitor.
This adds a visitor that is capable of accessing type
records randomly and caching intermediate results that it
learns about during partial linear scans.  This yields
amortized O(1) access to a type stream even though type
streams cannot normally be indexed.

Differential Revision: https://reviews.llvm.org/D33009

llvm-svn: 302936
2017-05-12 19:18:12 +00:00
Geoff Berry ddbbf6416c [AArch64][Falkor] Refine modeling of multiply accumulate forwarding.
llvm-svn: 302933
2017-05-12 18:57:10 +00:00
Craig Topper 4bdd621e93 [APInt] Add an assert to check for divide by zero in udivrem. NFC
udiv and urem already had the same assert.

llvm-svn: 302931
2017-05-12 18:19:01 +00:00
Craig Topper 06da0816fd [APInt] Remove unnecessary checks of rhsWords==1 with lhsWords==1 from udiv and udivrem. NFC
At this point in the code rhsWords is guaranteed to be non-zero and less than or equal to lhsWords. So if lhsWords is 1, rhsWords must also be 1. urem alread had the check removed so this makes all 3 consistent.

llvm-svn: 302930
2017-05-12 18:18:57 +00:00
Tom Stellard fab6b1af6e AMDGPU: Add lit.local.cfg to disable global-isel tests when global-isel is disabled
This should fix bots broken by r302919.

llvm-svn: 302928
2017-05-12 17:59:30 +00:00
Simon Pilgrim b146e61828 Strip trailing whitespace. NFCI.
llvm-svn: 302927
2017-05-12 17:42:36 +00:00
Craig Topper 8df66c602a [KnownBits] Add bit counting methods to KnownBits struct and use them where possible
This patch adds min/max population count, leading/trailing zero/one bit counting methods.

The min methods return answers based on bits that are known without considering unknown bits. The max methods give answers taking into account the largest count that unknown bits could give.

Differential Revision: https://reviews.llvm.org/D32931

llvm-svn: 302925
2017-05-12 17:20:30 +00:00
Reid Kleckner 5bc8543a36 [codeview] Fix assertion failure introduced in r295354 refactoring
CodeViewDebug sets Asm to nullptr to disable debug info generation.  You
can get a .ll file like no-cus.ll from 'clang -gcodeview -g0', which
happens in the ubsan test suite.

llvm-svn: 302923
2017-05-12 17:02:40 +00:00
Galina Kistanova 4f5771d71b Make sure we have actually written what is expected by the test.
llvm-svn: 302922
2017-05-12 17:00:13 +00:00
Tom Stellard a0d67c748a AMDGPU/GlobalISel: Mark 32-bit integer constants as legal
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D33115

llvm-svn: 302919
2017-05-12 16:46:46 +00:00
Craig Topper 51416caf34 [APInt] Use MathExtras.h BitsToFloat/Double and Float/DoubleToBits instead of type punning through a union
The functions in MathExtras.h uses a safer memcpy instead of going through a union.

Differential Revision: https://reviews.llvm.org/D33116

llvm-svn: 302916
2017-05-12 16:28:21 +00:00
James Y Knight d4e1b00e7c [SPARC] Support 'f' and 'e' inline asm constraints.
Based on patch by Patrick Boettcher and Chris Dewhurst.

Differential Revision: https://reviews.llvm.org/D29116

llvm-svn: 302911
2017-05-12 15:59:10 +00:00
Sanjay Patel ae362303fd [x86] add tests for potential vector narrowing optimization (PR32790)
llvm-svn: 302910
2017-05-12 15:56:39 +00:00
Davide Italiano cc7257c200 [LoopUnroll] Fix a test. REQUIRE should be REQUIRES.
Found by inspection.

llvm-svn: 302909
2017-05-12 15:30:58 +00:00
Davide Italiano c43a9f80ed [NewGVN] Improve debug output a bit. NFCI.
While debugging a predicate info problem, I noticed this was missing
a newline, making the debug output slightly less readable.

llvm-svn: 302908
2017-05-12 15:28:12 +00:00