Commit Graph

13653 Commits

Author SHA1 Message Date
Chris Lattner 87dd2d6388 comment fix.
llvm-svn: 98494
2010-03-14 17:10:52 +00:00
Chris Lattner 28aae17fee shrink 4-byte branches to 1-byte branches when lowering from
MachineInstr -> MCInst.  This is what the assembler backend wants,
it relaxes from smaller to larger things.  This fixes rdar://7750815

llvm-svn: 98493
2010-03-14 17:04:18 +00:00
Chris Lattner 6e52e9db31 get MMI out of the label uniquing business, just go to MCContext
to get unique assembler temporary labels.

llvm-svn: 98489
2010-03-14 08:36:50 +00:00
Chris Lattner d5e8d9f29a Now that DBG_LABEL is updated, we can finally make MachineMove
contain an MCSymbol instead of a label index.

llvm-svn: 98482
2010-03-14 08:12:40 +00:00
Chris Lattner c26f44fb07 change the DBG_LABEL MachineInstr to always be created
with an MCSymbol instead of an immediate.

llvm-svn: 98481
2010-03-14 07:56:48 +00:00
Chris Lattner 1065f49ad9 switch GC_LABEL to use an MCSymbol operand instead of a label ID operand.
llvm-svn: 98474
2010-03-14 07:27:07 +00:00
Evan Cheng d703df67ce Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions.
llvm-svn: 98465
2010-03-14 03:48:46 +00:00
Chris Lattner ee2fbbc978 change the LabelSDNode to be EHLabelSDNode and make it hold
an MCSymbol.  Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID.  Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".

llvm-svn: 98463
2010-03-14 02:33:54 +00:00
Chris Lattner 34adc8d225 change EH related stuff (other than EH_LABEL) to use MCSymbol
instead of label ID's.  This cleans up and regularizes a bunch 
of code and makes way for future progress.

Unfortunately, this pointed out to me that JITDwarfEmitter.cpp
is largely copy and paste from DwarfException/MachineModuleInfo
and other places.  This is very sad and disturbing. :(

One major change here is that TidyLandingPads moved from being
called in DwarfException::BeginFunction to being called in
DwarfException::EndFunction.  There should not be any 
functionality change from doing this, but I'm not an EH expert.

llvm-svn: 98459
2010-03-14 01:41:15 +00:00
Daniel Dunbar f3530bdd8a X86_64: Fix encoding for the rest of the 64i32 instructions too.
llvm-svn: 98458
2010-03-13 22:57:53 +00:00
Daniel Dunbar d324a7c990 X86: Fix ADD64i32 encoding.
llvm-svn: 98457
2010-03-13 22:49:39 +00:00
Chris Lattner 29bdac4928 eliminate the now-unneeded context argument of MBB::getSymbol()
llvm-svn: 98451
2010-03-13 21:04:28 +00:00
Chris Lattner e468f88b26 rearrange MCContext ownership. Before LLVMTargetMachine created it
and passing off ownership to AsmPrinter.  Now MachineModuleInfo
creates it and owns it by value.  This allows us to use MCSymbols
more consistently throughout the rest of the code generator, and
simplifies a bit of code.  This also allows MachineFunction to 
keep an MCContext reference handy, and cleans up the TargetRegistry
interfaces for AsmPrinters.

llvm-svn: 98450
2010-03-13 20:55:24 +00:00
Daniel Dunbar 906a432031 MC/X86_64: Fix matching of leaq.
llvm-svn: 98444
2010-03-13 19:31:44 +00:00
Daniel Dunbar e60c883bf4 MC/X86_64: Fix matching of callq.
llvm-svn: 98443
2010-03-13 19:31:38 +00:00
Chris Lattner 5bb8207c13 simplify some overly general code. The stack always grows down on x86.
llvm-svn: 98431
2010-03-13 08:04:35 +00:00
Benjamin Kramer 13f4db8c29 Fix another warning. There is a functionality change but I believe it's correct.
llvm-svn: 98430
2010-03-13 07:50:22 +00:00
Bob Wilson f1e8f7ff7d Attempt to appease the arm-linux buildbot by fixing the JIT encodings for new
base register updating load/store-multiple instructions.

llvm-svn: 98427
2010-03-13 07:34:35 +00:00
Chris Lattner 81fe45d911 switch to the text section at the start of the .s file for darwin/x86
targets.  This is a temporary hack for the .o file writer that Daniel
wants :)

llvm-svn: 98413
2010-03-13 02:10:00 +00:00
Bob Wilson 947f04bad0 Change ARM ld/st multiple instructions to have variant instructions for
writebacks to the address register.  This gets rid of the hack that the
first register on the list was the magic writeback register operand.  There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand.  The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other.  This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.

llvm-svn: 98409
2010-03-13 01:08:20 +00:00
Daniel Dunbar 18fc344290 MC/X86: Add temporary hack to match shrl $1,%eax correctly, to support testing
other functionality on 403.gcc compiled at -O0.

llvm-svn: 98405
2010-03-13 00:47:29 +00:00
Bob Wilson 53149401ee Combine the code to build VLDM and VSTM instructions, since they are
mostly the same.

llvm-svn: 98402
2010-03-13 00:43:32 +00:00
Bob Wilson af10d27d80 Tidy up. No functional changes.
llvm-svn: 98398
2010-03-12 22:50:09 +00:00
Bob Wilson 27cce1c0b6 Remove obsolete comments. VLDM is implemented in ARMInstrVFP.td.
llvm-svn: 98395
2010-03-12 22:00:08 +00:00
Jeffrey Yasskin 9eeda13a52 Fix LLVM build when the user specifies CPPFLAGS on the make command line.
llvm-svn: 98394
2010-03-12 21:42:14 +00:00
Chris Lattner 013f794dc0 remove special case code that isn't needed anymore.
llvm-svn: 98391
2010-03-12 21:21:19 +00:00
Chris Lattner 0b822ab447 inline GetGlobalValueSymbol into the rest its callers and
remove it.

llvm-svn: 98390
2010-03-12 21:19:23 +00:00
Chris Lattner 9e4cafe6f1 inline the now-trivial implementation of GetGlobalValueSymbol into
some of its callers.

llvm-svn: 98388
2010-03-12 21:09:07 +00:00
Chris Lattner e80055f8fc eliminate the X86 version of GetGlobalValueSymbol, allowing
it to be non-virtual and soon disappear.

llvm-svn: 98387
2010-03-12 21:06:41 +00:00
Chris Lattner d3ca1e2854 prune #includes, this file should be removed pending hte cygwin stub issue being resolved.
llvm-svn: 98386
2010-03-12 21:04:31 +00:00
Chris Lattner 8d99c764d3 move fastcall/stdcall mangling up into Mangler.
llvm-svn: 98384
2010-03-12 21:03:47 +00:00
Daniel Dunbar 968b36a0bd MC: Constify MCAsmLayout argument to MCExpr::EvaluteAs...
llvm-svn: 98380
2010-03-12 21:00:45 +00:00
Chris Lattner c7b46f9d9c give Mangler access to TargetData.
llvm-svn: 98378
2010-03-12 20:47:28 +00:00
Chris Lattner 892ac21f06 make DecorateCygMingName a static method.
llvm-svn: 98377
2010-03-12 20:43:52 +00:00
Chris Lattner 74026ffcae minor tidying, only do work if a function is
actually X86_StdCall or X86_FastCall.

llvm-svn: 98374
2010-03-12 19:48:03 +00:00
Chris Lattner e397df7af0 eliminate the string form of DecorateCygMingName
llvm-svn: 98373
2010-03-12 19:42:40 +00:00
Chris Lattner c795a5235f remove the FnArgWords cache to make way for future changes.
llvm-svn: 98372
2010-03-12 19:31:03 +00:00
Bill Wendling 3d0cd822a9 Add a beta-test for placing the LSDA into the TEXT section on X86.
llvm-svn: 98370
2010-03-12 19:20:40 +00:00
Devang Patel d19e302f77 Fix llc crash on invalid input.
llvm-svn: 98369
2010-03-12 19:18:30 +00:00
Chris Lattner 8abe1ce883 Remove some dead code. This method only gets called on
definitions.

llvm-svn: 98368
2010-03-12 19:14:18 +00:00
Chris Lattner 6428db5089 use Mang->getSymbol instead of duplicating the logic, reduce indentation.
llvm-svn: 98367
2010-03-12 19:04:14 +00:00
Chris Lattner be3242b523 finally give Mangler a getSymbol method, which returns an MCSymbol
for a global instead of messing around with string buffers.

llvm-svn: 98366
2010-03-12 18:55:20 +00:00
Chris Lattner d75813970a simplify code to use OutContext.GetOrCreateTemporarySymbol with
no arguments instead of having to come up with a unique name.
This also makes the code less fragile.

llvm-svn: 98364
2010-03-12 18:47:50 +00:00
Chris Lattner 2eff505fba make the mangler take an MCContext instead of an MAI.
No functionality change.

llvm-svn: 98363
2010-03-12 18:44:54 +00:00
Benjamin Kramer d69ee90f2f Use StringRef::substr instead of std::string::substr to avoid using a free'd
string temporary. This should fix PR6590.

llvm-svn: 98349
2010-03-12 13:54:59 +00:00
Bill Wendling dd3fe94336 The same situation that effected ARM effects PPC with regards to placing the
LSDA into the TEXT section. We need to generate non-lazy pointers to it on
Mach-O. However, the object the NLP points to may be local to the translation
unit. If so, then the NLP needs to have the value of that object specified
instead of "0", which the linker interprets as "external".

llvm-svn: 98325
2010-03-12 02:00:43 +00:00
Chris Lattner 47bef1a8a2 make TargetLoweringObjectFile::getExprForDwarfReference
just make unnamed temp symbols instead of having to come
up with its own names.

llvm-svn: 98324
2010-03-12 01:56:43 +00:00
Bill Wendling faec0815a3 MC-ize PPC's asm printing of stubs.
llvm-svn: 98300
2010-03-11 23:39:44 +00:00
Chris Lattner 03627cb12c fix a fixme in TargetLoweringObjectFile::getExprForDwarfReference
where we used ot create an MCSymbol for ".".  Now emit an assembler
temporary label and reference it instead of "." textually.

rdar://7739457

llvm-svn: 98292
2010-03-11 21:55:20 +00:00
Dan Gohman 576aec4363 Remove getWidenVectorType, which is no longer used.
llvm-svn: 98289
2010-03-11 21:39:57 +00:00
Johnny Chen c1d1229d78 Set the (Format)F filed of t2Int_MemBarrierV7 & t2Int_SyncBarrierV7 to ThumbFrm,
instead of Pseudo, which helps Thumb decoder to recognize them as Thumb instr.

llvm-svn: 98285
2010-03-11 21:02:50 +00:00
Bill Wendling 00810c39da revert r98270.
llvm-svn: 98281
2010-03-11 19:50:31 +00:00
Chris Lattner 2562356992 rename getSymbolForDwarf* to getExprForDwarf* since it returns
an MCExpr and not an MCSymbol.  Change it to take an MCStreamer,
which is currently unused.

No functionality change.

llvm-svn: 98278
2010-03-11 19:41:58 +00:00
Evan Cheng 31fe835bf2 Bad bad bug. x86 force indirect tail call address into eax when it's meant to force it into a call preserved register instead. Change it to ecx for now.
llvm-svn: 98270
2010-03-11 18:49:14 +00:00
Richard Osborne 7aa06ac2b9 Remove dead code. (S|U)MUL_LO is now lowered to LMUL or MACC(S|U)
llvm-svn: 98269
2010-03-11 18:38:59 +00:00
Richard Osborne 4780109254 Add dag combine to simplify lmul(x, 0, a, b)
llvm-svn: 98258
2010-03-11 16:26:35 +00:00
Richard Osborne 29ffbf123f Switch XCore over to using inline jump table entries.
llvm-svn: 98256
2010-03-11 14:58:56 +00:00
Eric Christopher 304f13c637 Have fast-isel understand llvm.objectsize. Update testcase for slightly
different codegen.

llvm-svn: 98244
2010-03-11 06:20:22 +00:00
Daniel Dunbar ac8a95498a MC: Sketch initial MCAsmLayout class, which encapsulates the current layout of an assembly file. The MCAsmLayout is also available for use by MCExpr::EvaluateAs{Absolute,Relocatable}, to allow target specific hooks and "absolutizing" of symbols.
llvm-svn: 98227
2010-03-11 02:28:59 +00:00
Daniel Dunbar 77c4141c8f MC: Sketch some TargetAsmBackend hooks we are going to need.
llvm-svn: 98221
2010-03-11 01:34:21 +00:00
Daniel Dunbar 245f5b2810 MC: Provide the target triple to AsmBackend constructors.
llvm-svn: 98220
2010-03-11 01:34:16 +00:00
Bill Wendling e8e79524d2 When outputing a non-lazy pointer for a stub, we may need to fill in the value
for the NLP because the object it's pointing to may be internal to the file.

This seems counter-intuitive, but bear with me. When we place the LSDA into the
TEXT section, the type info pointers need to be indirect and pc-rel. We
accomplish this by using NLPs. However, sometimes the types are local to the
file. GCC gets around this by not using a NLP in this case, but a "regular"
indirection like this:

GCC_except_tbl:
  .long Lfoo-.

__ZTIA:  @ This is local
  ...

Lfoo:
  .long __ZTIA

LLVM prefers NLPs on Darwin. In fact, it's more optimal for load performance to
use them.

llvm-svn: 98218
2010-03-11 01:18:13 +00:00
Johnny Chen f5e81aeba5 Added Thumb2 LDRD/STRD pre/post variants for disassembly only.
Plus fixed the encoding of t2LDRDpci such that P = 1 and W = 0 (offset mode).

llvm-svn: 98217
2010-03-11 01:13:36 +00:00
Bob Wilson 1b0e614b10 Fix ARM buildbot breakage.
llvm-svn: 98215
2010-03-11 00:46:22 +00:00
Chris Lattner a179e4d0a8 add support, testcases, and dox for the new GHC calling
convention.  Patch by David Terei!

llvm-svn: 98212
2010-03-11 00:22:57 +00:00
Bob Wilson c499fae068 Lower small memcpys to load/stores on Thumb2.
Radar 7686922.

llvm-svn: 98210
2010-03-11 00:20:49 +00:00
Chris Lattner 963b233f2c Work around a bug in the openbsd assembler on i386,
which doesn't support .quad correctly because it is
"really really old".  PR6528.

Yet another reason the mc assembler should take over ;-)

llvm-svn: 98205
2010-03-11 00:06:19 +00:00
Bob Wilson c4ceb1e2f8 Fix an obvious typo in an assert.
Patch by Sean Callanan.

llvm-svn: 98200
2010-03-10 22:38:45 +00:00
Bill Wendling a810bdfcca Add a bit along with the MCSymbols stored in the MachineModuleInfo maps that
indicates that an MCSymbol is external or not. (It's true if it's external.)
This will be used to specify the correct information to add to non-lazy
pointers. That will be explained further when this bit is used.

llvm-svn: 98199
2010-03-10 22:34:10 +00:00
Dale Johannesen 49de0607a8 Progress towards shepherding debug info through SelectionDAG.
No functional effect yet.  This is still evolving and should
not be viewed as final.

llvm-svn: 98195
2010-03-10 22:13:47 +00:00
Chris Lattner 1f6689a8ba move PR6576 here.
llvm-svn: 98194
2010-03-10 21:42:42 +00:00
Jim Grosbach f0a7e8e77d Make sure the LR gets pushed in functions that use vaargs. This fixes
400.perlbench for the nightly tests.

llvm-svn: 98183
2010-03-10 20:01:30 +00:00
Jim Grosbach 77f781405d comment why we use custom epilogue for t1 functions using vaargs.
llvm-svn: 98182
2010-03-10 19:59:47 +00:00
Johnny Chen 9a3e2398ae Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.

llvm-svn: 98172
2010-03-10 18:59:38 +00:00
Richard Osborne 66839831a7 The backend now makes a reasonable job of targeting lmul / macc
llvm-svn: 98169
2010-03-10 18:14:47 +00:00
Richard Osborne 54a2c32670 Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit
expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.

llvm-svn: 98168
2010-03-10 18:12:27 +00:00
Richard Osborne c99b9b2193 Fix checking of intermediates having one use in isADDADDMUL
llvm-svn: 98164
2010-03-10 17:16:29 +00:00
Richard Osborne 5a457de4b2 Extract recognition of patterns such as add(add(mul(x,y),a),b)
into a seperate function.

llvm-svn: 98162
2010-03-10 17:10:35 +00:00
Richard Osborne 11ec7ee125 Fix thinko.
llvm-svn: 98158
2010-03-10 16:27:11 +00:00
Richard Osborne 1a396d53ed Fold add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if the intermediate
results are unused elsewhere.

llvm-svn: 98157
2010-03-10 16:19:31 +00:00
Richard Osborne f57aea3d38 Prefer LMUL to MACCU as LMUL has no tied operands.
llvm-svn: 98153
2010-03-10 13:27:10 +00:00
Richard Osborne 0012bc1e41 Custom lower (S|U)MUL_LOHI -> MACC(S|U)
llvm-svn: 98152
2010-03-10 13:20:07 +00:00
Richard Osborne ef00c1bd6f Fix indentation
llvm-svn: 98151
2010-03-10 11:42:05 +00:00
Richard Osborne 54dfa01adc Lower add (mul a, b), c into MACCU / MACCS nodes which translate
directly to the maccu / maccs instructions. We handle this in
ExpandADDSUB since after type legalisation it is messy to
recognise these operations.

llvm-svn: 98150
2010-03-10 11:41:08 +00:00
Chris Lattner 71c30c164f move three lowering hooks from MAI to TLOF and make one of them
semantic instead of syntactic.  This completes MCization of
darwin/x86[-64]!

llvm-svn: 98145
2010-03-10 07:20:42 +00:00
Chris Lattner ac2361a9b0 set the temporary bit on MCSymbols correctly.
llvm-svn: 98124
2010-03-10 02:25:11 +00:00
Jim Grosbach e620178436 Clear up the last (famous last words) frame index value reuse issues for Thumb1.
llvm-svn: 98109
2010-03-10 00:13:42 +00:00
Daniel Dunbar b70c2f795e MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.
llvm-svn: 98098
2010-03-09 22:50:46 +00:00
Daniel Dunbar f5b6a1118d MC/X86: Rename alternate spellings of CMP{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.
llvm-svn: 98097
2010-03-09 22:50:40 +00:00
Jim Grosbach fae913adf8 Change the Value argument to eliminateFrameIndex to a type-tagged value. This
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).

No functionality change.

llvm-svn: 98086
2010-03-09 21:45:49 +00:00
Johnny Chen 15804db55c MSR (Move to Special Register from ARM core register) requires a mask to specify
what fields of the CPSR or SPSR are affected.

llvm-svn: 98085
2010-03-09 21:39:34 +00:00
Dale Johannesen 90eab67320 The address of an indirect call must be in R12 on Darwin.
Make it so.  (This patch is in LowerCall_Darwin, which seems
to be used by SVR4 code as well; since that doesn't belong here,
I haven't worried about this case.)

llvm-svn: 98077
2010-03-09 20:15:42 +00:00
Jim Grosbach 31f275e63c scavenged frame index value re-use gets confused when more than one base
register is involved for thumb1. Work around this for the moment by only
re-using SP-relative offsets. This is temporary 'til the code can distinguish
multiple base registers.

llvm-svn: 98071
2010-03-09 19:07:28 +00:00
Bill Wendling 9481181d40 The ARM EH experiment worked!
Place the LSDA into the TEXT section for ARM platforms. This involves making the
encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The
references to the type infos are then non-lazy pointers. Revision 98019 changed
the encoding of non-lazy pointers to add the symbol to the non-lazy pointer
definition if it's a local symbol (otherwise, it's external and set to '0' so
that the loader can adjust it to the real value). This paved the way for this
change to work on ARM.

llvm-svn: 98068
2010-03-09 18:31:07 +00:00
Richard Osborne c420c4cb4e In cases where the carry / borrow unused converted ladd / lsub
to an add or a sub.

llvm-svn: 98059
2010-03-09 16:34:25 +00:00
Richard Osborne c5ff63d70f Canonicalize ladd constant to RHS.
llvm-svn: 98058
2010-03-09 16:13:57 +00:00
Richard Osborne f4e76cf44d Add DAG combine for ladd / lsub.
llvm-svn: 98057
2010-03-09 16:07:47 +00:00
Dan Gohman 772952f46e Don't try to fold V_SET0 and V_SETALLONES to loads in medium and
large code models.

llvm-svn: 98042
2010-03-09 03:01:40 +00:00
Bill Wendling 46ffefc66c This is part of an LLC-beta test used to test <rdar://problem/6804645>. Please
bear with the awful code. It won't last in its current state beyond tonight.

llvm-svn: 98040
2010-03-09 02:46:12 +00:00
Bill Wendling ffba5fafb6 Print blank line and clear stubs vector.
llvm-svn: 98019
2010-03-09 00:43:34 +00:00
Bill Wendling f1eae222c9 MC-ize the stub printing in ARM.
llvm-svn: 98018
2010-03-09 00:40:17 +00:00
Chris Lattner d802615d0c don't reset defaults.
llvm-svn: 98004
2010-03-08 23:18:21 +00:00
Bob Wilson 0bfbd9b68c Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand.  We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.

llvm-svn: 98001
2010-03-08 22:56:15 +00:00
Kevin Enderby d2030e38a6 Fix the vmxon entry in the X86InstrInfo.td so it has the correct prefix bytes
for the encoding and is not the same as vmptrld.

llvm-svn: 97992
2010-03-08 22:17:26 +00:00
Daniel Dunbar b59f7734b9 X86: Fix encoding for TEST{8,16,32}rr.
llvm-svn: 97982
2010-03-08 21:10:36 +00:00
Devang Patel 3b548aa8e2 Avoid using DIDescriptor.isNull().
This is a first step towards eliminating checks in Descriptor constructors.

llvm-svn: 97975
2010-03-08 20:52:55 +00:00
Devang Patel bc97f6b757 Revert r97947.
llvm-svn: 97963
2010-03-08 19:20:38 +00:00
Chris Lattner e77f993262 disambiguate some types, add a fixme about some
inconsistent intrinsics.

llvm-svn: 97959
2010-03-08 18:59:49 +00:00
Chris Lattner d8045649a6 fix some more ambiguous patterns, remove another nontemporalstore
pattern which is broken (source and address swapped).

llvm-svn: 97958
2010-03-08 18:57:56 +00:00
Chris Lattner a6d842fac0 Correct immediate sizes.
llvm-svn: 97957
2010-03-08 18:55:15 +00:00
Chris Lattner 6742f1f338 fix a type compatibility bug. imm is i32 in the input
pattern, not i64.

llvm-svn: 97956
2010-03-08 18:52:55 +00:00
Chris Lattner b8a7427636 fix a bunch of partially ambiguous patterns on ARM. As an
example, this:

(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))

is ambiguous because DPR contains both f64 and v2f32.  tblgen
currently accidentally picks f64 because it's first in the 
regclass.

llvm-svn: 97955
2010-03-08 18:51:21 +00:00
Chris Lattner dac58bd094 Fix a bunch of ambiguous patterns which tblgen happens to infer types
for, due to a bug.

llvm-svn: 97953
2010-03-08 18:44:04 +00:00
Chris Lattner 2b7ecfbe40 tidy up
llvm-svn: 97950
2010-03-08 18:29:38 +00:00
Devang Patel fe28599f6f Avoid using DIDescriptor.isNull().
This is a first step towards eliminating unncessary constructor checks in light weight DIDescriptor wrappers.

llvm-svn: 97947
2010-03-08 18:25:48 +00:00
Chris Lattner ca8d590c28 remove a non-temporal store pattern which is not tested and
could never have matched because the operand list was backwards.

llvm-svn: 97933
2010-03-08 03:18:28 +00:00
Wesley Peck 1fb4edc05d Re-committing the failed r97807 commit with changes to eliminate warnings.
llvm-svn: 97891
2010-03-06 23:23:12 +00:00
Anton Korobeynikov c9c8b2713c Describe what's going on with mingw alloca and why do we need separate instruction.
llvm-svn: 97888
2010-03-06 20:07:32 +00:00
Anton Korobeynikov bf16a17fc1 Initial bits of ARMv4-only support.
Patch by John Tytgat!

llvm-svn: 97886
2010-03-06 19:39:36 +00:00
Anton Korobeynikov d5e3fd6dc8 Lower dynamic stack allocation on mingw32 to separate instruction.
We cannot use a normal call here since it has extra unmodelled side
effects (it changes stack pointer). This should fix PR5292.

llvm-svn: 97884
2010-03-06 19:32:29 +00:00
Anton Korobeynikov 6f5523aa8b Do not use '&' prefix for globals when register base field is non-zero, otherwise msp430-as will silently miscompile the code (TI's assembler report an error though).
This fixes PR6349

llvm-svn: 97877
2010-03-06 11:41:12 +00:00
Chris Lattner 29146d417e clean this up.
llvm-svn: 97870
2010-03-06 07:02:28 +00:00
Chris Lattner 4279a078a5 revert r97807, it introduced build warnings.
llvm-svn: 97869
2010-03-06 04:32:46 +00:00
Jim Grosbach 24c9b550b2 Thumb1 epilogue code generation needs to take into account that callee-saved
registers may be restored via a pop instruction, not just a tRestore.
This fixes nightly test 471.omnetep for Thumb1.

llvm-svn: 97867
2010-03-06 03:28:39 +00:00
Evan Cheng 27494232d4 Fix typo.
llvm-svn: 97818
2010-03-05 19:55:55 +00:00
Chris Lattner f0692603d5 fix bss section printing for cell, patch by Kalle Raiskila!
llvm-svn: 97814
2010-03-05 18:55:36 +00:00
Wesley Peck 34004170c5 Reworking the stack layout that the MicroBlaze backend generates.
The MicroBlaze backend was generating stack layouts that did not
conform correctly to the ABI. This update generates stack layouts
which are closer to what GCC does.

Variable arguments support was added as well but the stack layout
for varargs has not been finalized.

llvm-svn: 97807
2010-03-05 15:26:02 +00:00
Evan Cheng 654ec2a663 Fix an oops in x86 sibcall optimization. If the ByVal callee argument is itself passed as a pointer, then it's obviously not safe to do a tail call.
llvm-svn: 97797
2010-03-05 08:38:04 +00:00
Evan Cheng cf67ffa500 Rever 96389 and 96990. They are causing some miscompilation that I do not fully understand.
llvm-svn: 97782
2010-03-05 03:08:23 +00:00
Johnny Chen 70e01cd001 Trivial comment change.
llvm-svn: 97776
2010-03-05 01:45:46 +00:00
Bill Wendling 543ce1f64a Revert r97766. It's deleting a tag.
llvm-svn: 97768
2010-03-05 00:33:59 +00:00
Bill Wendling 6517f88f25 Micro-optimization:
This code:

float floatingPointComparison(float x, float y) {
    double product = (double)x * y;
    if (product == 0.0)
        return product;
    return product - 1.0;
}

produces this:

_floatingPointComparison:
0000000000000000        cvtss2sd        %xmm1,%xmm1
0000000000000004        cvtss2sd        %xmm0,%xmm0
0000000000000008        mulsd           %xmm1,%xmm0
000000000000000c        pxor            %xmm1,%xmm1
0000000000000010        ucomisd         %xmm1,%xmm0
0000000000000014        jne             0x00000004
0000000000000016        jp              0x00000002
0000000000000018        jmp             0x00000008
000000000000001a        addsd           0x00000006(%rip),%xmm0
0000000000000022        cvtsd2ss        %xmm0,%xmm0
0000000000000026        ret

The "jne/jp/jmp" sequence can be reduced to this instead:

_floatingPointComparison:
0000000000000000        cvtss2sd        %xmm1,%xmm1
0000000000000004        cvtss2sd        %xmm0,%xmm0
0000000000000008        mulsd           %xmm1,%xmm0
000000000000000c        pxor            %xmm1,%xmm1
0000000000000010        ucomisd         %xmm1,%xmm0
0000000000000014        jp              0x00000002
0000000000000016        je              0x00000008
0000000000000018        addsd           0x00000006(%rip),%xmm0
0000000000000020        cvtsd2ss        %xmm0,%xmm0
0000000000000024        ret

for a savings of 2 bytes.

This xform can happen when we recognize that jne and jp jump to the same "true"
MBB, the unconditional jump would jump to the "false" MBB, and the "true" branch
is the fall-through MBB.

llvm-svn: 97766
2010-03-05 00:24:26 +00:00
Johnny Chen ece1797542 Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version
of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".

llvm-svn: 97760
2010-03-04 22:24:41 +00:00
Bob Wilson 749ba9a7d5 pr6478: The frame pointer spill frame index is only defined when there is a
frame pointer.

llvm-svn: 97755
2010-03-04 21:42:36 +00:00
Bob Wilson cf6e29a818 pr6480: Don't try producing ld/st-multiple instructions when the address is
an undef value.  This is only going to come up for bugpoint-reduced tests --
correct programs will not access memory at undefined addresses -- so it's not
worth the effort of doing anything more aggressive.

llvm-svn: 97745
2010-03-04 21:04:38 +00:00
Jakob Stoklund Olesen af6ca23294 Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH.
These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG
reads AX in order to avoid reading AH with a REX instruction.

Fix PR6489.

llvm-svn: 97742
2010-03-04 20:42:07 +00:00
Dan Gohman b8ebd408da Fix recognition of 16-bit bswap for C front-ends which emit the
clobber registers in a different order.

llvm-svn: 97741
2010-03-04 19:58:08 +00:00
Chris Lattner 795667b424 not committing what you test = bad.
llvm-svn: 97740
2010-03-04 19:54:45 +00:00
Chris Lattner 6ce8e24b70 make gep matching in fastisel match the base of the gep as a
register if it isn't possible to match the indexes *and* the base.
This fixes some fast isel rejects of load instructions on oggenc.

llvm-svn: 97739
2010-03-04 19:48:19 +00:00
Johnny Chen 334db0ce7f Added 32-bit Thumb instructions for Preload Data (PLD, PLDW) and Preload
Instruction (PLI) for disassembly only.

According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0]" and "pli [pc, #-0"].  The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.

llvm-svn: 97731
2010-03-04 17:40:44 +00:00
Chris Lattner 82cc53388e add a comment.
llvm-svn: 97709
2010-03-04 01:43:43 +00:00
John McCall 25a7b297ad Teach the pic16 target to recognize pic16-*-* triples.
llvm-svn: 97691
2010-03-04 00:21:47 +00:00
Johnny Chen 1d63b9574d Modified the asm string of 16-bit Thumb MUL instruction so that it prints:
MULS <Rdm>, <Rn>, <Rdm>

according to A8.6.105 MUL Encoding T1.

llvm-svn: 97675
2010-03-03 23:15:43 +00:00
Andrew Lenharth a8e87d57be Fix PR6444, note still doesn't compile libgcc2 all the way, but fixes that error. May not fix it in an ABI complient way. It wasn't clear what gcc does
llvm-svn: 97660
2010-03-03 20:15:31 +00:00
Johnny Chen f1e25c7163 Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT,
and STRHT for disassembly only.

llvm-svn: 97655
2010-03-03 18:45:36 +00:00
Chris Lattner db42f3ef2b remove nvload and two patterns that use it which are
better done by dag combine.

llvm-svn: 97633
2010-03-03 02:14:54 +00:00
Johnny Chen f1ea86b567 Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBG
for disassembly only.

llvm-svn: 97632
2010-03-03 02:09:43 +00:00
Chris Lattner 46897d35cb factor the 'in the default address space' check out to a single
'dsload' pattern.  tblgen doesn't check patterns to see if they're
textually identical.  This allows better factoring.

llvm-svn: 97630
2010-03-03 01:52:59 +00:00
Chris Lattner 3fcbbd8673 factor the 'sign extended from 8 bit' patterns better so
that they are not destination type specific.  This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.

llvm-svn: 97629
2010-03-03 01:45:01 +00:00
Evan Cheng e9c46c25a1 - Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).

llvm-svn: 97628
2010-03-03 01:44:33 +00:00
Evan Cheng d8c50c67dc Eliminate unused instruction classes.
llvm-svn: 97617
2010-03-03 00:43:15 +00:00
Johnny Chen 334af68052 Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy for
disassembly only.

llvm-svn: 97614
2010-03-03 00:16:28 +00:00
Chris Lattner 8d63704021 merge two loops over all nodes in the graph into one.
llvm-svn: 97606
2010-03-02 23:12:51 +00:00
Chris Lattner 1eb6eb059c eliminate PreprocessForRMW now that isel handles it.
We still preprocess calls and fp return stuff.

llvm-svn: 97598
2010-03-02 22:33:56 +00:00
Chris Lattner 71ddd8e2aa remove 300 lines of code that is now dead in the MSP430 backend
now that isel handles chains more aggressively.  This also
allows us to make isLegalToFold non-virtual.

llvm-svn: 97597
2010-03-02 22:30:08 +00:00
Chris Lattner dd030701bd Fix some issues in WalkChainUsers dealing with
CopyToReg/CopyFromReg/INLINEASM.  These are annoying because
they have the same opcode before an after isel.  Fix this by
setting their NodeID to -1 to indicate that they are selected,
just like what automatically happens when selecting things that
end up being machine nodes.

With that done, give IsLegalToFold a new flag that causes it to
ignore chains.  This lets the HandleMergeInputChains routine be
the one place that validates chains after a match is successful,
enabling the new hotness in chain processing.  This smarter
chain processing eliminates the need for "PreprocessRMW" in the
X86 and MSP430 backends and enables MSP to start matching it's
multiple mem operand instructions more aggressively.

I currently #if out the dead code in the X86 backend and MSP 
backend, I'll remove it for real in a follow-on patch.

The testcase changes are:
  test/CodeGen/X86/sse3.ll: we generate better code
  test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was 
      miscompiling this before, we now generate correct code
      Convert it to filecheck while I'm at it.
  test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem
      folding to make anton happy. :)

llvm-svn: 97596
2010-03-02 22:20:06 +00:00
Johnny Chen 7041f2cef6 Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.
llvm-svn: 97595
2010-03-02 22:11:06 +00:00
Johnny Chen 9dc2105478 Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as from
the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.

llvm-svn: 97582
2010-03-02 19:38:59 +00:00
Johnny Chen 44908a5e17 Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.

llvm-svn: 97573
2010-03-02 18:14:57 +00:00
Johnny Chen 0dae1cbf1c AL is an optional mnemonic extension for always, except in IT instructions.
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.

Ref: A8.3 Conditional execution
llvm-svn: 97571
2010-03-02 17:57:15 +00:00
Johnny Chen d520eabcb9 Change some asm shift opcode strings to lowercase.
llvm-svn: 97567
2010-03-02 17:03:18 +00:00
Xerxes Ranby 09d9a690d2 fix typo add missing (
llvm-svn: 97565
2010-03-02 13:42:03 +00:00
Xerxes Ranby b1baf6583e Unbreak llvm-arm-linux buildbot and fix PR5309.
llvm-svn: 97564
2010-03-02 13:26:18 +00:00
Chris Lattner f98f124a73 Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection.  Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.

Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.

 17 files changed, 114 insertions(+), 430 deletions(-)

llvm-svn: 97555
2010-03-02 06:34:30 +00:00
Eric Christopher 118dc6a645 Only save vector registers if we've defined for the vector registers.
Fixes PR5309.

llvm-svn: 97554
2010-03-02 06:25:00 +00:00
Bill Wendling 78c5b7a76d Remove dead parameter passing.
llvm-svn: 97536
2010-03-02 01:55:18 +00:00
Dan Gohman 6f34abd092 Floating-point add, sub, and mul are now spelled fadd, fsub, and fmul,
respectively.

llvm-svn: 97531
2010-03-02 01:11:08 +00:00
Chris Lattner bd6e193f54 remove a little hack I did for the old isel, not needed
now that it is gone.

llvm-svn: 97516
2010-03-01 22:51:11 +00:00
Evan Cheng 87d50aa18a Remove the optimize for code size limitation on r67917. Optimize 64-bit imul by constants into leas + shl regardless if optimizing for code size. The size saving from using imulq isn't worth it. Also, the lea and shl instructions may expose further optimization.
llvm-svn: 97507
2010-03-01 22:00:11 +00:00
Chris Lattner 55ef1ebe52 remove a terrible hack that disabled assertions from this file because of build time
problems.  rdar://7697850.

llvm-svn: 97500
2010-03-01 21:20:46 +00:00
Chris Lattner 3780ca6ef2 stop using generated sdnodexforms.
llvm-svn: 97485
2010-03-01 19:38:53 +00:00
Johnny Chen 718ed8a6d5 Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the W
bit should be set to 0 instead of 1.

llvm-svn: 97481
2010-03-01 19:22:00 +00:00
Dan Gohman b0e07d53c1 Add explicit keywords.
llvm-svn: 97460
2010-03-01 17:56:46 +00:00
Dan Gohman 312d604ee2 This is now done.
llvm-svn: 97450
2010-03-01 17:43:57 +00:00
Nathan Keynes 42a5be5121 Add JIT support to the TODO list (test commit)
llvm-svn: 97443
2010-03-01 10:40:41 +00:00
Mikhail Glushenkov abd56bde0e 80-col violations/trailing whitespace.
llvm-svn: 97427
2010-02-28 22:54:30 +00:00
Chris Lattner 56c50da3f6 remove redundant instruction.
llvm-svn: 97374
2010-02-28 07:23:21 +00:00
Dan Gohman 0d8a9af7b8 Add a flag to addPassesToEmit* to disable the Verifier pass run
after LSR, so that clients can opt in.

llvm-svn: 97357
2010-02-28 00:41:59 +00:00
Dan Gohman bdd6405f29 Implement XMM subregs.
Extracting the low element of a vector is now done with EXTRACT_SUBREG,
and the zero-extension performed by load movss is now modeled with
SUBREG_TO_REG, and so on.

Register-to-register movss and movsd are no longer considered copies;
they are two-address instructions which insert a scalar into a vector.

llvm-svn: 97354
2010-02-28 00:17:42 +00:00
Dan Gohman 8c5d683aa9 The mayHaveSideEffects flag is no longer used.
llvm-svn: 97348
2010-02-27 23:47:46 +00:00
Chris Lattner f159afc951 remove a bogus pattern, which had the same pattern as STDU
but codegen'd differently.  This really wanted to use some
sort of subreg to get the low 4 bytes of the G8RC register
or something.  However, it's invalid and nothing is testing
it, so I'm just zapping the bogosity.

llvm-svn: 97345
2010-02-27 21:15:32 +00:00
Chris Lattner a2075d44ad fix an incorrect (overly conservative) predicate.
llvm-svn: 97316
2010-02-27 08:18:55 +00:00
Evan Cheng 228c31f045 Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap.
llvm-svn: 97310
2010-02-27 07:36:59 +00:00
Johnny Chen 38e7bb6f34 Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]

llvm-svn: 97276
2010-02-26 22:04:29 +00:00
Jakob Stoklund Olesen 17d54920d7 Merge PPC instructions FMRS and FMRD into a single FMR instruction.
This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so
fextend has a pattern.

Also allow folding of memory operands on FMRSD.

llvm-svn: 97275
2010-02-26 21:53:24 +00:00
Jakob Stoklund Olesen ddbf7a858e Use the right floating point load/store instructions in PPCInstrInfo::foldMemoryOperandImpl().
The PowerPC floating point registers can represent both f32 and f64 via the
two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to
allow cross-class coalescing. This coalescing only affects whether registers
are spilled as f32 or f64.

Spill slots must be accessed with load/store instructions corresponding to the
class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking
at the instruction opcode which is wrong.

X86 has similar floating point register classes, but doesn't try to fold
memory operands, so there is no problem there.

llvm-svn: 97262
2010-02-26 21:09:24 +00:00
Dale Johannesen dd33104203 Move dbg_value generation to target-independent FastISel,
as X86 is currently the only FastISel target.  Per review.

llvm-svn: 97255
2010-02-26 20:01:55 +00:00
Sanjiv Gupta ef686dc38d The cloner has nothing to do if any of the main or ISR entrypoints are not
present in the module.

llvm-svn: 97232
2010-02-26 18:32:18 +00:00
Sanjiv Gupta 2bdbb3c167 Reapply things reverted back in 97220, with the fixed test case.
llvm-svn: 97228
2010-02-26 17:59:28 +00:00
Dan Gohman 952f6f98bb movl is a cheaper way to materialize 0 without clobbering EFLAGS than movabsq.
llvm-svn: 97227
2010-02-26 16:49:27 +00:00
Richard Osborne 333300e0df Fix XCoreTargetLowering::isLegalAddressingMode() to handle VoidTy.
Previously LoopStrengthReduce would sometimes be unable to find
a legal formula, causing an assertion failure.

llvm-svn: 97226
2010-02-26 16:44:51 +00:00
Chandler Carruth 663f658d87 Revert r97211 and r97213 to get the build green again.
llvm-svn: 97220
2010-02-26 08:43:09 +00:00
Sanjiv Gupta 7828ff9535 Currently in LLVM, names of libcalls are assigned during TargetLowering
object construction. There is no provision to change them when the 
code for a function generated. 
So we have to change these names while printing assembly.

llvm-svn: 97213
2010-02-26 07:31:15 +00:00
Sanjiv Gupta 528b1465e5 Before converting an operand to mem, check if it is legal to do so.
llvm-svn: 97211
2010-02-26 07:27:35 +00:00
Dan Gohman 9300486d68 Delete a bunch of redundant predicates.
llvm-svn: 97201
2010-02-26 01:14:30 +00:00
Johnny Chen 3adff378cc Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE,
and SRS.

llvm-svn: 97164
2010-02-25 20:25:24 +00:00
Johnny Chen 871e5b0926 Added the 32-bit Thumb instructions (BXJ) for disassembly only.
llvm-svn: 97163
2010-02-25 19:05:29 +00:00
Johnny Chen e285f70a42 Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only.
llvm-svn: 97159
2010-02-25 18:46:43 +00:00
Daniel Dunbar 68e22cb5a0 Fix TextAlignFillValue in a few places
llvm-svn: 97151
2010-02-25 18:07:10 +00:00
Johnny Chen 74cca5a989 Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE,
WFI, SEV, SETEND.

llvm-svn: 97149
2010-02-25 17:51:03 +00:00
Dan Gohman 9b80f86e5b Revert r97064. Duncan pointed out that bitcasts are defined in
terms of store and load, which means bitcasting between scalar
integer and vector has endian-specific results, which undermines
this whole approach.

llvm-svn: 97137
2010-02-25 15:20:39 +00:00
Sanjiv Gupta ad117dac4b Each field of auxiliary debug entry is only 1 byte long.
llvm-svn: 97108
2010-02-25 03:54:49 +00:00
Johnny Chen 90adefcf7e Added tNOP for disassembly only.
llvm-svn: 97105
2010-02-25 03:28:51 +00:00
Dan Gohman ec4e1b67bf Truncate from i64 to i32 is "free" on x86-32, because it involves
just discarding one of the registers.

llvm-svn: 97100
2010-02-25 03:04:36 +00:00
Scott Michel 4a99c34873 Revert this patch for the time being. Needs more testing.
llvm-svn: 97099
2010-02-25 02:32:54 +00:00
Johnny Chen 57656da73f Added tSVC and tTRAP for disassembly only.
llvm-svn: 97098
2010-02-25 02:21:11 +00:00
Scott Michel 0ab0ad93bd Large stack frame patch for the CellSPU: handle stack frames that exceed 8176
(511*16) bytes register displacement (D-form).

NOTE: This is a potential headache, given the SPU's local core limitations,
allowing the software developer to commit stack overrun suicide unknowingly.
Also, large SPU stack frames will cause code size explosion. But, one presumes
that the software developer knows what they're doing...

Contributed by Kalle.Raiskila@nokia.com, edited slightly before commit.

llvm-svn: 97091
2010-02-25 01:53:17 +00:00
Jakob Stoklund Olesen 63af51c1c8 Create a stack frame on ARM when
- Function uses all scratch registers AND
- Function does not use any callee saved registers AND
- Stack size is too big to address with immediate offsets.

In this case a register must be scavenged to calculate the address of a stack
object, and the scavenger needs a spare register or emergency spill slot.

llvm-svn: 97071
2010-02-24 22:43:17 +00:00
Bob Wilson ba8ac74fd9 Check for comparisons of +/- zero when optimizing less-than-or-equal and
greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions.  This is
only allowed when UnsafeFPMath is set or when at least one of the operands
is known to be nonzero.

llvm-svn: 97065
2010-02-24 22:15:53 +00:00
Dan Gohman 4b2b48daba Make getTypeSizeInBits work correctly for array types; it should return
the number of value bits, not the number of bits of allocation for in-memory
storage.

Make getTypeStoreSize and getTypeAllocSize work consistently for arrays and
vectors.

Fix several places in CodeGen which compute offsets into in-memory vectors
to use TargetData information.

This fixes PR1784.

llvm-svn: 97064
2010-02-24 22:05:23 +00:00
Wesley Peck 05d9124625 Adding function "lookupGCCName" to MBlazeIntrinsicInfo
Adding the function "lookupGCCName" to the MBlazeIntrinsicInfo
class to support the Clang MicroBlaze target.

Additionally, minor fixes which remove some unused PIC code 
(PIC is not supported yet in the MicroBlaze backend) and
removed some unused variables.

llvm-svn: 97054
2010-02-24 20:16:27 +00:00
Johnny Chen 86ba44a4c7 Added Vector Swap (VSWPd and VSWPq) instructions for disassembly only.
A8.6.405

llvm-svn: 97052
2010-02-24 20:06:07 +00:00
Jakob Stoklund Olesen 0b94eb19e4 Stay away from str <undef> in ARMLoadStoreOpt. This pass does not understand
<undef> operands, and can cause scavenger failures when it translates
<kill,undef> to <kill>.

llvm-svn: 97046
2010-02-24 18:57:08 +00:00
Johnny Chen 03ac201ad9 Fixed typo of opcodestr, should be "vst1", not "vld1".
llvm-svn: 97044
2010-02-24 18:00:40 +00:00
Daniel Dunbar 4811d004be Speculatively revert r97011, "Re-apply 96540 and 96556 with fixes.", again in
the hopes of fixing PPC bootstrap.

llvm-svn: 97040
2010-02-24 17:05:47 +00:00
Dan Gohman 3860521406 When forming SSE min and max nodes for UGE and ULE comparisons, it's
necessary to swap the operands to handle NaN and negative zero properly.

Also, reintroduce logic for checking for NaN conditions when forming
SSE min and max instructions, fixed to take into consideration NaNs and
negative zeros. This allows forming min and max instructions in more
cases.

llvm-svn: 97025
2010-02-24 06:52:40 +00:00
Chandler Carruth f0485ed9ac Remove an unused variable. Was this intentional?
llvm-svn: 97022
2010-02-24 06:09:03 +00:00
Johnny Chen d5c472d811 Added for disassembly VST1 (multiple single elements) which stores elements to
memory from three or four registers and VST2 (multiple two-element structures)
which stores to memory from two double-spaced registers.

A8.6.391 & A8.6.393

llvm-svn: 97018
2010-02-24 02:57:20 +00:00
Jim Grosbach 2921550485 handle very large call frames when require SPAdj != 0 for Thumb1
llvm-svn: 97013
2010-02-24 02:15:43 +00:00
Jim Grosbach 6ad4bcb0da LowerCall() should always do getCopyFromReg() to reference the stack pointer.
Machine instruction selection is much happier when operands are in virtual
registers.

llvm-svn: 97012
2010-02-24 01:43:03 +00:00
Evan Cheng 328a607490 Re-apply 96540 and 96556 with fixes.
llvm-svn: 97011
2010-02-24 01:42:31 +00:00
Jakob Stoklund Olesen a2d8c97b65 DIV8r must define %AX since X86DAGToDAGISel::Select() sometimes uses it
instead of %AL/%AH.

llvm-svn: 97006
2010-02-24 00:39:35 +00:00
Evan Cheng da52f449a0 Fix rev 96389 by restricting the xform to mask that's either signbit or max signed value.
llvm-svn: 96990
2010-02-23 21:51:54 +00:00
Richard Osborne 00fb2ce233 Don't mark call instruction as a barrier.
llvm-svn: 96983
2010-02-23 21:08:11 +00:00
Johnny Chen b14a5c52bc Added for disassembly VLD1 (multiple single elements) which loads memory into
three or four registers and VLD2 (multiple two-element structures) which loads
memory into two double-spaced registers.

A8.6.307 & A8.6.310

llvm-svn: 96980
2010-02-23 20:51:23 +00:00
Nicolas Geoffray 3cc6673fd0 Use the module's context instead of the global context.
llvm-svn: 96977
2010-02-23 19:42:44 +00:00
Chris Lattner 8d7b4393d2 no need to override IsLegalToFold, the base implementation
disables load folding at -O0.

llvm-svn: 96973
2010-02-23 19:33:11 +00:00
Wesley Peck e4801e49c9 Adding the MicroBlaze backend.
The MicroBlaze is a highly configurable 32-bit soft-microprocessor for
use on Xilinx FPGAs. For more information see:
http://www.xilinx.com/tools/microblaze.htm
http://en.wikipedia.org/wiki/MicroBlaze

The current LLVM MicroBlaze backend generates assembly which can be
compiled using the an appropriate binutils assembler.

llvm-svn: 96969
2010-02-23 19:15:24 +00:00
Richard Osborne 3a53f4e240 ECALLF, ECALLT shouldn't be marked as barriers.
llvm-svn: 96964
2010-02-23 18:29:49 +00:00
Richard Osborne f81db146b4 Mark unconditional branches as barriers. Found using -verify-machineinstrs
llvm-svn: 96960
2010-02-23 18:13:38 +00:00
Jim Grosbach 2f840382e2 Spelling. s/suppor /support /
llvm-svn: 96954
2010-02-23 17:16:27 +00:00
Richard Osborne e3eb3105d9 Remove unused lowering function LowerJumpTable
llvm-svn: 96943
2010-02-23 14:17:20 +00:00
Richard Osborne f578196968 Lower BR_JT on the XCore to a jump into a series of jump instructions.
llvm-svn: 96942
2010-02-23 13:25:07 +00:00
Chris Lattner 89f6ec462d disable two patterns that are using non-sensical result pattern types.
llvm-svn: 96903
2010-02-23 07:21:15 +00:00
Chris Lattner 7489838a89 remove a confused pattern that is trying to match an address
then use it as an MMX register (!?).

llvm-svn: 96901
2010-02-23 07:16:12 +00:00
Chris Lattner d17089231a remove a bunch of dead named arguments in input patterns,
though some look dubious afaict, these are all ok.

llvm-svn: 96899
2010-02-23 06:54:29 +00:00
Chris Lattner 48370e14e7 fix a type mismatch in this pattern, where we were using an i64 imm in a
place where an i32 imm was required, the old isel just got lucky.

This fixes CodeGen/X86/x86-64-and-mask.ll

llvm-svn: 96894
2010-02-23 06:09:57 +00:00
Chris Lattner c51b7198a9 reapply my cellspu changes with a fix to not break the old isel.
llvm-svn: 96885
2010-02-23 05:30:43 +00:00
Dan Gohman 7e5c4906dd Revert 96854, 96852, and 96849, unbreaking test/CodeGen/CellSPU/i64ops.ll.
llvm-svn: 96871
2010-02-23 02:33:29 +00:00
Chris Lattner a828850b4d X86InstrInfoSSE.td declares PINSRW as having type v8i16,
don't alis it in the MMX .td file with a different width,
split into two X86ISD opcodes.  This fixes an x86 testcase.

llvm-svn: 96859
2010-02-23 02:07:48 +00:00
Johnny Chen 21dbd6f449 Added versions of VCGE, VCGT, VCLE, and VCLT NEON instructions which compare to
(immediate #0) for disassembly only.

A8.6.283, A8.6.285, A8.6.287, A8.6.290

llvm-svn: 96856
2010-02-23 01:42:58 +00:00
Chris Lattner 22bc26e4cf fix hte last cellspu failure.
llvm-svn: 96854
2010-02-23 01:37:39 +00:00
Chris Lattner 807666783c hack around more crimes in instruction selection.
llvm-svn: 96852
2010-02-23 01:33:17 +00:00
Chris Lattner fbbe2617dc the cell backend is making all sorts of unsafe and incorrect assumptions
about ownership and update policies.  It isn't clear why it is doing all
this lowering at isel time instead of in legalize.  This fixes fcmp64.ll

llvm-svn: 96849
2010-02-23 01:20:00 +00:00
Johnny Chen 886915e3bb Added VCEQ (immediate #0) NEON instruction for disassembly only.
A8.6.281

llvm-svn: 96838
2010-02-23 00:33:12 +00:00
Jim Grosbach 45fceea0e4 Updated version of r96634 (which was reverted due to failing 176.gcc and
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

llvm-svn: 96822
2010-02-22 23:10:38 +00:00
Jim Grosbach 017a505716 Clean up a bit and fix for when SPAdj != 0
llvm-svn: 96818
2010-02-22 22:54:55 +00:00
Jim Grosbach 15f6ed348f The predicate index isn't fixed, so scan for it to make sure we get the proper
value.

Thumb2 uses the tADJCALLSTACK* instructions, and doesn't need t2 versions, so
remove the FIXME entry.

llvm-svn: 96817
2010-02-22 22:47:46 +00:00
Chris Lattner 3ac438b920 remove dupes now.
llvm-svn: 96811
2010-02-22 22:15:05 +00:00
Chris Lattner 435611200b move #includes earlier.
llvm-svn: 96810
2010-02-22 22:14:47 +00:00