34de7768bf
Make the use of the vmla and vmls VFP instructions controllable via cmd line.
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Preliminary testing shows significant performance wins by not using these
instructions.
llvm-svn: 99436
2010-03-24 22:31:46 +00:00
2497d85c9e
Revert the rest of 98679.
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--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U lib/Target/ARM/ARMInstrVFP.td
llvm-svn: 99049
2010-03-20 06:34:02 +00:00
e4191e719b
Revert this change, since it was causing ARM performance regressions.
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--- Reverse-merging r98889 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMInstrVFP.td
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Target/ARM/ARMInstrFormats.td
llvm-svn: 99010
2010-03-19 22:51:32 +00:00
f11aa9e7b4
Get rid of target-specific fp <-> int nodes when still I'm here.
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llvm-svn: 98889
2010-03-18 22:35:45 +00:00
64578d5599
Get rid of target-specific nodes for fp16 <-> fp32 conversion.
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llvm-svn: 98888
2010-03-18 22:35:37 +00:00
71ab18bdd5
Disambiguate the *_UPD and * variants by specifying the writeback flag as 1.
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This is for the disassembly work.
There are cases where this is not possible, for example, A8.6.53 LDM Encoding T1.
In such case, we'll use an adhoc approach to deduce the Opcode programmatically.
llvm-svn: 98679
2010-03-16 21:25:05 +00:00
466d1e3dc2
Remove redundant writeback flag in ARM addressing mode 5.
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llvm-svn: 98648
2010-03-16 18:38:09 +00:00
d7fece38fc
Add codegen support for FP16 on ARM
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llvm-svn: 98502
2010-03-14 18:42:31 +00:00
f1e8f7ff7d
Attempt to appease the arm-linux buildbot by fixing the JIT encodings for new
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base register updating load/store-multiple instructions.
llvm-svn: 98427
2010-03-13 07:34:35 +00:00
947f04bad0
Change ARM ld/st multiple instructions to have variant instructions for
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writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
llvm-svn: 98409
2010-03-13 01:08:20 +00:00
b8a7427636
fix a bunch of partially ambiguous patterns on ARM. As an
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example, this:
(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))
is ambiguous because DPR contains both f64 and v2f32. tblgen
currently accidentally picks f64 because it's first in the
regclass.
llvm-svn: 97955
2010-03-08 18:51:21 +00:00
8c5d683aa9
The mayHaveSideEffects flag is no longer used.
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llvm-svn: 97348
2010-02-27 23:47:46 +00:00
2588efd071
Added VCVT (between floating-point and fixed-point, VFP) for disassembly.
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A8.6.297
llvm-svn: 95885
2010-02-11 18:17:16 +00:00
b618f66c5f
Added VMRS/VMSR for disassembly only.
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A8.6.335 & A8.6.336
llvm-svn: 95703
2010-02-09 22:35:38 +00:00
64e0ae8dd4
Added vcvtb/vcvtt (between half-precision and single-precision, VFP).
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For disassembly only.
A8.6.300
llvm-svn: 95669
2010-02-09 17:21:56 +00:00
9e60686a83
Add VCVTR (between floating-point and integer, VFP) for disassembly purpose.
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The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.
A8.6.295
llvm-svn: 95584
2010-02-08 22:02:41 +00:00
beb1238a85
Add VCMP (VFP floating-point compare without 'E' bit set) for disassembly purpose.
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llvm-svn: 95560
2010-02-08 19:41:48 +00:00
c7e606f132
Added VMOVRRS/VMOVSRR to ARMInstrVFP.td for disassembly purpose.
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A8.6.331 VMOV (between two ARM core registers and two single-precision registers)
llvm-svn: 95548
2010-02-08 17:26:09 +00:00
a778db9a91
VMOVRRD and VMOVDRR both have Inst{7-6} = 0b00.
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llvm-svn: 95397
2010-02-05 18:04:58 +00:00
34a6afc68d
Modified encoding bits specification for VFP instructions. In particular, the D
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bit (Inst{22}) and the M bit (Inst{5}) should be left unspecified. For binary
format instructions, Inst{6} and Inst{4} need to specified for proper decodings.
llvm-svn: 94855
2010-01-29 23:21:10 +00:00
ece825dc4f
Data type suffix must come after predicate.
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llvm-svn: 89723
2009-11-24 01:05:23 +00:00
dbb4140f37
move fconst[sd] to UAL. <rdar://7414913>
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llvm-svn: 89700
2009-11-23 21:08:25 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
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llvm-svn: 89478
2009-11-20 19:57:15 +00:00
969910b3e8
use lower case for readability
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llvm-svn: 87054
2009-11-13 01:17:22 +00:00
e6548f4106
Add a comment.
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llvm-svn: 86706
2009-11-10 19:44:56 +00:00
ad95414c26
Work around assembler not recognizing #0.0 form immediate for vmcp
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llvm-svn: 86548
2009-11-09 15:27:51 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
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llvm-svn: 86494
2009-11-09 00:11:35 +00:00
6203c6868f
fconsts and fconstd are obviously re-materializable.
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llvm-svn: 85410
2009-10-28 18:19:56 +00:00
4a609f3cef
Use fconsts and fconstd to materialize small fp constants.
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llvm-svn: 85362
2009-10-28 01:44:26 +00:00
538984c1c3
Now VFP instructions.
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llvm-svn: 85186
2009-10-27 00:20:49 +00:00
1b2b64f618
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
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ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
3bbc6c3ae6
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
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llvm-svn: 83191
2009-10-01 01:33:39 +00:00
bea6848f9d
Finish scheduling itineraries for NEON.
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llvm-svn: 82788
2009-09-25 18:38:29 +00:00
5090273367
Add Cortex-A8 VFP model.
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llvm-svn: 82483
2009-09-21 20:52:17 +00:00
85b5b027f7
Use NEON for single-precision int<->FP conversions.
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llvm-svn: 78604
2009-08-10 22:17:39 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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llvm-svn: 78321
2009-08-06 16:52:47 +00:00
30bf625ac2
Add NEON single-precision FP support for fabs and fneg.
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llvm-svn: 78101
2009-08-04 20:39:05 +00:00
a3839bc6c0
Match common pattern for FNMAC. Add NEON SP support.
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llvm-svn: 78085
2009-08-04 18:44:29 +00:00
3b9c52c5c1
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
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llvm-svn: 78081
2009-08-04 17:53:06 +00:00
d214b72962
Model fpscr to prevent fcmped / fcmpezs etc from being deleted.
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llvm-svn: 76390
2009-07-20 02:12:31 +00:00
81cdd21dcb
Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2.
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llvm-svn: 75254
2009-07-10 17:03:29 +00:00
d93b5b672f
Mark some pattern-less instructions as neverHasSideEffects.
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llvm-svn: 73252
2009-06-12 20:46:18 +00:00
a52c3b4b8b
Fix a 80 col. violation.
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llvm-svn: 60901
2008-12-11 22:02:02 +00:00
69cc2cbbff
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
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llvm-svn: 60487
2008-12-03 18:15:48 +00:00
9c205bf03c
Fix fuitos encoding.
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llvm-svn: 59344
2008-11-15 00:40:57 +00:00
320902bcfc
fsub{d|s} encoding bugs.
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llvm-svn: 59234
2008-11-13 07:59:48 +00:00
af644b50b4
Consolidate formats; fix FCMPED etc. encodings.
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llvm-svn: 59107
2008-11-12 07:18:38 +00:00
4b6c7efbde
Fix VFP conversion instruction encodings.
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llvm-svn: 59104
2008-11-12 06:41:41 +00:00
a0e2f26320
Fix encoding of single-precision VFP registers.
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llvm-svn: 59102
2008-11-12 02:19:38 +00:00
97ccab888a
Fix FMDRR encoding.
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llvm-svn: 59088
2008-11-11 22:46:12 +00:00
Jim Grosbach