9bc1ed9962
add a note.
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llvm-svn: 99815
2010-03-29 17:02:02 +00:00
c86256fa5d
Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions.
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These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd). The table is specified via
a list of vectors, which can be:
{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}
llvm-svn: 99789
2010-03-29 01:14:22 +00:00
3dad5fbeb9
fix integer negates to use the proper type for the zero vectors,
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this also depends on the new "bitconvert dropping" behavior just
added to tblgen.
llvm-svn: 99757
2010-03-28 08:39:10 +00:00
6c223ee0e9
fix vnot matching to explicitly specify the type of the
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input to be v8i8 or v16i8, which buildvectors get canonicalized to.
This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.
llvm-svn: 99754
2010-03-28 08:08:07 +00:00
0f8a02830a
Fix indentation.
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llvm-svn: 99705
2010-03-27 04:01:23 +00:00
cf603fb1c5
Add a format argument to the N3V and N3VX classes, removing the N3Vf class.
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llvm-svn: 99704
2010-03-27 03:56:52 +00:00
6094cdab9f
Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set
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it as the format for the appropriate N3V*SL*<> classes. These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.
Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):
vmlal.s32 q3, d2, d10[0]
llvm-svn: 99690
2010-03-27 01:03:13 +00:00
44313db557
Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not pass
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through to the generic version. The generic functions use STR/LDR, but T2
needs the t2STR/t2LDR instead so we get the addressing mode correct.
llvm-svn: 99678
2010-03-27 00:09:12 +00:00
93acfbf441
Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified
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to now take a format argument. N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.
llvm-svn: 99676
2010-03-26 23:49:07 +00:00
0b57de3c4c
Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8}
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to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.
Modify VEXTd and VEXTq classes to use the format.
llvm-svn: 99659
2010-03-26 22:28:56 +00:00
2cf04957c2
Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
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follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm. The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from. N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.
Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.
llvm-svn: 99655
2010-03-26 21:26:28 +00:00
bf59859b2b
vldm/vstm can only do up to 16 double-word registers at a time.
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Radar 7797856
llvm-svn: 99630
2010-03-26 18:41:09 +00:00
8fc94d6362
Add N3RegFrm to represent "NEON 3 vector register format" instructions.
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Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).
llvm-svn: 99628
2010-03-26 18:32:20 +00:00
5d4e917d9f
Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily
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dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field. The Vd, Vm fields are interpreted
the same between the two, though.
See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.
llvm-svn: 99590
2010-03-26 01:07:59 +00:00
71fcb4fedd
switch the flag for using NEON for SP floating point to a subtarget 'feature'.
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Re-commit. This time complete with testsuite updates.
llvm-svn: 99570
2010-03-25 23:47:34 +00:00
42bb89c7d9
need to fix 'make check' tests first. revert for a moment.
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llvm-svn: 99569
2010-03-25 23:34:05 +00:00
7fce4e39aa
switch the flag for using NEON for SP floating point to a subtarget 'feature'
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llvm-svn: 99568
2010-03-25 23:32:19 +00:00
a3617ec88a
Removed instruction class NI from ARMInstrFormats.td.
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It doesn't seem to be used anywhere.
llvm-svn: 99566
2010-03-25 23:11:56 +00:00
a43386ba8f
switch the use-vml[as] instructions flag to a subtarget 'feature'
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llvm-svn: 99565
2010-03-25 23:11:16 +00:00
91d2774416
Add NVDupLnFrm and change NVDupLane class to use that format.
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llvm-svn: 99557
2010-03-25 21:49:12 +00:00
4b3b2ef65c
ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu
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llvm-svn: 99549
2010-03-25 20:48:50 +00:00
d82f9002e4
Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to
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expect a Format arg. N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.
llvm-svn: 99548
2010-03-25 20:39:04 +00:00
45ab3f3ccf
Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,
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instead of the current N2V. Format of NVDupLane instances are set to NEONFrm
currently.
llvm-svn: 99518
2010-03-25 17:01:27 +00:00
34de7768bf
Make the use of the vmla and vmls VFP instructions controllable via cmd line.
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Preliminary testing shows significant performance wins by not using these
instructions.
llvm-svn: 99436
2010-03-24 22:31:46 +00:00
bff23ca690
Trivial formating change.
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llvm-svn: 99428
2010-03-24 21:25:07 +00:00
e99953ce9c
Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
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NVCVTFrm will later be used to describe "vcvt with fractional bits".
llvm-svn: 99415
2010-03-24 19:47:14 +00:00
da44d5977f
Reverted r99376. The disassembler will deal with the 2-reg format of these two
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N3VX instructions using special case code.
llvm-svn: 99409
2010-03-24 18:46:34 +00:00
07607382d8
tweak the arm if conversion heuristic
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llvm-svn: 99402
2010-03-24 16:15:14 +00:00
aa9b1c81a7
Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
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llvm-svn: 99376
2010-03-24 01:29:25 +00:00
9b1f60adec
Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
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respectively, and add some more comment.
llvm-svn: 99373
2010-03-24 00:57:50 +00:00
e0874fa02f
try being more permissive for if-conversion on ARM V7. see what the nightly
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test run permformance numbers say as to whether it helps.
llvm-svn: 99355
2010-03-24 00:03:13 +00:00
6a64320da8
Renamed NVdImmFrm to N1RegModImmFrm.
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llvm-svn: 99344
2010-03-23 23:09:14 +00:00
8a687233e3
Fix typo in the comment for N3VX class.
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llvm-svn: 99328
2010-03-23 21:35:03 +00:00
5be6d5a6a9
Add comment.
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llvm-svn: 99327
2010-03-23 21:30:12 +00:00
5dbf39285d
Add New NEON Format NVdVmVCVTFrm.
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Converted some of the NEON vcvt instructions to this format.
llvm-svn: 99326
2010-03-23 21:25:38 +00:00
020023a3fa
Add New NEON Format NVdVmImmFrm.
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llvm-svn: 99322
2010-03-23 20:40:44 +00:00
59f75bba24
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
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These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
llvm-svn: 99309
2010-03-23 18:54:46 +00:00
3968c6a252
Fix bad indentation, 80-column violations, and trailing whitespace.
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llvm-svn: 99295
2010-03-23 17:23:59 +00:00
ac5024bbeb
Add New NEON Format NVdImmFrm.
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Ref: A7.4.6 One register and a modified immediate value.
llvm-svn: 99288
2010-03-23 16:43:47 +00:00
9b680e21c0
Rename some instructions to match the corresponding NEON opcode.
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llvm-svn: 99266
2010-03-23 06:26:18 +00:00
cc0a2a75a0
Change VST1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
llvm-svn: 99265
2010-03-23 06:20:33 +00:00
340861d29e
Change VLD1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
llvm-svn: 99261
2010-03-23 05:25:43 +00:00
e60e3ab624
Rename one more NEON instruction that I missed earlier.
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llvm-svn: 99201
2010-03-22 20:31:39 +00:00
c286c88db0
Regroup some instructions. No functional change.
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llvm-svn: 99192
2010-03-22 18:22:06 +00:00
c53a1125ff
Rename some VLD1/VST1 instructions to match the implementation, i.e., the
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corresponding NEON instructions, instead of operation they are currently
used for.
llvm-svn: 99189
2010-03-22 18:13:18 +00:00
98bf5189d7
Remove some redundant instruction classes.
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llvm-svn: 99187
2010-03-22 18:02:38 +00:00
debe0bdb13
Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to
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specify encoding bits in arguments instead of "let" expressions.
llvm-svn: 99185
2010-03-22 16:43:10 +00:00
7d116ce2e3
Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters.
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llvm-svn: 99182
2010-03-22 16:13:21 +00:00
fed917e078
TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.
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llvm-svn: 99097
2010-03-20 22:36:22 +00:00
162242b63b
pr6652: Use LDM to restore PC to the return address on ARMv4.
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Patch by John Tytgat!
llvm-svn: 99096
2010-03-20 22:20:40 +00:00
Chris Lattner