Bob Wilson
debbbe3fd9
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
...
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
llvm-svn: 104582
2010-05-25 04:43:08 +00:00
Bob Wilson
26fdebcae9
Clean up indentation.
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llvm-svn: 104580
2010-05-25 03:36:52 +00:00
Jakob Stoklund Olesen
adff18518a
Disable invalid coalescer assertion.
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llvm-svn: 104574
2010-05-25 00:15:18 +00:00
Jakob Stoklund Olesen
70affbd988
Use enums instead of literals in the ARM backend.
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llvm-svn: 104573
2010-05-25 00:15:15 +00:00
Bill Wendling
0b7488e8d5
Print out the name of the function during SSC.
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llvm-svn: 104572
2010-05-24 23:16:04 +00:00
Jakob Stoklund Olesen
fdb25de17e
Switch SubRegSet to using symbolic SubRegIndices
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llvm-svn: 104571
2010-05-24 23:03:18 +00:00
Bob Wilson
91b2b8540c
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
...
version of t2MVN already allowed that, but not the register versions.
llvm-svn: 104570
2010-05-24 22:41:19 +00:00
Chris Lattner
76b3de92f2
diaggroup categories should take precedence over diag-specific groups.
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llvm-svn: 104567
2010-05-24 21:55:47 +00:00
Jakob Stoklund Olesen
1181a19318
Lose the dummies
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llvm-svn: 104564
2010-05-24 21:47:01 +00:00
Jakob Stoklund Olesen
edab242488
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
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structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
llvm-svn: 104563
2010-05-24 21:46:58 +00:00
Evan Cheng
1b79babdec
Avoid adding duplicate function live-in's.
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llvm-svn: 104560
2010-05-24 21:33:37 +00:00
Dan Gohman
79b6a0f140
Fix an mmx movd encoding.
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llvm-svn: 104552
2010-05-24 20:51:08 +00:00
Kevin Enderby
dc71cc794b
MC/X86: Add aliases for CMOVcc variants.
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llvm-svn: 104549
2010-05-24 20:32:23 +00:00
Bob Wilson
722bff2c7d
Clean up some extra whitespace.
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llvm-svn: 104544
2010-05-24 20:08:34 +00:00
Bob Wilson
3eb7691858
Thumb2 RSBS instructions were being printed without the 'S' suffix.
...
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
llvm-svn: 104531
2010-05-24 18:44:06 +00:00
Devang Patel
51b37e0bd8
Do not emit line number entries for unknown debug values.
...
This fixes recent regression in store.exp from gdb testsuite.
llvm-svn: 104524
2010-05-24 18:26:49 +00:00
Evan Cheng
755d45be43
LR is in GPR, not tGPR even in Thumb1 mode.
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llvm-svn: 104518
2010-05-24 18:00:18 +00:00
Jakob Stoklund Olesen
ff2d118733
Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are
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never used.
llvm-svn: 104517
2010-05-24 17:55:38 +00:00
Jakob Stoklund Olesen
8a57aeca2a
Use SubRegIndex in SystemZ.
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Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.
llvm-svn: 104515
2010-05-24 17:43:01 +00:00
Jakob Stoklund Olesen
5d56769fb6
SubRegIndex'ize Mips
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llvm-svn: 104514
2010-05-24 17:42:58 +00:00
Jakob Stoklund Olesen
fd6f16fab9
SubRegIndex'ize MSP430
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llvm-svn: 104513
2010-05-24 17:42:55 +00:00
Jakob Stoklund Olesen
8d042c0269
Fix a few places that depended on the numeric value of subreg indices.
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Add assertions in places that depend on consecutive indices.
llvm-svn: 104510
2010-05-24 17:13:28 +00:00
Jakob Stoklund Olesen
6c47d6423c
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
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from ARMRegisterInfo.h
llvm-svn: 104508
2010-05-24 16:54:32 +00:00
Jakob Stoklund Olesen
9340ea59e1
Rename X86 subregister indices to something shorter.
...
Use the tablegen-produced enums.
llvm-svn: 104493
2010-05-24 14:48:17 +00:00
Jakob Stoklund Olesen
1c69646e99
Add the SubRegIndex TableGen class.
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This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
llvm-svn: 104492
2010-05-24 14:48:12 +00:00
Nicolas Geoffray
c5327226e4
Encode the Caml frametable by following what the comment says: the number of descriptors
...
is first emitted, and StackOffsets are emitted in 16 bits.
llvm-svn: 104488
2010-05-24 12:24:11 +00:00
Duncan Sands
e9cd6d069d
Apply timeouts and memory limits in more places. In particular, when
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bugpoint does "Running the code generator to test for a crash" this
gets you a crash if llc goes into an infinite loop or uses up vast
amounts of memory.
llvm-svn: 104485
2010-05-24 07:49:55 +00:00
Daniel Dunbar
6738a2e39e
llvm-mc: Use EmitIntValue where possible, which makes the API calls from the AsmParser and CodeGen line up better.
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llvm-svn: 104467
2010-05-23 18:36:38 +00:00
Daniel Dunbar
8271d1bb4a
llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better.
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llvm-svn: 104466
2010-05-23 18:36:34 +00:00
Daniel Dunbar
3ff1a06de6
MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.
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llvm-svn: 104463
2010-05-23 17:44:06 +00:00
Bob Wilson
49f40e8c32
VDUP doesn't support vectors with 64-bit elements.
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llvm-svn: 104455
2010-05-23 05:42:31 +00:00
Daniel Dunbar
b52fcd6304
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
...
addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
llvm-svn: 104453
2010-05-22 21:02:33 +00:00
Daniel Dunbar
346782c12c
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
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llvm-svn: 104452
2010-05-22 21:02:29 +00:00
Daniel Dunbar
d459e29a0a
MC/X86: Add alias for setz, setnz, jz, jnz.
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llvm-svn: 104435
2010-05-22 06:37:33 +00:00
John Mosby
987a1576d2
Trivial change to dump() function for SparseBitVector
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llvm-svn: 104433
2010-05-22 05:13:17 +00:00
Evan Cheng
168ced94d8
Implement @llvm.returnaddress. rdar://8015977.
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llvm-svn: 104421
2010-05-22 01:47:14 +00:00
Jim Grosbach
bd9485db63
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
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Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
2010-05-22 01:06:18 +00:00
Eric Christopher
64087cd346
This test is darwin only. Make it so(tm).
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llvm-svn: 104418
2010-05-22 00:55:55 +00:00
Bob Wilson
91fdf68516
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
...
copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
llvm-svn: 104415
2010-05-22 00:23:12 +00:00
Eric Christopher
6fdea1bda8
Add full bss data support for darwin tls variables.
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llvm-svn: 104414
2010-05-22 00:10:22 +00:00
Devang Patel
4a8e6e83dc
Collect variable information during endFunction() instead of beginFunction().
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llvm-svn: 104412
2010-05-22 00:04:14 +00:00
Eric Christopher
75ed30b593
Add a new section and accessor for TLS data.
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llvm-svn: 104411
2010-05-22 00:00:58 +00:00
Bob Wilson
61438fe064
Clean up extra whitespace.
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llvm-svn: 104410
2010-05-21 23:53:55 +00:00
Eric Christopher
53ff992dde
Make this LookAheadLimit, not the uninitialized LookAheadLeft.
...
Evan please verify!
llvm-svn: 104408
2010-05-21 23:40:03 +00:00
Chris Lattner
4dc833c607
add a note
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llvm-svn: 104404
2010-05-21 23:16:21 +00:00
Eric Christopher
09d47031b1
Expand on comment.
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llvm-svn: 104396
2010-05-21 23:03:53 +00:00
Kevin Enderby
7e7482c80f
Added retl for 32-bit x86 and added retq for 64-bit x86.
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llvm-svn: 104394
2010-05-21 23:01:38 +00:00
Eric Christopher
0624d5226c
Fix comment and whitespace.
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llvm-svn: 104392
2010-05-21 22:39:11 +00:00
Chris Lattner
37c529ae68
expand on the llvm ir bitcode dox. Patch by Peter Housel!
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llvm-svn: 104391
2010-05-21 22:20:54 +00:00
Evan Cheng
2c8bdead9e
Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.
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llvm-svn: 104385
2010-05-21 21:22:19 +00:00