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31 Commits

Author SHA1 Message Date
Elena Demikhovsky 50b88ddb87 AVX-512: Added logical and arithmetic instructions for SKX 
by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 235375
 2015-04-21 10:27:40 +00:00
Elena Demikhovsky 1eeece1285 AVX-512: intrinsics for VPADD, VPMULDQ and VPSUB 
by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 233906
 2015-04-02 10:51:40 +00:00
Elena Demikhovsky 98de9d6360 AVX-512: added intrinsics for VPAND, VPOR and VPXOR 
by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 233525
 2015-03-30 08:30:34 +00:00
Quentin Colombet f59b2d034c [X86] Fix a regression introduced by r223641. 
The permps and permd instructions have their operands swapped compared to the
intrinsic definition. Therefore, they do not fall into the INTR_TYPE_2OP
category.

I did not create a new category for those two, as they are the only one AFAICT
in that case.

<rdar://problem/20108262>

llvm-svn: 232085
 2015-03-12 19:34:12 +00:00
Elena Demikhovsky 52e81bc499 AVX-512: recommitted 229837 + bugfix + test 
llvm-svn: 230223
 2015-02-23 15:12:31 +00:00
Eric Christopher 0d94fa98e5 Revert "AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics." 
The instructions were being generated on architectures that don't support avx512.

This reverts commit r229837.

llvm-svn: 229942
 2015-02-20 00:45:28 +00:00
Elena Demikhovsky 69e8b45b13 AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics. 
llvm-svn: 229837
 2015-02-19 10:48:04 +00:00
Elena Demikhovsky 714f23bcdb AVX-512: Added support for FP instructions with embedded rounding mode. 
By Asaf Badouh <asaf.badouh@intel.com>

llvm-svn: 229645
 2015-02-18 07:59:20 +00:00
Elena Demikhovsky 7b0dd39db6 AVX-512: Added FMA intrinsics with rounding mode 
By Asaf Badouh and Elena Demikhovsky

Added special nodes for rounding: FMADD_RND, FMSUB_RND..
It will prevent merge between nodes with rounding and other standard nodes.

llvm-svn: 227303
 2015-01-28 10:21:27 +00:00
Elena Demikhovsky fcea06acb5 AVX-512: Added FMA instructions, intrinsics an tests for KNL and SKX targets 
by Asaf Badouh

http://reviews.llvm.org/D6456

llvm-svn: 224764
 2014-12-23 10:30:39 +00:00
Elena Demikhovsky 949b0d46bf AVX-512: Added all forms of BLENDM instructions, 
intrinsics, encoding tests for AVX-512F and skx instructions.

llvm-svn: 224707
 2014-12-22 13:52:48 +00:00
Elena Demikhovsky 72860c341e AVX-512: Added EXPAND instructions and intrinsics. 
llvm-svn: 224241
 2014-12-15 10:03:52 +00:00
Cameron McInally 5fb084e798 [AVX512] Add support for 512b variable bit shift intrinsics. 
llvm-svn: 224028
 2014-12-11 17:13:05 +00:00
Elena Demikhovsky 908dbf48c8 AVX-512: Added all forms of COMPRESS instruction 
+ intrinsics + tests

llvm-svn: 224019
 2014-12-11 15:02:24 +00:00
Elena Demikhovsky 68e04b8613 X86 intrinsics moved form X86ISelLowering.cpp to X86IntrinsicsInfo.h 
X86ISelLowering.cpp has a long switch for intrinsics. I moved a part of
this long switch to the new intrinsics table in X86IntrinsicsInfo.h.
No functional changes, just code and compile time optimization.

llvm-svn: 223641
 2014-12-08 09:03:08 +00:00
Ahmed Bougacha 8b54286d1c [X86] Refactor PMOV[SZ]Xrm to add missing AVX2 patterns. 
Most patterns will go away once the extload legalization changes land.

Differential Revision: http://reviews.llvm.org/D6125

llvm-svn: 223567
 2014-12-06 01:31:07 +00:00
Michael Liao 5bf9578ce4 [X86] Clean up whitespace as well as minor coding style 
llvm-svn: 223339
 2014-12-04 05:20:33 +00:00
Elena Demikhovsky 905a5a606f AVX-512: Scalar ERI intrinsics 
including SAE mode and memory operand.
Added AVX512_maskable_scalar template, that should cover all scalar instructions in the future.

The main difference between AVX512_maskable_scalar<> and AVX512_maskable<> is using X86select instead of vselect.
I need it, because I can't create vselect node for MVT::i1 mask for scalar instruction.

http://reviews.llvm.org/D6378

llvm-svn: 222820
 2014-11-26 10:46:49 +00:00
Cameron McInally 9b7c15a364 [AVX512] Add 512b integer shift by variable intrinsics and patterns. 
llvm-svn: 222786
 2014-11-25 20:41:51 +00:00
Cameron McInally 73a6bca32b [AVX512] Add integer shift by immediate intrinsics. 
llvm-svn: 221811
 2014-11-12 19:58:54 +00:00
Elena Demikhovsky be8808dc3f AVX-512: Intrinsics for ERI 
3 instructions: vrcp28, vrsqrt28, vexp2, only vector forms.
Intrinsics include SAE (Suppres All Exceptions) parameter.

http://reviews.llvm.org/D6214

llvm-svn: 221774
 2014-11-12 07:31:03 +00:00
Robert Khasanov b51bb22611 [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VPCMP/VPCMPU{BWDQ} 
Added CMP_MASK_CC intrinsic type.
Added tests for intrinsics.

Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com>

llvm-svn: 219316
 2014-10-08 15:49:26 +00:00
Robert Khasanov 28a7df0b5f [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of VCMPGT{BWDQ}. 
Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com>

llvm-svn: 218670
 2014-09-30 12:15:52 +00:00
Robert Khasanov 5aa4445bde [AVX512] Added intrinsics for 128- and 256-bit versions of VCMPEQ{BWDQ} 
Fixed lowering of this intrinsics in case when mask is v2i1 and v4i1.
Now cmp intrinsics lower in the following way:
 (i8 (int_x86_avx512_mask_pcmpeq_q_128
             (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
 (i8 (bitcast
   (v8i1 (insert_subvector undef,
           (v2i1 (and (PCMPEQM %a, %b),
                      (extract_subvector
                         (v8i1 (bitcast %mask)), 0))), 0))))

llvm-svn: 218669
 2014-09-30 11:41:54 +00:00
Robert Khasanov b25e562d14 [AVX512] Added intrinsics for VPCMPEQB and VPCMPEQW. 
Added new operand type for intrinsics (IIT_V64)

llvm-svn: 218668
 2014-09-30 11:32:22 +00:00
Robert Khasanov a27c8e0fd9 [AVX512] Enabled intrinsics for VPCMPEQD and VPCMPEQQ. 
Added CMP_MASK intrinsic type

llvm-svn: 218667
 2014-09-30 11:19:50 +00:00
Elena Demikhovsky 0f54a0b02a Fixed compilation problem on Windows (initialization of non-aggregate type). 
After commit 217131.

llvm-svn: 217134
 2014-09-04 07:20:39 +00:00
Elena Demikhovsky 228ab3d7b3 X86 Intrinsics table - changed to a static table sorted by intrinsic id. 
Used binary search over the tables.

llvm-svn: 217131
 2014-09-04 06:34:34 +00:00
Elena Demikhovsky 22e735d725 X86 intrinsics table - simplifies intrinsics lowering. 
The tables are initialized when X86TargetLowering object is created.

llvm-svn: 216345
 2014-08-24 09:19:56 +00:00
Elena Demikhovsky c0b420fdf5 Reverted last commit 
llvm-svn: 215827
 2014-08-17 09:36:07 +00:00
Elena Demikhovsky 2bb991a0c5 Added a table for intrinsics on X86. 
It should remove dosens of lines in handling instrinsics (in a huge switch) and give an easy way to add new intrinsics.
I did not completed to move al intrnsics to the table, I'll do this in the upcomming commits.

llvm-svn: 215826
 2014-08-17 09:00:20 +00:00