Commit Graph

158121 Commits

Author SHA1 Message Date
Petr Hosek 34ea06b09e [CMake] Pass LLVM_HAVE_LINK_VERSION_SCRIPT to external projects
Some external projects depend on this LLVM CMake variable.

Differential Revision: https://reviews.llvm.org/D41205

llvm-svn: 320658
2017-12-13 23:49:51 +00:00
Shoaib Meenai a9844566d3 [cmake] Add support for case-sensitive Windows SDKs
When the Windows SDK is hosted on a case-sensitive filesystem (e.g. when
compiling on Linux and not using ciopfs), we can automatically generate
a VFS overlay for headers and symlinks for libraries.

Differential Revision: https://reviews.llvm.org/D41156

llvm-svn: 320657
2017-12-13 23:38:12 +00:00
Shoaib Meenai 02fd152297 [cmake] Support host architectures other than x64
Allow building for other architectures when cross-compiling for Windows.

Differential Revision: https://reviews.llvm.org/D41158

llvm-svn: 320656
2017-12-13 23:12:38 +00:00
Craig Topper f82867c95a Recommit r320461 "[X86] Use regular expressions more aggressively to reduce the number of scheduler entries needed for FMA3 instructions."
I've hopefully sidestepped the MSVC issue that caused it to be reverted. We no longer include the Sched enum from X86GenInstrInfo.inc on the X86 target. So hopefully MSVC's preprocessor will skip over it and nothing will notice the 11000 character enum name.

Original commit message:

When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models.

This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do.

llvm-svn: 320655
2017-12-13 23:11:30 +00:00
Sanjay Patel 558a465473 [EarlyCSE] recognize swapped variants of abs/nabs as equivalent
Extends https://reviews.llvm.org/rL320640

Differential Revision: https://reviews.llvm.org/D41136

llvm-svn: 320653
2017-12-13 22:57:35 +00:00
Simon Pilgrim 5af7a6ddf2 [X86] Add missing MULX32 schedule test
llvm-svn: 320651
2017-12-13 22:43:55 +00:00
Yaxun Liu a5315a040d CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
Two issues were found about machine inst scheduler when compiling ProRender
with -g for amdgcn target:

GCNScheduleDAGMILive::schedule tries to update LiveIntervals for DBG_VALUE, which it
should not since DBG_VALUE is not mapped in LiveIntervals.

when DBG_VALUE is the last instruction of MBB, ScheduleDAGInstrs::buildSchedGraph and
ScheduleDAGMILive::scheduleMI does not move RPTracker properly, which causes assertion.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D41132

llvm-svn: 320650
2017-12-13 22:38:09 +00:00
Zachary Turner 048f8f99bf [CodeView] Teach clang to emit the .debug$H COFF section.
Currently this is an LLVM extension to the COFF spec which is
experimental and intended to speed up linking.  For now it is
behind a hidden cl::opt flag, but in the future we can move it
to a "real" cc1 flag and have the driver pass it through whenever
it is appropriate.

The patch to actually make use of this section in lld will come
in a followup.

Differential Revision: https://reviews.llvm.org/D40917

llvm-svn: 320649
2017-12-13 22:33:58 +00:00
Michael Zolotukhin 67b04bd8ac Recover some overzealously removed includes.
llvm-svn: 320648
2017-12-13 22:21:02 +00:00
Sanjay Patel 37373dd512 [EarlyCSE] add tests for swapped abs/nabs; NFC
llvm-svn: 320647
2017-12-13 22:19:40 +00:00
Hans Wennborg 886b2f868d Speculative build fix for llvm-pdbdump on Linux after Michael's #include removals
llvm-svn: 320646
2017-12-13 22:12:58 +00:00
Hans Wennborg 86f0b70f37 Speculative build fix for lld on Linux after Michael's #include removals
llvm-svn: 320645
2017-12-13 22:12:57 +00:00
Simon Pilgrim 49dbfe7de9 [X86] Add CLWB schedule test
llvm-svn: 320644
2017-12-13 22:09:09 +00:00
Sam Clegg 0fc5599f52 [WebAssembly] Use bitfield types in wasm YAML representation
Differential Revision: https://reviews.llvm.org/D41202

llvm-svn: 320642
2017-12-13 22:02:25 +00:00
Brian M. Rzycki 580bc3c8fa Reverting [JumpThreading] Preservation of DT and LVI across the pass
Stage 2 bootstrap failed:
http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/14434

llvm-svn: 320641
2017-12-13 22:01:17 +00:00
Sanjay Patel 3c7a35de7f [EarlyCSE] recognize commuted and swapped variants of min/max as equivalent (PR35642)
As shown in:
https://bugs.llvm.org/show_bug.cgi?id=35642
...we can have different forms of min/max, so we should recognize those here in EarlyCSE 
similar to how we already handle binops and compares that can commute.

Differential Revision: https://reviews.llvm.org/D41136

llvm-svn: 320640
2017-12-13 21:58:15 +00:00
Sam Clegg 75f8360e28 [WebAssembly] Add linking metatdata test coverage for wasm2yaml
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish

Differential Revision: https://reviews.llvm.org/D41196

llvm-svn: 320639
2017-12-13 21:53:40 +00:00
Simon Pilgrim 14318c5b31 [X86] Move ADX schedule tests out of schedule-x86_64.ll
llvm-svn: 320637
2017-12-13 21:49:09 +00:00
Michael Zolotukhin ad24af7f58 Remove redundant includes from lib/Target/X86.
llvm-svn: 320636
2017-12-13 21:31:19 +00:00
Michael Zolotukhin caf9ea6aa0 Remove redundant includes from lib/Target/ARM.
llvm-svn: 320635
2017-12-13 21:31:17 +00:00
Michael Zolotukhin a859bd9ced Remove redundant includes from lib/Target/AArch64.
llvm-svn: 320634
2017-12-13 21:31:16 +00:00
Michael Zolotukhin eb905c7e41 Remove redundant includes from lib/Target/*.cpp.
llvm-svn: 320633
2017-12-13 21:31:14 +00:00
Michael Zolotukhin 4d6b43ca94 Remove redundant includes from utils/TableGen.
llvm-svn: 320632
2017-12-13 21:31:13 +00:00
Michael Zolotukhin 62602a476a Remove redundant includes from tools.
llvm-svn: 320631
2017-12-13 21:31:10 +00:00
Michael Zolotukhin 5c0ab473f2 Remove redundant includes from unittests.
llvm-svn: 320630
2017-12-13 21:31:05 +00:00
Michael Zolotukhin d8920b1c44 Remove redundant includes from various places.
llvm-svn: 320629
2017-12-13 21:31:03 +00:00
Michael Zolotukhin 6af4f232b5 Remove redundant includes from lib/Transforms.
llvm-svn: 320628
2017-12-13 21:31:01 +00:00
Michael Zolotukhin da9f402677 Remove redundant includes from lib/Support.
llvm-svn: 320627
2017-12-13 21:30:58 +00:00
Michael Zolotukhin 6c02f9b884 Remove redundant includes from lib/ProfileData.
llvm-svn: 320626
2017-12-13 21:30:57 +00:00
Michael Zolotukhin fdfbab2baf Remove redundant includes from lib/Object.
llvm-svn: 320625
2017-12-13 21:30:55 +00:00
Michael Zolotukhin 910c0129c8 Remove redundant includes from lib/MC.
llvm-svn: 320624
2017-12-13 21:30:54 +00:00
Michael Zolotukhin e893b46b4a Remove redundant includes from lib/LTO.
llvm-svn: 320623
2017-12-13 21:30:53 +00:00
Michael Zolotukhin f05cb4374d Remove redundant includes from lib/IR.
llvm-svn: 320622
2017-12-13 21:30:52 +00:00
Michael Zolotukhin a44d5fe333 Remove redundant includes from lib/ExecutionEngine.
llvm-svn: 320621
2017-12-13 21:30:50 +00:00
Michael Zolotukhin 0c169bf7f7 Remove redundant includes from lib/DebugInfo.
llvm-svn: 320620
2017-12-13 21:30:49 +00:00
Michael Zolotukhin c468b648fd Remove redundant includes from lib/CodeGen.
llvm-svn: 320619
2017-12-13 21:30:47 +00:00
Michael Zolotukhin bda7dd5c31 Remove redundant includes from lib/Bitcode.
llvm-svn: 320618
2017-12-13 21:30:45 +00:00
Michael Zolotukhin b45595bd00 Remove redundant includes from lib/Analysis.
llvm-svn: 320617
2017-12-13 21:30:41 +00:00
Shoaib Meenai 75aab6e625 [cmake] Explicitly set VS 2017 compatibility
When cross-compiling using clang-cl 5.0 (which is currently the latest
stable release of the compiler), the default MS compatibility level is
set to VS 2013, which is too low to build LLVM. Explicitly set the
compatibility level to VS 2017 to support cross-compiling LLVM for
Windows using clang-cl 5.0. This will be a no-op when using clang-cl 6.0
and above, where the default MS compatibility level is already VS 2017.

Differential Revision: https://reviews.llvm.org/D41157

llvm-svn: 320616
2017-12-13 21:12:37 +00:00
Shoaib Meenai 3957bf30cc [cmake] Determine MSVC host triple correctly when cross-compiling
CMAKE_CL_64 will never be set when cross-compiling with clang-cl, since
CMake relies on an actual VS environment in order to determine it.
Instead, use the size of a void pointer to determine the bit width of
the host compiler (and therefore the host triple), which works for both
native and cross compilation.

Note that, with the impending advent of Windows on AArch64, assuming
that a 64-bit host == x86_64 isn't correct either, but that's something
to be addressed in a follow-up.

Differential Revision: https://reviews.llvm.org/D41155

llvm-svn: 320615
2017-12-13 21:11:14 +00:00
Matt Arsenault cad7fa857c AMDGPU: Partially fix disassembly of MIMG instructions
Stores failed to decode at all since they didn't have a
DecoderNamespace set. Loads worked, but did not change
the register width displayed to match the numbmer of
enabled channels.

The number of printed registers for vaddr is still wrong,
but I don't think that's encoded in the instruction so
there's not much we can do about that.

Image atomics are still broken. MIMG is the same
encoding for SI/VI, but the image atomic classes
are split up into encoding specific versions unlike
every other MIMG instruction. They have isAsmParserOnly
set on them for some reason. dmask is also special for
these, so we probably should not have it as an explicit
operand as it is now.

llvm-svn: 320614
2017-12-13 21:07:51 +00:00
Brian M. Rzycki d989af98b3 [JumpThreading] Preservation of DT and LVI across the pass
Summary:
See D37528 for a previous (non-deferred) version of this
patch and its description.

Preserves dominance in a deferred manner using a new class
DeferredDominance. This reduces the performance impact of
updating the DominatorTree at every edge insertion and
deletion. A user may call DDT->flush() within JumpThreading
for an up-to-date DT. This patch currently has one flush()
at the end of runImpl() to ensure DT is preserved across
the pass.

LVI is also preserved to help subsequent passes such as
CorrelatedValuePropagation. LVI is simpler to maintain and
is done immediately (not deferred). The code to perfom the
preversation was minimally altered and was simply marked
as preserved for the PassManager to be informed.

This extends the analysis available to JumpThreading for
future enhancements. One example is loop boundary threading.

Reviewers: dberlin, kuhar, sebpop

Reviewed By: kuhar, sebpop

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D40146

llvm-svn: 320612
2017-12-13 20:52:26 +00:00
Aditya Kumar 49c03b11df [GVNHoist] Fix: PR35222 gvn-hoist incorrectly erases load
w.r.t. the paper
"A Practical Improvement to the Partial Redundancy Elimination in SSA Form"
(https://sites.google.com/site/jongsoopark/home/ssapre.pdf)

Proper dominance check was missing here, so having a loopinfo should not be required.
Committing this diff as this fixes the bug, if there are
further concerns, I'll be happy to work on them.

Differential Revision: https://reviews.llvm.org/D39781

llvm-svn: 320607
2017-12-13 19:40:07 +00:00
Adrian Prantl 46af7316ea Ignore metainstructions during the shrink wrap analysis
Shrink wrapping should ignore DBG_VALUEs referring to frame indices,
since the presence of debug information must not affect code
generation.

Differential Revision: https://reviews.llvm.org/D41187

llvm-svn: 320606
2017-12-13 19:10:54 +00:00
Jonas Devlieghere ce5930af5c [dsymutil][test] Fix failing test when no lipo binary available
The invocation without -no-output would try to lipo the different debug
objects together. This wouldn't work on platforms that don't provide
that utility.

llvm-svn: 320605
2017-12-13 18:35:39 +00:00
Simon Pilgrim f02a39c371 [X86] Add JCC/JECXZ/JECXZ/JRCXZ/LOOP schedule tests
llvm-svn: 320603
2017-12-13 18:09:45 +00:00
Amaury Sechet a402e51428 Regenerate test-shrink.ll test results. NFC
llvm-svn: 320602
2017-12-13 18:04:57 +00:00
Jonas Devlieghere 2fbee4f869 [dsymutil] Re-enable threading
Threading was disabled in r317263 because it broke a test in combination
with `-DLLVM_ENABLE_THREADS=OFF`. This was because a ThreadPool warning
was piped to llvm-dwarfdump which was expecting to read an object from
stdin.

This patch re-enables threading and fixes the offending test.
Unfortunately this required more than just moving the ThreadPool out of
the for loop because of the TempFile refactoring that took place in the
meantime.

Differential revision: https://reviews.llvm.org/D41180

llvm-svn: 320601
2017-12-13 18:03:04 +00:00
Simon Pilgrim 542a711806 [X86] Add RET/RETF schedule tests
llvm-svn: 320600
2017-12-13 17:50:40 +00:00
Simon Pilgrim c1bd968c8c [X86] Add POP/PUSH schedule tests
llvm-svn: 320598
2017-12-13 17:42:25 +00:00
Brian M. Rzycki dde93259a3 [Function] Remove trailing end-of-line whitespace. NFC.
llvm-svn: 320595
2017-12-13 16:56:18 +00:00
Nemanja Ivanovic 6af7524063 Fix link failure on one build bot introduced by r320584.
llvm-svn: 320589
2017-12-13 15:28:01 +00:00
Galina Kistanova 9dee3f0a97 Reverted r320229. It broke tests on builder llvm-clang-x86_64-expensive-checks-win.
llvm-svn: 320588
2017-12-13 15:26:27 +00:00
Simon Pilgrim 0bd31a8360 [X86] Add PREFETCH schedule tests
llvm-svn: 320587
2017-12-13 15:12:02 +00:00
Simon Pilgrim 1df18ee3fc [X86] Add XCHG schedule tests
llvm-svn: 320586
2017-12-13 15:02:10 +00:00
Simon Pilgrim 9d9f170172 [X86] Add MOVNTI schedule tests
llvm-svn: 320585
2017-12-13 14:51:06 +00:00
Nemanja Ivanovic 6f590bf8bb [PowerPC] MachineSSA pass to reduce the number of CR-logical operations
The initial implementation of an MI SSA pass to reduce cr-logical operations.
Currently, the only operations handled by the pass are binary operations where
both CR-inputs come from the same block and the single use is a conditional
branch (also in the same block).

Committing this off by default to allow for a period of field testing. Will
enable it by default in a follow-up patch soon.

Differential Revision: https://reviews.llvm.org/D30431

llvm-svn: 320584
2017-12-13 14:47:35 +00:00
Simon Pilgrim 88e6f83f9e [X86] Add ENTER/LEAVE schedule tests
llvm-svn: 320583
2017-12-13 14:46:33 +00:00
Simon Pilgrim cef5b64fdb [X86] Add IMUL schedule tests
llvm-svn: 320582
2017-12-13 14:24:04 +00:00
Simon Pilgrim f00ea1b4cd [X86] Add RDMSR/WRMSR, RDPMC + RDTSC/RDTSCP schedule tests
Add missing RDTSCP itinerary

llvm-svn: 320581
2017-12-13 14:22:04 +00:00
Simon Pilgrim 46ec195d19 [X86] Add ARPL/BOUND schedule tests
llvm-svn: 320580
2017-12-13 13:54:45 +00:00
Alex Bradbury 845e5dce83 [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools
Unfortunately these aren't defined explicitly in the privileged spec, but the
GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the
usual `sfence.vma rs, rt`.

llvm-svn: 320575
2017-12-13 12:46:55 +00:00
Igor Laevsky d209ff9814 [FuzzMutate] Only generate loads and stores to the first class sized types
Differential Revision: https://reviews.llvm.org/D41109

llvm-svn: 320573
2017-12-13 11:49:04 +00:00
Igor Laevsky f39a29265c [FuzzMutate] Avoid zero sized aggregates
Differential Revision: https://reviews.llvm.org/D41110

llvm-svn: 320572
2017-12-13 11:47:35 +00:00
Igor Laevsky 541f9707a5 [FuzzMutate] Correctly split landingpad blocks
Differential Revision: https://reviews.llvm.org/D41112

llvm-svn: 320571
2017-12-13 11:45:53 +00:00
Simon Pilgrim f51f4d3623 [X86][SSE] MOVMSK only uses the sign bit from each vector element
Pass the input vector through SimplifyDemandedBits as we only need the sign bit from each vector element of MOVMSK

We'd probably get more hits if SimplifyDemandedBits was better at handling vectors...

Differential Revision: https://reviews.llvm.org/D41119

llvm-svn: 320570
2017-12-13 11:43:14 +00:00
Alex Bradbury fa7e4ec837 [RISCV] Implement floating point assembler pseudo instructions
Adds the assembler aliases for the floating point instructions
which can be mapped to a single canonical instruction. The missing
pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

This patch builds upon D40902.

Differential Revision: https://reviews.llvm.org/D41071

Patch by Mario Werner.

llvm-svn: 320569
2017-12-13 11:37:19 +00:00
Igor Laevsky e0edb66475 Reintroduce r320049, r320014 and r319894.
OpenGL issues should be fixed by now.

llvm-svn: 320568
2017-12-13 11:21:18 +00:00
Roger Ferrer Ibanez e8d4e88bab [DAG] Promote ADDCARRY / SUBCARRY
Add missing case that was not implemented yet.

Differential Revision: https://reviews.llvm.org/D38942

llvm-svn: 320567
2017-12-13 10:45:21 +00:00
Francis Visoiu Mistrih b41dbbe325 [CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and debug output
Work towards the unification of MIR and debug output by printing `%jump-table.0` instead of `<jt#0>`.

Only debug syntax is affected.

llvm-svn: 320566
2017-12-13 10:30:59 +00:00
Francis Visoiu Mistrih b3a0d51374 [CodeGen] Print target index operands as target-index(target-specific) + 8 in both MIR and debug output
Work towards the unification of MIR and debug output by printing `target-index(target-specific) + 8` instead of `<ti#0+8>` and `target-index(target-specific) + 8` instead of `<ti#0-8>`.

Only debug syntax is affected.

llvm-svn: 320565
2017-12-13 10:30:51 +00:00
Francis Visoiu Mistrih 26ae8a6582 [CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`%const.0 + 8` instead of `<cp#0+8>` and `%const.0 - 8` instead of
`<cp#0-8>`.

Only debug syntax is affected.

Differential Revision: https://reviews.llvm.org/D41116

llvm-svn: 320564
2017-12-13 10:30:45 +00:00
Stefan Maksimovic 0a075d68ec [mips] Provide additional DSP bitconvert patterns
Previously, v2i16 -> f32 bitcast could not be matched.
Add patterns to support matching this and similar types of bitcasts.

Differential revision: https://reviews.llvm.org/D40959

llvm-svn: 320562
2017-12-13 10:13:35 +00:00
Pavel Labath 56c2d99979 [Testing/Support] Make the HasValue matcher composable
Summary:
This makes it possible to run an arbitrary matcher on the value
contained within the Expected<T> object.

To do this, I've needed to fully spell out the matcher, instead of using
the shorthand MATCHER_P macro.

The slight gotcha here is that standard template deduction will fail if
one tries to match HasValue(47) against an Expected<int &> -- the
workaround is to use HasValue(testing::Eq(47)).

The explanations produced by this matcher have changed a bit, since now
we delegate to the nested matcher to print the value. Since these don't
put quotes around the value, I've changed our PrintTo methods to match.

Reviewers: zturner

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41065

llvm-svn: 320561
2017-12-13 10:00:38 +00:00
Alex Bradbury 19c9314aea [RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention
When an instruction mnemonic contains a '.', we usually name the instruction
with a _ in that place. e.g. fadd.s -> FADD_S.

This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP.

Also includes some minor formatting changes in RISCVInstrInfoC.td to better
align it with the formatting conventions in the rest of the backend.

llvm-svn: 320560
2017-12-13 09:57:25 +00:00
Alex Bradbury 581d6b081d [RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted position
We sort these helper functions and td definitions by bit width. simm6 was
previously out-of-order with respect to the others.

llvm-svn: 320559
2017-12-13 09:41:21 +00:00
Alex Bradbury 60714f98ba [RISCV] MC layer support for the remaining RVC instructions
Differential Revision: https://reviews.llvm.org/D40003

Patch by Shiva Chen.

llvm-svn: 320558
2017-12-13 09:32:55 +00:00
Gadi Haber 6090c148dc [X86][BMI]: Adding full coverage of MC encoding for the BMI isa set.<NFC>
NFC.
Adding MC regressions tests to cover the BMI1 and BMI2 ISA sets both 32 and 64 bit.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
started in revision: https://reviews.llvm.org/D39952

Reviewers: zvi, craig.topper, m_zuckerman, RKSimon
Differential Revision: https://reviews.llvm.org/D41106

Change-Id: I033ce137b5b82d36e1e601cd5e0534637b43a4a9
llvm-svn: 320557
2017-12-13 09:13:53 +00:00
Alex Bradbury c35aae36d5 [cmake] Fix host tools build in when LLVM_EXPERIMENTAL_TARGETS_TO_BUILD is set
r320413 triggered cmake configure failures when building with 
-DLLVM_OPTIMIZED_TABLEGEN=True and with LLVM_EXPERIMENTAL_TARGETS_TO_BUILD set 
(e.g. to RISCV). This is because that patch moved to passing through 
LLVM_TARGETS_TO_BUILD, and at that point LLVM_EXPERIMENTAL_TARGETS_TO_BUILD 
has been merged in to it. LLVM_EXPERIMENTAL_TARGETS_TO_BUILD must be also be 
passed through to avoid errors like below:

-- Constructing LLVMBuild project information
CMake Error at CMakeLists.txt:682 (message):
  The target `RISCV' does not exist.

      It should be one of


  AArch64;AMDGPU;ARM;BPF;Hexagon;Lanai;Mips;MSP430;NVPTX;PowerPC;Sparc;SystemZ;X86;XCore


-- Configuring incomplete, errors occurred!

See the thread
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20171211/509225.html 
for discussion of this fix.

llvm-svn: 320556
2017-12-13 09:02:13 +00:00
Serguei Katkov ac4a8fb1cd Revert "[CGP] Enable select in complex addr mode"
Causes: Assertion `ScaledReg == nullptr' failed.

This actually a revert of rL320551.

llvm-svn: 320553
2017-12-13 07:39:35 +00:00
Craig Topper ac59db2efe [Targets] Don't automatically include the scheduler class enum from *GenInstrInfo.inc with GET_INSTRINFO_ENUM. Make targets request is separately.
Most of the targets don't need the scheduler class enum.

I have an X86 scheduler model change that causes some names in the enum to become about 18000 characters long. This is because using instregex in scheduler models causes the scheduler class to get named with every instruction that matches the regex concatenated together. MSVC has a limit of 4096 characters for an identifier name. Rather than trying to come up with way to reduce the name length, I'm just going to sidestep the problem by not including the enum in X86.

llvm-svn: 320552
2017-12-13 07:26:17 +00:00
Serguei Katkov b8cb5da28d [CGP] Enable select in complex addr mode
Enable select instruction handling in complex addr modes.

Reviewers: john.brawn, reames, aaboud
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40634

llvm-svn: 320551
2017-12-13 06:57:59 +00:00
Dean Michael Berris eec462f0e8 [XRay][compiler-rt] Reduce XRay log spam
This change makes XRay print the log file output only when the verbosity
level is higher than 0. It reduces the log spam in the default case when
we want XRay running silently, except when there are actual
fatal/serious errors.

We also update the documentation to show how to get the information
after the change to the default behaviour.

llvm-svn: 320550
2017-12-13 06:37:13 +00:00
Serguei Katkov c80e76cdf5 [NFC] Refactor SafepointIRVerifier
Now two classes are responsible for verification: one of them can track GC
pointers and know whether a pointer is relocated or not and another based on
that information can verify uses of GC pointers.

Patch Author: Daniil Suchkov
Reviewers: mkazantsev, anna, apilipenko
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40885

llvm-svn: 320549
2017-12-13 05:32:46 +00:00
Mohammad Shahid dbd30edb7f [SLP] Vectorize jumbled memory loads.
Summary:
This patch tries to vectorize loads of consecutive memory accesses, accessed
in non-consecutive or jumbled way. An earlier attempt was made with patch D26905
which was reverted back due to some basic issue with representing the 'use mask' of
jumbled accesses.

This patch fixes the mask representation by recording the 'use mask' in the usertree entry.

Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df

Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh

Reviewed By: Ayal

Subscribers: mgrang, dcaballe, hans, mzolotukhin

Differential Revision: https://reviews.llvm.org/D36130

llvm-svn: 320548
2017-12-13 03:08:29 +00:00
Florian Hahn beda7d517d [CallSiteSplitting] Refactor creating callsites.
Summary:
This change makes the call site creation more general if any of the
arguments is predicated on a condition in the call site's predecessors.

If we find a callsite, that potentially can be split, we collect the set
of conditions for the call site's predecessors (currently only 2
predecessors are allowed). To do that, we traverse each predecessor's
predecessors as long as it only has single predecessors and record the
condition, if it is relevant to the call site. For each condition, we
also check if the condition is taken or not. In case it is not taken,
we record the inverse predicate.

We use the recorded conditions to create the new call sites and split
the basic block.

This has 2 benefits: (1) it is slightly easier to see what is going on
(IMO) and (2) we can easily extend it to handle more complex control
flow.

Reviewers: davidxl, junbuml

Reviewed By: junbuml

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D40728

llvm-svn: 320547
2017-12-13 03:05:20 +00:00
Matthias Braun f842297d50 Rename LiveIntervalAnalysis.h to LiveIntervals.h
Headers/Implementation files should be named after the class they
declare/define.

Also eliminated an `#include "llvm/CodeGen/LiveIntervalAnalysis.h"` in
favor of `class LiveIntarvals;`

llvm-svn: 320546
2017-12-13 02:51:04 +00:00
Matthias Braun d9847b114f Remove unnecessary includes; NFC
llvm-svn: 320545
2017-12-13 02:51:01 +00:00
Evgeniy Stepanov ecb48e523e [hwasan] Inline instrumentation & fixed shadow.
Summary: This brings CPU overhead on bzip2 down from 5.5x to 2x.

Reviewers: kcc, alekseyshl

Subscribers: kubamracek, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D41137

llvm-svn: 320538
2017-12-13 01:16:34 +00:00
Michael Trent 1d3d8adad7 reverting out -r320532 because a warning is breaking the lld build
llvm-svn: 320534
2017-12-13 00:36:13 +00:00
Michael Trent 0f6bfaf176 Updated llvm-objdump to display local relocations in Mach-O binaries
Summary:
llvm-objdump's Mach-O parser was updated in r306037 to display external
relocations for MH_KEXT_BUNDLE file types. This change extends the Macho-O
parser to display local relocations for MH_PRELOAD files. When used with
the -macho option relocations will be displayed in a historical format.

rdar://35778019

Reviewers: enderby

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41061

llvm-svn: 320532
2017-12-12 23:53:46 +00:00
Sanjay Patel 3cf695aa38 [EarlyCSE] add tests for commuted min/max; NFC
See PR35642: https://bugs.llvm.org/show_bug.cgi?id=35642

llvm-svn: 320530
2017-12-12 22:23:09 +00:00
Krzysztof Parzyszek 2eda05db87 [Hexagon] Relax some checks in testcases, NFC
llvm-svn: 320529
2017-12-12 21:44:04 +00:00
Alexey Bataev 83c15b1363 [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.

Reviewers: RKSimon, spatel, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320525
2017-12-12 20:28:46 +00:00
Krzysztof Parzyszek edcd9dcbc4 [Hexagon] Better detection of identity and undef masks in shuffles
llvm-svn: 320523
2017-12-12 20:23:12 +00:00
Krzysztof Parzyszek 40a605f1be [Hexagon] Fix wrong order of operands for vmux
Shuffle generation uses vmux to collapse vectors resulting from two
individual shuffles into one. The indexes of the elements selected
from the first operand were indicated by 0xFF in the constant vector
used in the compare instruction, but the compare (veqb) set the bits
corresponding to the 0x00 elements, thus inverting the selection.

Reverse the order of operands to vmux to get the correct output.

llvm-svn: 320516
2017-12-12 19:32:41 +00:00
Fiona Glaser b8a330c42a Reassociate: add global reassociation algorithm
This algorithm (explained more in the source code) takes into account
global redundancies by building a "pair map" to find common subexprs.

The primary motivation of this is to handle situations like

foo = (a * b) * c
bar = (a * d) * c

where we currently don't identify that "a * c" is redundant.

Accordingly, it prioritizes the emission of a * c so that CSE
can remove the redundant calculation later.

Does not change the actual reassociation algorithm -- only the
order in which the reassociated operand chain is reconstructed.

Gives ~1.5% floating point math instruction count reduction on
a large offline suite of graphics shaders.

llvm-svn: 320515
2017-12-12 19:18:02 +00:00
Alexey Bataev fa0a76dbcc Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320510 - again sanitizers bbots.

llvm-svn: 320513
2017-12-12 19:12:34 +00:00
Sanjoy Das 1074eb225b Reapply "[X86] Flag BroadWell scheduler model as complete"
This reverts commit r320508, in effect re-applying r320308.  Simon has already
reverted the parts that caused the crash that motivated the revert in r320492.

llvm-svn: 320512
2017-12-12 19:11:31 +00:00
Hiroshi Yamauchi f3bda1daa2 Split IndirectBr critical edges before PGO gen/use passes.
Summary:
The PGO gen/use passes currently fail with an assert failure if there's a
critical edge whose source is an IndirectBr instruction and that edge
needs to be instrumented.

To avoid this in certain cases, split IndirectBr critical edges in the PGO
gen/use passes. This works for blocks with single indirectbr predecessors,
but not for those with multiple indirectbr predecessors (splitting an
IndirectBr critical edge isn't always possible.)

Reviewers: davidxl, xur

Reviewed By: davidxl

Subscribers: efriedma, llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D40699

llvm-svn: 320511
2017-12-12 19:07:43 +00:00
Alexey Bataev 195c97e220 [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.

Reviewers: RKSimon, spatel, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320510
2017-12-12 18:47:00 +00:00
Sanjoy Das 81a4a02cbc Revert "[X86] Flag BroadWell scheduler model as complete"
This reverts commit r320308.  r320308 crashes LLC, please see the llvm-commits
thread for a reproducer.

llvm-svn: 320508
2017-12-12 18:40:58 +00:00
Craig Topper 712a209db9 [X86] Add a couple TODOs about missing coverage/features motivated by D40335
D40335 was wanting to add FMSUBADD support, but it discovered that there are two pieces of code to make FMADDSUB and only one of those is tested. So I've asked that review to implement the one path until we get tests that test the existing code.

llvm-svn: 320507
2017-12-12 18:39:04 +00:00
Nirav Dave 674d053d18 [X86] Cleanup type conversion of 64-bit load-store pairs.
Summary:
Simplify and generalize chain handling and search for 64-bit load-store pairs.
Nontemporal test now converts 64-bit integer load-store into f64 which it realizes directly instead of splitting into two i32 pairs.

Reviewers: craig.topper, spatel

Reviewed By: craig.topper

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D40918

llvm-svn: 320505
2017-12-12 18:25:48 +00:00
Alexandre Ganea 757026dbe6 Test commit.
llvm-svn: 320504
2017-12-12 18:00:43 +00:00
Geoff Berry 60c431022e [MachineOperand][MIR] Add isRenamable to MachineOperand.
Summary:
Add isRenamable() predicate to MachineOperand.  This predicate can be
used by machine passes after register allocation to determine whether it
is safe to rename a given register operand.  Register operands that
aren't marked as renamable may be required to be assigned their current
register to satisfy constraints that are not captured by the machine
IR (e.g. ABI or ISA constraints).

Reviewers: qcolombet, MatzeB, hfinkel

Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D39400

llvm-svn: 320503
2017-12-12 17:53:59 +00:00
Alexey Bataev 6132a50d2a Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320499 again to resolve the problem with the
sanitizers bbots.

llvm-svn: 320501
2017-12-12 17:35:29 +00:00
Alexey Bataev ca4c9a5246 [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.

Reviewers: RKSimon, spatel, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320499
2017-12-12 17:19:15 +00:00
Alexey Bataev d19dbe6791 Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320496 to solve the problems with sanitizer
buildbots.

llvm-svn: 320498
2017-12-12 17:08:48 +00:00
Don Hinton 49777fa933 [cmake] Support moving debuginfo-tests to llvm/projects
Differential Revision: https://reviews.llvm.org/D40972

llvm-svn: 320497
2017-12-12 17:06:08 +00:00
Alexey Bataev d0c3aeb200 [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.

Reviewers: RKSimon, spatel, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320496
2017-12-12 16:58:48 +00:00
Simon Pilgrim 68f9accf51 [X86] Remove CompleteModel tags from CPU targets until we have better error checking (PR35636)
The checks we have for complete models are not great and miss many cases - e.g. in PR35636 it failed to recognise that only the first output (of 2) was actually tagged by the InstRW

Raised PR35639 and PR35643 as examples

llvm-svn: 320492
2017-12-12 16:12:53 +00:00
Alex Bradbury c01db1ce8f [RISCV][NFC] Formatting fix in RISCVInstrInfo.td
llvm-svn: 320491
2017-12-12 16:10:21 +00:00
Alexey Bataev c9f1d2e4a0 Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320488 because of the failed asan buildbots..

llvm-svn: 320490
2017-12-12 16:05:52 +00:00
Alexey Bataev fb68c48a82 [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.

Reviewers: RKSimon, spatel, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320488
2017-12-12 15:54:49 +00:00
Alex Bradbury 9ed84c8ae8 [RISCV] Implement assembler pseudo instructions for RV32I and RV64I
Adds the assembler pseudo instructions of RV32I and RV64I which can
be mapped to a single canonical instruction. The missing pseudo
instructions (e.g., call, tail, ...) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

Currently, alias emission is disabled by default to keep the patch
minimal. Alias emission by default will be enabled in a subsequent
patch which also updates all affected tests. Note that this patch
should actually break the floating point MC tests. However, the
used FileCheck configuration is not tight enought to detect the
breakage.

Differential Revision: https://reviews.llvm.org/D40902

Patch by Mario Werner.

llvm-svn: 320487
2017-12-12 15:46:15 +00:00
Alexey Bataev ca2a8cea2f Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320483 because of the failed Windows buildbots.

llvm-svn: 320485
2017-12-12 15:24:17 +00:00
Alex Bradbury 8bba6bfeef [RISCV] MC layer support for the instructions added in the privileged spec
Adds support for the instructions added in the RISC-V privileged ISA
(https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf):
uret, sret, mret, wfi, and sfence.vma.

Note from the committer: I made very minor formatting changes prior to commit, 
which didn't seem worth creating another review round-trip for.

Differential Revision: https://reviews.llvm.org/D40383

Patch by David Craven.

llvm-svn: 320484
2017-12-12 15:17:45 +00:00
Alexey Bataev 1daef8a667 [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.

Reviewers: RKSimon, spatel, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320483
2017-12-12 15:03:17 +00:00
Ayman Musa c2eed926b0 [X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction.
Recognize constant arrays with the following values:
  0x0, 0x1, 0x3, 0x7, 0xF, 0x1F, .... , 2^(size - 1) -1
where //size// is the size of the array.

the result of a load with index //idx// from this array is equivalent to the result of the following:
  (0xFFFFFFFF >> (sub 32, idx))             (assuming the array of type 32-bit integer).

And the result of an 'AND' operation on the returned value of such a load and another input, is exactly equivalent to the X86 BZHI instruction behavior.

See test cases in the LIT test for better understanding.

Differential Revision: https://reviews.llvm.org/D34141

llvm-svn: 320481
2017-12-12 14:13:51 +00:00
Anna Thomas 2dd9835f35 [InstComineLoadStoreAlloca] Optimize stores to GEP off null base
Summary:
Currently, in InstCombineLoadStoreAlloca, we have simplification
rules for the following cases:
  1. load off a null
  2. load off a GEP with null base
  3. store to a null

This patch adds support for the fourth case which is store into a
GEP with null base. Since this is UB as well (and directly analogous to
the load off a GEP with null base), we can substitute the stored val
with undef in instcombine, so that SimplifyCFG can optimize this code
into unreachable code.

Note: Right now, simplifyCFG hasn't been taught about optimizing
this to unreachable and adding an llvm.trap (this is already done for
the above 3 cases).

Reviewers: majnemer, hfinkel, sanjoy, davide

Reviewed by: sanjoy, davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41026

llvm-svn: 320480
2017-12-12 14:12:33 +00:00
Nemanja Ivanovic 6479c72fcd [PowerPC] Add branch flag on asm parser-only branch instructions
This flag was missing but it wasn't an issue as nothing depended on it
for these asm parser-only instructions. Now that LLDB support is slowly
landing, it is important to get this right.
Committing on behalf of Leonardo Bianconi.

Differential revision: https://reviews.llvm.org/D40846

llvm-svn: 320475
2017-12-12 12:33:09 +00:00
Nemanja Ivanovic b0783cccb7 [PowerPC] Follow-up to r318436 to get the missed CSE opportunities
The last of the three patches that https://reviews.llvm.org/D40348 was
broken up into.
Canonicalize the materialization of constants so that they are more likely
to be CSE'd regardless of the bit-width of the use. If a constant can be
materialized using PPC::LI, materialize it the same way always.
For example:
  li 4, -1
  li 4, 255
  li 4, 65535
are equivalent if the uses only use the low byte. Canonicalize it to the
first form.

Differential Revision: https://reviews.llvm.org/D40348

llvm-svn: 320473
2017-12-12 12:09:34 +00:00
Simon Pilgrim 0f8a5a41cf Revert r320461 - causing ICE in windows buildss
[X86] Use regular expressions more aggressively to reduce the number of scheduler entries needed for FMA3 instructions.

When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models.

This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do.

llvm-svn: 320470
2017-12-12 11:34:25 +00:00
Jonas Devlieghere f0945f48bd [dsymutil] Accept line tables up to DWARFv5.
This patch removes the hard-coded check for DWARFv2 line tables. Now
dsymutil accepts line tables for DWARF versions 2 to 5 (inclusive).

Differential revision: https://reviews.llvm.org/D41084

rdar://35968319

llvm-svn: 320469
2017-12-12 11:32:21 +00:00
Eugene Leviant d53f3da772 Revert r320464 as it breaks gold plugin tests
llvm-svn: 320467
2017-12-12 10:12:46 +00:00
Igor Laevsky d63560b817 Revert r320049, r320014 and r319894
They were causing failures of the piglit OpenGL tests with AMD GPUs using the
Mesa radeonsi driver.

llvm-svn: 320466
2017-12-12 10:03:39 +00:00
Serguei Katkov f4ceb77cd9 [NFC][SafepointIRVerifier] Add alias for set of available values
Introduces usage of AvailableValueSet alias name instead of
DenseSet<const Value *> for better reading.

Patch Author: Daniil Suchkov
Reviewers: mkazantsev, anna, apilipenko
Reviewed By: anna
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41002

llvm-svn: 320465
2017-12-12 09:44:41 +00:00
Eugene Leviant 3695183395 [ThinLTO] Remove unused code from thinLTOInternalizeModule
Differential revision: https://reviews.llvm.org/D40970

llvm-svn: 320464
2017-12-12 09:12:32 +00:00
Dorit Nuzman 927b31600e [LV] Ignore the cost of values that will not appear in the vectorized loop
VecValuesToIgnore holds values that will not appear in the vectorized loop.
We should therefore ignore their cost when VF > 1.

Differential Revision: https://reviews.llvm.org/D40883

llvm-svn: 320463
2017-12-12 08:57:43 +00:00
Craig Topper c8e64ab539 [X86] Use regular expressions more aggressively to reduce the number of scheduler entries needed for FMA3 instructions.
When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models.

This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do.

llvm-svn: 320461
2017-12-12 08:17:04 +00:00
Mikael Holmen 66cf383761 [CallSiteSplitting] Don't let debug intrinsics affect optimizations
Summary:
This solves PR35616.

We don't want the compiler to generate different code when we compile
with/without -g, so we now ignore debug intrinsics when determining if
the optimization can trigger or not.

Reviewers: junbuml

Subscribers: davide, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D41068

llvm-svn: 320460
2017-12-12 07:29:57 +00:00
Craig Topper 468a813315 [X86] Use Ld scheduler classes for instructions with folded loads.
llvm-svn: 320459
2017-12-12 07:06:35 +00:00
Craig Topper c1e72c019d [X86] Correct the FMA3 regular expressions in the znver1 scheduler model.
llvm-svn: 320458
2017-12-12 07:06:32 +00:00
Tony Tye a697880b38 [AMDGPU] Rename Bonaire target to be gfx704; remove gfx800 and make Iceland and Tonga both use gfx802; update target feature handling
Correct committed version to match intended accepted review D40051 id=123417

- Rename Bonaire target to be gfx704.
- Eliminate gfx800 and make Iceland and Tonga both use gfx802 as they use the same code.
- List target features supported by each processor in the processor table together with the default value.
- Add xnack flag to e_flags.
- Remove xnack from kernel metadata and kernel descriptor since it is now a whole code object property.

Differential Revision: https://reviews.llvm.org/D40051

llvm-svn: 320457
2017-12-12 05:47:00 +00:00
Vedant Kumar 7a911b5851 [llvm-cov] Simplify a test case. NFC.
llvm-svn: 320439
2017-12-11 23:34:50 +00:00
Max Moroz fe4d904917 [llvm-cov] Add an option for "export" command to emit only file summary data.
Summary:
That allows to get the same data as produced by "llvm-cov report",
but in JSON format, which is better for further processing by end users.

Reviewers: vsk

Reviewed By: vsk

Differential Revision: https://reviews.llvm.org/D41085

llvm-svn: 320435
2017-12-11 23:17:46 +00:00
Sam Clegg f950b24a7a Reland "[WebAssembly] Import the linear memory and function table."
Original change: https://reviews.llvm.org/D40875

llvm-svn: 320432
2017-12-11 23:03:38 +00:00
Richard Trieu efef032f02 Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion
See bug https://bugs.llvm.org/show_bug.cgi?id=35631
r318704 is giving a fatal error on some code with unsigned to floating point
conversions.

llvm-svn: 320429
2017-12-11 22:25:04 +00:00
Matt Arsenault 3e268cc0dd LSR: Check more intrinsic pointer operands
llvm-svn: 320424
2017-12-11 21:38:43 +00:00
Hans Wennborg 27d1c00c01 Revert r320407 "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
The tests fail (opt asserts) on Windows.

> Summary:
> If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
> &V2)))), bitcast)`, but the load is used in other instructions, it leads
> to looping in InstCombiner. Patch adds additional check that all users
> of the load instructions are stores and then replaces all uses of load
> instruction by the new one with new type.
>
> Reviewers: RKSimon, spatel, majnemer
>
> Subscribers: llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320421
2017-12-11 21:15:27 +00:00
Evandro Menezes 54be62df39 [CodeGen] Improve the consistency of instruction fusion*
When either instruction in a fused pair has no other dependency, besides on
the other instruction, make sure that other instructions do not get
scheduled between them.  Additionally, avoid fusing an instruction more than
once along the same dependency chain.

Differential revision: https://reviews.llvm.org/D36704

llvm-svn: 320420
2017-12-11 21:09:27 +00:00
Adrian Prantl 3c6c14d14b ASAN: Provide reliable debug info for local variables at -O0.
The function stack poisioner conditionally stores local variables
either in an alloca or in malloc'ated memory, which has the
unfortunate side-effect, that the actual address of the variable is
only materialized when the variable is accessed, which means that
those variables are mostly invisible to the debugger even when
compiling without optimizations.

This patch stores the address of the local stack base into an alloca,
which can be referred to by the debug info and is available throughout
the function. This adds one extra pointer-sized alloca to each stack
frame (but mem2reg can optimize it away again when optimizations are
enabled, yielding roughly the same debug info quality as before in
optimized code).

rdar://problem/30433661

Differential Revision: https://reviews.llvm.org/D41034

llvm-svn: 320415
2017-12-11 20:43:21 +00:00
Tony Jiang 3b49dc548f [PowerPC] Partially enable the ISEL expansion pass.
The pass to expand ISEL instructions into if-then-else sequences in patch D23630
is currently disabled. This patch partially enable it by always removing the
unnecessary ISELs (all registers used by the ISELs are the same one) and folding
the ISELs which have the same input registers into unconditional copies.

Differential Revision: https://reviews.llvm.org/D40497

llvm-svn: 320414
2017-12-11 20:42:37 +00:00
Justin Bogner b608076e56 [cmake] Pass TARGETS_TO_BUILD through to host tools build
In r319620, the host build was changed to use Native for
TARGETS_TO_BUILD because passing semicolons through add_custom_command
is surprisingly difficult. However, Native really doesn't make any
sense here, and it only works because we don't technically do any
codegen in the host tools so pretty well anything will "work".

The problem here is that passing something other than the correct
value is very fragile - as evidence note how the llvm-config in the
host tools acts differently than the target one now, and misreports
the targets to build. Similarly, if there is any logic conditional on
the targets in tablegen (now or in the future), it will do the wrong
thing.

To fix this, we need to escape the semicolons in the targets string
and pass it through to the child cmake invocation.

llvm-svn: 320413
2017-12-11 19:53:23 +00:00
George Burgess IV 8c5886b45f Ensure moved-from container is cleared on move
In all cases except for this optimistic attempt to reuse memory, the
moved-from TinyPtrVector was left `empty()` at the end of this
assignment. Though using a container after it's been moved from can be a
bit sketchy, it's probably best to just be consistent here.

llvm-svn: 320408
2017-12-11 19:22:59 +00:00
Alexey Bataev ec128ace8a [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.

Reviewers: RKSimon, spatel, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41072

llvm-svn: 320407
2017-12-11 19:11:16 +00:00
Krzysztof Parzyszek a8ab1b75cb [Hexagon] Add support for Hexagon V65
llvm-svn: 320404
2017-12-11 18:57:54 +00:00
Simon Pilgrim e83876e31d [X86] Add LODS schedule tests
llvm-svn: 320403
2017-12-11 18:39:42 +00:00
Simon Pilgrim e8715025f5 [X86] Add CMP/TEST schedule tests
llvm-svn: 320402
2017-12-11 18:32:59 +00:00
Simon Pilgrim 5512525c5d [X86] Add AND/OR/XOR schedule tests
llvm-svn: 320400
2017-12-11 18:23:24 +00:00
Jonas Devlieghere ba915897da [dwarfdump] Fix off-by-one bug in accelerator table extractor.
This fixes a bug where the verifier was complaining about empty
accelerator tables. When the table is empty, its size is not a valid
offset as it points after the end of the section.

This patch also makes the extractor return llvm:Error instead of bool
for better error reporting in the verifier.

Differential revision: https://reviews.llvm.org/D41063

rdar://35932007

llvm-svn: 320399
2017-12-11 18:22:47 +00:00
Simon Pilgrim 9b2a5e1e0b [X86] Add ADD/SUB schedule tests
llvm-svn: 320397
2017-12-11 18:13:40 +00:00
Simon Pilgrim dbe6c45fcd [X86] Add ADC/SBB schedule tests
llvm-svn: 320395
2017-12-11 17:59:05 +00:00
Simon Pilgrim 8c2d90a2f4 [X86] Add MOVSLQ schedule tests
llvm-svn: 320392
2017-12-11 17:37:08 +00:00
Simon Pilgrim 6d89f407db Normalize line endings. NFCI.
llvm-svn: 320389
2017-12-11 17:01:21 +00:00
Amara Emerson df9b529d42 [GlobalISel] Disable GISel for big endian.
This is due to PR26161 needing to be resolved before we can fix
big endian bugs like PR35359. The work to split aggregates into smaller LLTs
instead of using one large scalar will take some time, so in the mean time
we'll fall back to SDAG.

Some ARM BE tests xfailed for now as a result.

Differential Revision: https://reviews.llvm.org/D40789

llvm-svn: 320388
2017-12-11 16:58:29 +00:00
Simon Pilgrim fabe354b42 [X86] Add LWP schedule tests
Tag LWP instructions as WriteSystem

llvm-svn: 320387
2017-12-11 16:47:21 +00:00
Simon Pilgrim 67644be692 [X86] Add INT/INTO schedule tests
llvm-svn: 320386
2017-12-11 16:32:58 +00:00
Simon Pilgrim 1fe82016a2 [X86] Add IN/OUT schedule tests
llvm-svn: 320385
2017-12-11 16:16:40 +00:00
Simon Pilgrim d0ce975528 [X86] Add IDIV schedule tests
llvm-svn: 320384
2017-12-11 16:08:21 +00:00
Simon Pilgrim 6c29962f2e [X86] Add CMPXCHG schedule tests
llvm-svn: 320383
2017-12-11 16:04:08 +00:00
Simon Pilgrim 1c83cd18ae [X86] Add CLZERO schedule test
llvm-svn: 320382
2017-12-11 15:53:12 +00:00
Alexander Potapenko 3c934e4864 [MSan] Hotfix compilation
For some reason the override directives got removed in r320373.
I suspect this to be an unwanted effect of clang-format.

llvm-svn: 320381
2017-12-11 15:48:56 +00:00
Simon Pilgrim d9d37f8c3c [X86] Add ADCX/ADOX/XADD/XLAT schedule tests
llvm-svn: 320380
2017-12-11 15:41:52 +00:00
Nirav Dave e830b758b8 [X86] Modify Nontemporal tests to avoid deadstore optimization.
llvm-svn: 320379
2017-12-11 15:35:40 +00:00
Tony Tye 31105cc997 [AMDGPU] Rename Bonaire target to be gfx704; update target feature handling
- Rename Bonaire target to be gfx704.
- Eliminate gfx800 and make Iceland and Tonga both use gfx802 as they use the same code.
- List target features supported by each processor in the processor table together with the default value.
- Add xnack flag to e_flags.
- Remove xnack from kernel metadata and kernel descriptor since it is now a whole code object property.

Differential Revision: https://reviews.llvm.org/D40051

llvm-svn: 320378
2017-12-11 15:35:27 +00:00
Simon Pilgrim 4f2c415a13 [X86] Add SETCC/STC/STD/UD2 schedule tests
llvm-svn: 320376
2017-12-11 15:25:31 +00:00
Dmitry Preobrazhensky ac2b02643b [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma
See bugs 35494 and 35559:
https://bugs.llvm.org/show_bug.cgi?id=35494
https://bugs.llvm.org/show_bug.cgi?id=35559

Reviewers: vpykhtin, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41007

llvm-svn: 320375
2017-12-11 15:23:20 +00:00
Sanjay Patel f3436d7dab [DAGCombiner] protect against an infinite loop between shl <--> mul (PR35579)
At first, I tried to thread the x86 needle and use a target hook (isVectorShiftByScalarCheap())
to disable the transform only for non-splat pow-of-2 constants, but not AVX2, but only some
element types, but...it's difficult.

Here we just avoid the loop with the x86 vector transform that conflicts with the general DAG
combine and preserve all of the existing behavior AFAICT otherwise.

Some tests that will probably fail if someone does try to restrict this in a more targeted way
for x86-only may be found in:

test/CodeGen/X86/combine-mul.ll
test/CodeGen/X86/vector-mul.ll
test/CodeGen/X86/widen_arith-5.ll

This should prevent the infinite looping seen with:
https://bugs.llvm.org/show_bug.cgi?id=35579

Differential Revision: https://reviews.llvm.org/D41040

llvm-svn: 320374
2017-12-11 15:19:31 +00:00
Alexander Potapenko c07e6a0eff [MSan] introduce getShadowOriginPtr(). NFC.
This patch introduces getShadowOriginPtr(), a method that obtains both the shadow and origin pointers for an address as a Value pair.
The existing callers of getShadowPtr() and getOriginPtr() are updated to use getShadowOriginPtr().

The rationale for this change is to simplify KMSAN instrumentation implementation.
In KMSAN origins tracking is always enabled, and there's no direct mapping between the app memory and the shadow/origin pages.
Both the shadow and the origin pointer for a given address are obtained by calling a single runtime hook from the instrumentation,
therefore it's easier to work with those pointers together.

Reviewed at https://reviews.llvm.org/D40835.

llvm-svn: 320373
2017-12-11 15:05:22 +00:00
Simon Pilgrim 5154d249a8 [X86] Add SAR/SHL/SHR schedule tests
llvm-svn: 320371
2017-12-11 14:56:44 +00:00
Simon Pilgrim 426add6915 [X86] Add RCL/RCR schedule tests
llvm-svn: 320370
2017-12-11 14:46:42 +00:00
Krzysztof Parzyszek 152414595b [Hexagon] Crash in instruction selection for insert_vector_elt for HVX
A wrong type was passed to insertVector, causing an out-of-bounds value
to be added an an operand to HexagonISD::INSERT. This later failed in
instruction selection.

llvm-svn: 320369
2017-12-11 14:46:06 +00:00
Nemanja Ivanovic 50d37a1129 [PowerPC] Sign-extend negative constant stores
Second part of https://reviews.llvm.org/D40348.
Revision r318436 has extended all constants feeding a store to 64 bits
to allow for CSE on the SDAG. However, negative constants were zero extended
which made the constant being loaded appear to be a positive value larger than
16 bits. This resulted in long sequences to materialize such constants
rather than simply a "load immediate". This patch just sign-extends those
updated constants so that they remain 16-bit signed immediates if they started
out that way.

llvm-svn: 320368
2017-12-11 14:35:48 +00:00
Nemanja Ivanovic 25d9af0cb5 [DAGCombiner] Add combined indexed load to the work list
This commit is the first part of https://reviews.llvm.org/D40348.
In order to allow target combines to be performed on newly combined
indexed loads, add them back to the worklist. The remainder of the
above patch will be committed in subsequent revisions and will use
this. Test cases will be included with those follow-up commits.

llvm-svn: 320365
2017-12-11 14:16:02 +00:00
Diana Picus 291e8d924f [ARM GlobalISel] Add test for a MOVTi16 pattern. NFC
Add test for matching an OR with 0xFFFF0000 to a MOVTi16.

llvm-svn: 320362
2017-12-11 13:28:45 +00:00
Simon Pilgrim 969850f514 [X86] Add fsgsbase schedule tests.
llvm-svn: 320361
2017-12-11 13:25:02 +00:00
Alex Bradbury dc31c61b18 [RISCV] Add custom CC_RISCV calling convention and improved call support
The TableGen-based calling convention definitions are inflexible, while
writing a function to implement the calling convention is very
straight-forward, and allows difficult cases to be handled more easily. With
this patch adds support for:
* Passing large scalars according to the RV32I calling convention
* Byval arguments
* Passing values on the stack when the argument registers are exhausted

The custom CC_RISCV calling convention is also used for returns.

This patch also documents the ABI lowering that a language frontend is 
expected to perform. I would like to work to simplify these requirements over 
time, but this will require further discussion within the LLVM community.

We add PendingArgFlags CCState, as a companion to PendingLocs.

The PendingLocs vector is used by a number of backends to handle arguments 
that are split during legalisation. However CCValAssign doesn't keep track of 
the original argument alignment. Therefore, add a PendingArgFlags vector which 
can be used to keep track of the ISD::ArgFlagsTy for every value added to 
PendingLocs.

Differential Revision: https://reviews.llvm.org/D39898

llvm-svn: 320359
2017-12-11 12:49:02 +00:00
Alex Bradbury bfb00d4c1c [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestore
llvm-svn: 320358
2017-12-11 12:38:17 +00:00
Alex Bradbury b014e3de52 [RISCV] Implement prolog and epilog insertion
As frame pointer elimination isn't implemented until a later patch and we make 
extensive use of update_llc_test_checks.py, this changes touches a lot of the 
RISC-V tests.

Differential Revision: https://reviews.llvm.org/D39849

llvm-svn: 320357
2017-12-11 12:34:11 +00:00
Simon Pilgrim 220b1c13bf [X86] Regenerate fsgsbase intrinsic tests. NFCI.
llvm-svn: 320356
2017-12-11 12:22:15 +00:00
Roger Ferrer Ibanez 5ea0f2501f [ARM] Use ADDCARRY / SUBCARRY
This is a preparatory step for D34515.

This change:
 - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32
 - lowering is done by first converting the boolean value into the carry flag
   using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value
   using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two
   operations does the actual addition.
 - for subtraction, given that ISD::SUBCARRY second result is actually a
   borrow, we need to invert the value of the second operand and result before
   and after using ARMISD::SUBE. We need to invert the carry result of
   ARMISD::SUBE to preserve the semantics.
 - given that the generic combiner may lower ISD::ADDCARRY and
   ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering
   as well otherwise i64 operations now would require branches. This implies
   updating the corresponding test for unsigned.
 - add new combiner to remove the redundant conversions from/to carry flags
   to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C
 - fixes PR34045
 - fixes PR34564
 - fixes PR35103

Differential Revision: https://reviews.llvm.org/D35192

llvm-svn: 320355
2017-12-11 12:13:45 +00:00
Alex Bradbury 660bcceccf [RISCV] Support lowering FrameIndex
Introduces the AddrFI "addressing mode", which is necessary simply because 
it's not possible to write a pattern that directly matches a frameindex.

Ensure callee-saved registers are accessed relative to the stackpointer. This
is necessary as callee-saved register spills are performed before the frame
pointer is set.

Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can 
make use of it in the RISC-V backend.

Differential Revision: https://reviews.llvm.org/D39848

llvm-svn: 320353
2017-12-11 11:53:54 +00:00
Diana Picus 775bb74379 [ARM GlobalISel] Add tests for PKHBT and PKHTB
Test (some of) the patterns for selecting PKHBT and PKHTB. The others
are just very similar to the ones we're testing and there would be
little value in covering them as well.

llvm-svn: 320352
2017-12-11 11:44:23 +00:00
Aleksandar Beserminji d6dada17ff [mips] Removal of microMIPS64R6
All files and parts of files related to microMIPS4R6 are removed.
When target is microMIPS4R6, errors are printed.

This is LLVM part of patch.

Differential Revision: https://reviews.llvm.org/D35625

llvm-svn: 320350
2017-12-11 11:21:40 +00:00
Dylan McKay 2124bcf805 [AVR] Implement some missing code paths
This has been broken since r320009.

llvm-svn: 320348
2017-12-11 11:01:27 +00:00
Dylan McKay ab6204b1e5 [AVR] Fix incorrectly-calculated AVRMCExpr evaluations
This has been broken since r320009.

llvm-svn: 320347
2017-12-11 11:01:19 +00:00
Craig Topper ad45bf5895 [DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors.
We should probably also fold (mulhs/u X, 1) for vectors, but that's harder.

llvm-svn: 320344
2017-12-11 08:33:20 +00:00
Craig Topper 65ed4d4492 [DAGCombiner] Reuse existing SDLoc variable instead of creating a new one. NFC
llvm-svn: 320343
2017-12-11 08:33:19 +00:00
Craig Topper 0bea09b737 [X86] Regenerate test with update_llc_test_checks.py
llvm-svn: 320342
2017-12-11 06:16:26 +00:00
Craig Topper 1e83485613 [X86] Add a test case for masked scatter where the index needs to be legalized from v2i32 while other types are legal.
llvm-svn: 320340
2017-12-11 01:48:10 +00:00
Simon Pilgrim 6b1f532ccf [X86] Add ROL/ROR schedule tests
llvm-svn: 320334
2017-12-10 22:11:56 +00:00
Simon Pilgrim a6564e2358 [X86] Add DIV/MUL/NEG/NOP/NOT/PAUSE schedule tests
llvm-svn: 320333
2017-12-10 21:56:24 +00:00
Simon Pilgrim 8e6d0fcbac [X86] Add DEC/INC schedule tests
Include i686 (non-REX) variant tests as well

llvm-svn: 320332
2017-12-10 21:28:00 +00:00
Simon Pilgrim f1c51d187a [X86] Add INS/OUTS schedule tests
llvm-svn: 320331
2017-12-10 21:10:28 +00:00
Simon Pilgrim 07ebbd53f0 [X86] Add CMPS/MOVS/SCAS/STOS schedule tests
llvm-svn: 320330
2017-12-10 20:58:22 +00:00
Simon Pilgrim f65831d731 [X86] Add CMOV schedule tests
llvm-svn: 320329
2017-12-10 20:46:57 +00:00
Simon Pilgrim 4a431edddc [X86] Add BT/BTC/BTR/BTS schedule tests
llvm-svn: 320328
2017-12-10 20:22:47 +00:00
Craig Topper c6a4a97260 [X86] Add VCOMISDZrr, VCOMISSZrr, VUCOMISDZrr, and VUCOMISSZrr to the skylake server sheduler model
llvm-svn: 320326
2017-12-10 19:47:57 +00:00
Craig Topper a0be5a06c1 [X86] Rename some instructions that start with Int_ to have the _Int at the end.
This matches AVX512 version and is more consistent overall. And improves our scheduler models.

In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses.

llvm-svn: 320325
2017-12-10 19:47:56 +00:00
Simon Pilgrim c493d4f5b9 [X86][X87] Fix typo in znver1 FIST/FISTT schedule patterns
llvm-svn: 320322
2017-12-10 19:19:22 +00:00
Simon Pilgrim 930e435937 [X86][X87] Add missing x87 scheduler tests
Split off some 'n' instruction versions to make it clearer when WAIT is being inserted

llvm-svn: 320321
2017-12-10 18:53:15 +00:00
Craig Topper 1de942b2d1 [X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper suffix. Fix the scheduling information for some of them.
Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)'

llvm-svn: 320320
2017-12-10 17:42:44 +00:00
Craig Topper c7445f2cdc [X86] Add VCVTQQ2PS to the skylake server scheduler models.
llvm-svn: 320319
2017-12-10 17:42:43 +00:00
Craig Topper c268527b2f [X86] Add VPMULLWZ256 to the skylake server scheduler model
llvm-svn: 320318
2017-12-10 17:42:42 +00:00
Craig Topper 4ec397cbd3 [X86] Add 256/512-bit EVEX VPSADBW instructions to skylake server scheduler model.
llvm-svn: 320317
2017-12-10 17:42:41 +00:00
Craig Topper aa904d5ab6 [X86] Fix a few instructions that were named Z512 instead of just Z.
This makes things consistent with our normal instruction naming.

llvm-svn: 320316
2017-12-10 17:42:39 +00:00
Craig Topper 7c89de1760 [X86] Add VPSRLWZrr to skylake server scheduler model.
llvm-svn: 320315
2017-12-10 17:42:38 +00:00
Craig Topper 1d7760db49 [X86] Add VPUNPCKLWDZrr to skylake server scheduler model.
llvm-svn: 320314
2017-12-10 17:42:37 +00:00
Craig Topper 57c2815cbe [X86] Adjust tablegen includes so we can use Instructions in scheduler models instead of just instregexs.
This separates the CPU specific scheduler model includes to occur after the instructions. Moves the instruction includes between the basic scheduler information and the CPU specific scheduler models.

llvm-svn: 320313
2017-12-10 17:42:36 +00:00
Sanjay Patel b23e148114 [SimplifyLibCalls] propagate FMF when folding pow(x, -1.0) call
Follow-up for a bug that's similar to:
https://bugs.llvm.org/show_bug.cgi?id=35601

llvm-svn: 320312
2017-12-10 17:25:54 +00:00
Sanjay Patel ac9cbd6c56 [InstCombine] add test for pow(x, -1.0) with FMF; NFC
llvm-svn: 320311
2017-12-10 17:21:51 +00:00
Sanjay Patel 09ec34349a [SimplifyLibCalls] propagate FMF when folding pow(x, 2.0) call (PR35601)
This should fix the larger problem with sqrt shown in:
https://bugs.llvm.org/show_bug.cgi?id=35601

llvm-svn: 320310
2017-12-10 16:52:26 +00:00
Sanjay Patel 719bc64ba5 [InstCombine] add test for pow(x, 2.0) with FMF; NFC
llvm-svn: 320309
2017-12-10 16:43:34 +00:00
Simon Pilgrim 1f8cfba0bb [X86] Flag BroadWell scheduler model as complete
Locally tag COPY as WriteMove, which has caused some reg-reg + reg-mem instruction tests to reorder.

llvm-svn: 320308
2017-12-10 13:49:51 +00:00
Simon Pilgrim 4ff43d8120 Regenerate some AVX2+ scheduling tests that got missed
llvm-svn: 320307
2017-12-10 13:41:29 +00:00
Simon Pilgrim 49c74934dd Strip trailing whitespace. NFCI.
llvm-svn: 320306
2017-12-10 13:00:37 +00:00
Simon Pilgrim af35b76bda Regenerate some scheduling tests that got missed
llvm-svn: 320305
2017-12-10 12:59:55 +00:00
Simon Pilgrim 320996576d [X86] Flag ZNVER1 scheduler model as complete
We just have to locally tag COPY as WriteMove

llvm-svn: 320304
2017-12-10 12:43:53 +00:00
Simon Pilgrim 8547645948 [X86] Flag SLM scheduler model as complete
We just have to locally tag COPY as WriteMove

llvm-svn: 320303
2017-12-10 12:36:29 +00:00
Simon Pilgrim 91c159d841 [X86][AVX[ Tag VZEROALL/VZEROUPPER instructions scheduler classes
llvm-svn: 320302
2017-12-10 12:26:35 +00:00
Simon Pilgrim 6de94a1adc [X86] Tag SSE4A instructions as SSE INTALU scheduler classes
llvm-svn: 320301
2017-12-10 12:08:04 +00:00
Simon Pilgrim cd58171110 [X86] Flag BTVER2 scheduler model as complete
We just have to locally tag COPY as WriteMove

llvm-svn: 320300
2017-12-10 11:51:29 +00:00
Simon Pilgrim b7fb2e2fa1 [X86] Tag ADJSTACK instructions as INTALU scheduler class
llvm-svn: 320299
2017-12-10 11:34:08 +00:00
Dorit Nuzman 5809e70540 [SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCasts
CreateAddRecFromPHIWithCastsImpl() adds an IncrementNUSW overflow predicate
which allows the PSCEV rewriter to rewrite this scev expression:
 (zext i8 {0, + , (trunc i32 step to i8)} to i32)
into
 {0, +, (sext i8 (trunc i32 step to i8) to i32)}

But then it adds the wrong Equal predicate:
 %step == (zext i8 (trunc i32 %step to i8) to i32).
instead of:
 %step == (sext i8 (trunc i32 %step to i8) to i32)

This is fixed here.

Differential Revision: https://reviews.llvm.org/D40641

llvm-svn: 320298
2017-12-10 11:13:35 +00:00
Simon Pilgrim 1a030016a6 [X86] Tag MORESTACK instructions as ret scheduler class
llvm-svn: 320296
2017-12-10 10:08:21 +00:00
Craig Topper 253562eb81 [X86] Fix duplicate entries in skylake server scheduler model by changing Z128 to Z256
Based on the fact that the 'Y' version of the instruction is next to this, I assume Z256 is the intended value.

llvm-svn: 320295
2017-12-10 09:14:45 +00:00
Craig Topper 90c9c15936 [X86] Add MOVQI2PQIrm, MOVSDmr, and MOVSDrm to scheduler information
The VEX versions were present but not the legacy SSE versions.

llvm-svn: 320294
2017-12-10 09:14:44 +00:00
Craig Topper 28e55386ac [X86] Add LEA64_32r to scheduler models for Sandybridge,Haswell,Broadwell,Skylake
llvm-svn: 320293
2017-12-10 09:14:42 +00:00
Craig Topper 8ade4640f3 [X86] Add IN16/OUT16 to scheduling information for Haswell,Broadwell,Skylake
Sandy Bridge is also missing it, but it has other issues. See PR35590.

llvm-svn: 320292
2017-12-10 09:14:41 +00:00
Craig Topper 1a88c50fd7 [X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. Similar for all sizes of AND/OR/XOR/SUB/ADC/SBB/CMP.
llvm-svn: 320291
2017-12-10 09:14:39 +00:00
Craig Topper c89e282f7d [X86] Rename some instructions so that 'b' is added as a suffix instead of replacing an 'r'
llvm-svn: 320290
2017-12-10 09:14:38 +00:00
Craig Topper 6c65910160 [X86] Add CMPSDrr/rm to the scheduler models.
Somehow CMPSSrr/rm was there and the VEX version was there, but this was consistently missing.

llvm-svn: 320289
2017-12-10 09:14:37 +00:00
Craig Topper d435a1950f [Docs] Fix typo in scheduler model documentation. enumemation->enumeration
llvm-svn: 320288
2017-12-10 09:14:35 +00:00
Tim Northover cf4701bb89 PowerPC: support external pid instructions in MC layer.
This adds assembly & disassembly support for the e500mc "external pid"
instructions.

See https://reviews.llvm.org/D39249.

Patch by vit9696 <vit9696@avp.su>

llvm-svn: 320287
2017-12-10 08:43:19 +00:00
Xinliang David Li fa3f1a15b2 [PGO] change arg type to uint64_t to match member field type
llvm-svn: 320285
2017-12-10 07:39:53 +00:00
Craig Topper da7e78e18c [X86] Rename the rb form of scalar ADD/SUB/MUL/DIV to include _Int since they can only be selected by intrinsics.
llvm-svn: 320283
2017-12-10 04:07:28 +00:00
Craig Topper 4e57776fb2 [X86] Correct the _Int part of more scheduler model instrexes. Put _b in the correct order relative to _Int
llvm-svn: 320282
2017-12-10 03:16:38 +00:00
Craig Topper a2f5528084 [X86] Remove ReadAfterLd from several several rb instructions
This affects CVTSD2SS, FMA, RCP28, RSQRT28, and SQRT scalar instructions

'b' here refers to 'sae' not broadcast. These aren't memory instructions.

llvm-svn: 320281
2017-12-10 03:16:36 +00:00
Craig Topper 29868dcbaa [X86] Fix test case I failed ot update in r320279.
llvm-svn: 320280
2017-12-10 01:27:54 +00:00
Craig Topper 391c6f9507 [X86] Fix bad regular expressions in the scheduler models. Question marks should be outside of multicharacter parenthesized expressions
If the question mark is inside the parentheses it only applies to the single character proceeding it.

I had to make a few additional cleanups to fix some duplicate warnings that were exposed by fixing this.

llvm-svn: 320279
2017-12-10 01:24:08 +00:00
Craig Topper 8ee98d0b51 [X86] Make the _Int part of some instregex sheduler patterns optional
llvm-svn: 320278
2017-12-10 01:24:06 +00:00
Craig Topper 5ffe80103e [X86] Add the commutable floating point min/max pseudo instructions to sandybridge,haswell,broadwell,skylakeclient scheduler models.
llvm-svn: 320277
2017-12-10 01:24:05 +00:00
Simon Pilgrim 6655eef1b4 [X86] Tag PIC setup instruction as jump scheduler class
llvm-svn: 320276
2017-12-10 00:40:37 +00:00
Simon Pilgrim 5d74949e5f [X86] Tag ACQUIRE/RELEASE atomic instructions as microcoded scheduler classes
Note: We may be too pessimistic here and should possibly use something closer to the LOCK arithmetic instructions
llvm-svn: 320275
2017-12-10 00:30:57 +00:00
Simon Pilgrim dcbe723d28 [X86] Tag TLS instructions as system scheduler classes
llvm-svn: 320274
2017-12-10 00:12:57 +00:00
Simon Pilgrim 3508a09455 [X86] Tag ALLOCA/VAARG instructions as system scheduler classes
llvm-svn: 320273
2017-12-10 00:03:16 +00:00
Joel Jones 5cc21e83ce [AArch64] Improve loop unrolling performance on Cavium T99
This patch improves performance on Cavium T99 as shown here (libquantum 0.2.4):

https://docs.google.com/spreadsheets/d/1Lo1o2E1NjrpkwS7DvYYWsiVvPdd93h7KBaqeptMrZPY/edit?usp=sharing

By increasing the LoopMicroOpsBufferSize in the Cavium T99 Scheduler file,
loop unrolling becomes more aggressive. This helps performance on T99.

Test case included.

Patch by Stefan Teleman

Differential Revision: https://reviews.llvm.org/D40695 

llvm-svn: 320272
2017-12-09 23:59:55 +00:00
Simon Pilgrim a42a54258e [InstCombine] Fix SimplifyDemandedUseBits SHL handling (PR35515)
Don't assume that the pattern matched SRL can be cast to an Instruction (might be ConstExpr etc.)

llvm-svn: 320270
2017-12-09 23:42:56 +00:00