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7 Commits

Author SHA1 Message Date
Daniel Sanders 0d97270ae5 [mips] Use --check-prefixes where appropriate. NFC. 
llvm-svn: 273669
 2016-06-24 12:23:17 +00:00
Hrvoje Varga f1e0a03d08 [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions 
Differential Revision: http://reviews.llvm.org/D16917

llvm-svn: 272876
 2016-06-16 07:06:25 +00:00
Vasileios Kalintiris 32177d6bec [mips] Optimize code generation for 64-bit variable shift instructions. 
Summary:
The 64-bit version of the variable shift instructions uses the
shift_rotate_reg class which uses a GPR32Opnd to specify the variable
shift amount. With this patch we avoid the generation of a redundant
SLL instruction for the variable shift instructions in 64-bit targets.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7413

llvm-svn: 235376
 2015-04-21 10:49:03 +00:00
Akira Hatanaka 2a232d81f6 Remove definitions of double word shift plus 32 instructions. Assembler or 
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.

llvm-svn: 146893
 2011-12-19 19:44:09 +00:00
Akira Hatanaka 7ba8a8d656 Add definitions of Mips64 rotate instructions. 
llvm-svn: 140870
 2011-09-30 18:51:46 +00:00
Akira Hatanaka b381129095 Check values of immediate operands. 
llvm-svn: 140860
 2011-09-30 17:19:21 +00:00
Akira Hatanaka 61e256aa69 Mips64 shift instructions. 
llvm-svn: 140841
 2011-09-30 03:18:46 +00:00