Commit Graph

175839 Commits

Author SHA1 Message Date
Kamil Rytarowski 502ba11583 Revert duplicate check for DragonFly BSD
Summary: Revert duplicate check for DragonFly BSD

Submitted by tuxillo.

Reviewers: krytarowski

Reviewed By: krytarowski

Subscribers: mgorny, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58907

llvm-svn: 355319
2019-03-04 15:51:02 +00:00
Simon Pilgrim eeb1144d27 [X86] Regenerate illegal type load test with non-undef load address.
This would be affected by an upcoming patch without undoing some of the bugpoint reduction.

llvm-svn: 355316
2019-03-04 14:49:02 +00:00
Kamil Rytarowski 0c5b6ede2f Unbreak shared library linkage on DragonFlyBSD.
Patch submitted by rimvydas.

Reviewers: llvm-commits, krytarowski, mgorny

Reviewed By: krytarowski, mgorny

Subscribers: mgorny

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D35125

llvm-svn: 355315
2019-03-04 14:36:43 +00:00
Andrea Di Biagio 3437142aad [MCA] Remove unused methods. NFC
llvm-svn: 355314
2019-03-04 13:34:56 +00:00
Dmitry Preobrazhensky 6023d5990d [AMDGPU][MC] Enable lds_direct operand for v_readfirstlane_b32, v_readlane_b32 and v_writelane_b32
See bug 40662: https://bugs.llvm.org/show_bug.cgi?id=40662

Reviewers: artem.tamazov, arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D58713

llvm-svn: 355312
2019-03-04 12:48:32 +00:00
Andrea Di Biagio 9735d9011a [MCA] Correctly initialize struct SummaryView::BackPressureInfo.
This should appease the buildbots.

llvm-svn: 355309
2019-03-04 12:23:05 +00:00
Andrea Di Biagio be3281a281 [MCA] Highlight kernel bottlenecks in the summary view.
This patch adds a new flag named -bottleneck-analysis to print out information
about throughput bottlenecks.

MCA knows how to identify and classify dynamic dispatch stalls. However, it
doesn't know how to analyze and highlight kernel bottlenecks.  The goal of this
patch is to teach MCA how to correlate increases in backend pressure to backend
stalls (and therefore, the loss of throughput).

From a Scheduler point of view, backend pressure is a function of the scheduler
buffer usage (i.e. how the number of uOps in the scheduler buffers changes over
time). Backend pressure increases (or decreases) when there is a mismatch
between the number of opcodes dispatched, and the number of opcodes issued in
the same cycle.  Since buffer resources are limited, continuous increases in
backend pressure would eventually leads to dispatch stalls. So, there is a
strong correlation between dispatch stalls, and how backpressure changed over
time.

This patch teaches how to identify situations where backend pressure increases
due to:
 - unavailable pipeline resources.
 - data dependencies.

Data dependencies may delay execution of instructions and therefore increase the
time that uOps have to spend in the scheduler buffers. That often translates to
an increase in backend pressure which may eventually lead to a bottleneck.
Contention on pipeline resources may also delay execution of instructions, and
lead to a temporary increase in backend pressure.

Internally, the Scheduler classifies instructions based on whether register /
memory operands are available or not.

An instruction is marked as "ready to execute" only if data dependencies are
fully resolved.
Every cycle, the Scheduler attempts to execute all instructions that are ready
to execute. If an instruction cannot execute because of unavailable pipeline
resources, then the Scheduler internally updates a BusyResourceUnits mask with
the ID of each unavailable resource.

ExecuteStage is responsible for tracking changes in backend pressure. If backend
pressure increases during a cycle because of contention on pipeline resources,
then ExecuteStage sends a "backend pressure" event to the listeners.
That event would contain information about instructions delayed by resource
pressure, as well as the BusyResourceUnits mask.

Note that ExecuteStage also knows how to identify situations where backpressure
increased because of delays introduced by data dependencies.

The SummaryView observes "backend pressure" events and prints out a "bottleneck
report".

Example of bottleneck report:

```
Cycles with backend pressure increase [ 99.89% ]
Throughput Bottlenecks:
  Resource Pressure       [ 0.00% ]
  Data Dependencies:      [ 99.89% ]
   - Register Dependencies [ 0.00% ]
   - Memory Dependencies   [ 99.89% ]
```

A bottleneck report is printed out only if increases in backend pressure
eventually caused backend stalls.

About the time complexity:

Time complexity is linear in the number of instructions in the
Scheduler::PendingSet.

The average slowdown tends to be in the range of ~5-6%.
For memory intensive kernels, the slowdown can be significant if flag
-noalias=false is specified. In the worst case scenario I have observed a
slowdown of ~30% when flag -noalias=false was specified.

We can definitely recover part of that slowdown if we optimize class LSUnit (by
doing extra bookkeeping to speedup queries). For now, this new analysis is
disabled by default, and it can be enabled via flag -bottleneck-analysis. Users
of MCA as a library can enable the generation of pressure events through the
constructor of ExecuteStage.

This patch partially addresses https://bugs.llvm.org/show_bug.cgi?id=37494

Differential Revision: https://reviews.llvm.org/D58728

llvm-svn: 355308
2019-03-04 11:52:34 +00:00
Jeremy Morse 09d8ea5282 [X86] Avoid codegen changes when DBG_VALUE appears between lowered selects
X86TargetLowering::EmitLoweredSelect presently detects sequences of CMOV pseudo
instructions without accounting for debug intrinsics. This leads to different
codegen with and without option -g, if a DBG_VALUE instruction lands in the
middle of several lowered selects.

Work around this by skipping over debug instructions when looking for CMOV
sequences, and sinking those debug insts into the EmitLoweredSelect sunk block.
This might slightly shift where variables appear in the instruction sequence,
but won't re-order assignments.

Differential Revision: https://reviews.llvm.org/D58672

llvm-svn: 355307
2019-03-04 10:56:02 +00:00
Oliver Stannard 181afc7f3b [ARM] Fix selection of VLDR.16 instruction with imm offset
The isScaledConstantInRange function takes upper and lower bounds which are
checked after dividing by the scale, so the bounds checks for half, single and
double precision should all be the same. Previously, we had wrong bounds checks
for half precision, so selected an immediate the instructions can't actually
represent.

Differential revision: https://reviews.llvm.org/D58822

llvm-svn: 355305
2019-03-04 09:17:38 +00:00
Jonas Hahnfeld 65a401f6a9 [AArch64/ARM] Fix two compiler warnings in InstructionSelector, NFCI
1) GCC complains that KnownValid is set but not used.
2) In ARMInstructionSelector::selectGlobal() the code is mixing "enumeral
   and non-enumeral type in conditional expression". Solve this by casting
   to unsigned which is the final type anyway.

Differential Revision: https://reviews.llvm.org/D58834

llvm-svn: 355304
2019-03-04 08:51:32 +00:00
Eugene Leviant daea28ab64 [DebugInfo] Construct nested types on behalf of owner CU
Differential revision: https://reviews.llvm.org/D58786

llvm-svn: 355303
2019-03-04 07:15:36 +00:00
Michal Gorny 2d8be64401 [llvm] [Support] Revert "Reimplement getMainExecutable() using sysctl on NetBSD"
This apparently does not work reliably after all (non-reentrant?)
and causes test failures such as:

http://lab.llvm.org:8011/builders/netbsd-amd64/builds/19254/steps/run%20unit%20tests/logs/FAIL%3A%20libc%2B%2B%3A%3Asize.pass.cpp

llvm-svn: 355302
2019-03-04 04:53:50 +00:00
Davide Italiano 672bec223d [InstCombine] Mark debug values as unavailable after DCE.
Fixes PR40838.

llvm-svn: 355301
2019-03-04 04:38:58 +00:00
Craig Topper 69abb15b81 [SubtargetFeatures] Add operator< for comparing SubtargetInfoKV objects. NFCI
Use instead of passing a lambda to std::is_sorted. This is more consistent with SubtargetFeatureKV.

llvm-svn: 355300
2019-03-04 04:26:31 +00:00
Craig Topper b306ef12f0 [SubtargetFeatures] Don't call ApplyFeatureFlag if the feature name is '+help'
Just print the help and stop. Otherwise we'll print a message about it not being a real feature name after printing the help text.

llvm-svn: 355299
2019-03-04 02:02:24 +00:00
Craig Topper a761f9f407 [SubtargetFeatuers] Simplify the code used to imply features from CPU name.
If we make SetImpliedBits OR features outside of its loop, we can reuse it for the first round of implying features for CPUs.

llvm-svn: 355298
2019-03-04 02:02:22 +00:00
Heejin Ahn 195a62e9ae [WebAssembly] Delete ThrowUnwindDest map from WasmEHFuncInfo
Summary:
Before when we implemented the first EH proposal, 'catch <tag>'
instruction may not catch an exception so there were multiple EH pads an
exception can unwind to. That means a BB could have multiple EH pad
successors.

Now after we switched to the new proposal, every 'catch' instruction
catches an exception, and there is only one catchpad per catchswitch, so
we at most have one EH pad successor, making `ThrowUnwindDest` map in
`WasmEHInfo` unnecessary.

Keeping `ThrowUnwindDest` map in `WasmEHInfo` has its own problems,
because other optimization passes can split a BB that contains possibly
throwing calls (previously invokes), and we have to update the map every
time that happens, which is not easy for common CodeGen passes.

This also correctly updates successor info in LateEHPrepare when we add
a rethrow instruction.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58486

llvm-svn: 355296
2019-03-03 22:35:56 +00:00
Craig Topper e9e4a0f5b4 [X86] Regenerate test to get the full FP operands printed. NFC
Missed when I updated the printer to print implicit %st operand on binops.

llvm-svn: 355295
2019-03-03 20:28:52 +00:00
Sanjay Patel e076491759 [InstCombine] remove stale FIXME comment from test; NFC
llvm-svn: 355293
2019-03-03 19:08:54 +00:00
Sanjay Patel 2a70703770 [ValueTracking] do not try to peek through bitcasts in computeKnownBitsFromAssume()
There are no tests for this case, and I'm not sure how it could ever work,
so I'm just removing this option from the matcher. This should fix PR40940:
https://bugs.llvm.org/show_bug.cgi?id=40940

llvm-svn: 355292
2019-03-03 18:59:33 +00:00
Amaury Sechet d341a94261 Add extra ops in add to sub transform test in order to enforce proper operand ordering. NFC
llvm-svn: 355291
2019-03-03 15:11:13 +00:00
Fangrui Song 5fa53d1593 [DemandedBits] Remove some redundancy in the work list
InputIsKnownDead check is shared by all operands. Compute it once.

For non-integer instructions, use Visited.insert(I).second to replace a
find() and an insert().

llvm-svn: 355290
2019-03-03 14:50:01 +00:00
Simon Pilgrim e48be5d698 Remove unused variable. NFCI.
llvm-svn: 355289
2019-03-03 14:23:07 +00:00
Simon Pilgrim d8e91a54c0 [X86] getShuffleScalarElt - peek through insert/extract subvector nodes.
llvm-svn: 355288
2019-03-03 14:11:05 +00:00
Simon Pilgrim 11149ea433 [X86] Pull out combineToConsecutiveLoads helper. NFCI.
llvm-svn: 355287
2019-03-03 13:53:27 +00:00
Kristina Brooks 24659eb2e7 Remove large amount of empty lines mid-file. NFC
llvm-svn: 355286
2019-03-03 13:21:38 +00:00
Fangrui Song 981f216d1d [DemandedBits] Optimize a find()+insert pattern with try_emplace and APInt::operator|=
llvm-svn: 355284
2019-03-03 11:12:57 +00:00
Michal Gorny 8f04766d13 [llvm] [Support] Reimplement getMainExecutable() using sysctl on NetBSD
Use sysctl() to implement getMainExecutable() on NetBSD, rather than
trying to guess the correct path from argv[0].  This is one
of the fixes to recent clang-check-mac-libcxx-fixed-compilation-db.cpp
test failure on NetBSD.

This has been historically done on both FreeBSD and NetBSD in r303015,
and reverted in r303285 due to buggy implementation on FreeBSD.
However, FWIK the NetBSD implementation does not suffer from the same
bugs and is more reliable than playing with argv[0].

Differential Revision: https://reviews.llvm.org/D56975

llvm-svn: 355283
2019-03-03 10:06:40 +00:00
Craig Topper ce68659772 [X86] Prefer VPBLENDD for v2i64/v4i64 blends with AVX2.
We were using VPBLENDW for v2i64 and VBLENDPD for v4i64. VPBLENDD has better throughput than VPBLENDW on some CPUs so it makes sense to use it when possible. VBLENDPD will probably become VBLENDD during execution domain fixing, but we might as well use integer in isel while we can.

This should work around some issues with the domain fixing pass prefering PBLENDW when we start with PBLENDW. There may still be some v8i16 cases that could use PBLENDD.

llvm-svn: 355281
2019-03-03 00:18:07 +00:00
Amaury Sechet 315d0bbb9c Add test case for add to sub transformation. NFC
llvm-svn: 355277
2019-03-02 20:12:25 +00:00
Nico Weber 84f2803bc6 gn build: Add a cfi/sources target.
This build target is currently unused, but after r355144 the sync script
started complaining about cfi.cpp not being listed, and this makes the
script happy again.

llvm-svn: 355275
2019-03-02 18:29:56 +00:00
Sanjay Patel 1f65903dc1 [InstCombine] move add after smin/smax
Follow-up to rL355221.
This isn't specifically called for within PR14613,
but we'll get there eventually if it's not already
requested in some other bug report.

https://rise4fun.com/Alive/5b0

  Name: smax
  Pre: WillNotOverflowSignedSub(C1,C0)
  %a = add nsw i8 %x, C0
  %cond = icmp sgt i8 %a, C1
  %r = select i1 %cond, i8 %a, i8 C1
  =>
  %c2 = icmp sgt i8 %x, C1-C0
  %u2 = select i1 %c2, i8 %x, i8 C1-C0
  %r = add nsw i8 %u2, C0

  Name: smin
  Pre: WillNotOverflowSignedSub(C1,C0)
  %a = add nsw i32 %x, C0
  %cond = icmp slt i32 %a, C1
  %r = select i1 %cond, i32 %a, i32 C1
  =>
  %c2 = icmp slt i32 %x, C1-C0
  %u2 = select i1 %c2, i32 %x, i32 C1-C0
  %r = add nsw i32 %u2, C0

llvm-svn: 355272
2019-03-02 16:45:10 +00:00
Sanjay Patel 42ad8685c6 [InstCombine] add tests for add+smin/smax; NFC
llvm-svn: 355271
2019-03-02 16:45:05 +00:00
Amaury Sechet 31291a403c Add test case for add to sub transformation. NFC
llvm-svn: 355269
2019-03-02 14:28:59 +00:00
Simon Pilgrim f436f70fb8 Fix update_mir_test_checks.py to run on python3
Split off from D58817

Differential Revision: https://reviews.llvm.org/D58820

llvm-svn: 355268
2019-03-02 11:14:01 +00:00
Simon Pilgrim 37a63a748e Use SDValue::getConstantOperandAPInt helper where possible. NFCI.
llvm-svn: 355267
2019-03-02 11:11:22 +00:00
Xing GUO 23b1dfe675 [Transforms] fix typo in test case. NFC.
llvm-svn: 355265
2019-03-02 08:32:32 +00:00
Xing GUO 33649349c5 [Codegen] fix typos in test case
llvm-svn: 355264
2019-03-02 08:03:59 +00:00
Xing GUO b285878907 [llvm-objdump] Should print unknown d_tag in hex format
Summary:
Currently, `llvm-objdump` prints "unknown" instead of d_tag value in hex format. Because getDynamicTagAsString returns "unknown" rather than empty 
string.

Reviewers: grimar, jhenderson

Reviewed By: jhenderson

Subscribers: rupprecht, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58763

llvm-svn: 355262
2019-03-02 04:20:28 +00:00
Thomas Lively 43876ae7bc [WebAssembly] Expand operations not supported by SIMD
Summary:
This prevents crashes in instruction selection when these operations
are used. The tests check that the scalar version of the instruction
is used where applicable, although some expansions do not use the
scalar version.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58859

llvm-svn: 355261
2019-03-02 03:32:25 +00:00
Amaury Sechet f24abf6511 [X86] Improve use of SHLD/SHRD
Summary:
This extends the variety of pattern that can generate a SHLD instead of using two shifts.

This fixes a regression that would be introduced by D57367 or D33587

Reviewers: RKSimon, craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D57389

llvm-svn: 355260
2019-03-02 02:44:16 +00:00
Florian Hahn 98f11a7d75 [SCEV] Handle case where MaxBECount is less precise than ExactBECount for OR.
In some cases, MaxBECount can be less precise than ExactBECount for AND
and OR (the AND case was PR26207). In the OR test case, both ExactBECounts are
undef, but MaxBECount are different, so we hit the assertion below. This
patch uses the same solution the AND case already uses.

Assertion failed:
   ((isa<SCEVCouldNotCompute>(ExactNotTaken) || !isa<SCEVCouldNotCompute>(MaxNotTaken))
     && "Exact is not allowed to be less precise than Max"), function ExitLimit

This patch also consolidates test cases for both AND and OR in a single
test case.

Fixes https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=13245

Reviewers: sanjoy, efriedma, mkazantsev

Reviewed By: sanjoy

Differential Revision: https://reviews.llvm.org/D58853

llvm-svn: 355259
2019-03-02 02:31:44 +00:00
Amaury Sechet 1cc0f6061f Add test case for truncate funnel shifts. NFC
llvm-svn: 355258
2019-03-02 02:24:36 +00:00
Florian Hahn 3c7e92b5d6 [SCEV] Remove undef check for SCEVConstant (NFC)
The value stored in SCEVConstant is of type ConstantInt*, which can
never be UndefValue. So we should never hit that code.

Reviewers: mkazantsev, sanjoy

Reviewed By: sanjoy

Differential Revision: https://reviews.llvm.org/D58851

llvm-svn: 355257
2019-03-02 01:57:28 +00:00
Vlad Tsyrklevich 53a9f1d367 Revert "[DWARFFormValue] Cleanup DWARFFormValue interface. (2/2) (NFC)"
This reverts commit r355233, it was causing UBSan failures.

llvm-svn: 355255
2019-03-02 01:10:00 +00:00
Thomas Lively 7ec62fde78 Revert "[WebAssembly][WIP] Expand operations not supported by SIMD"
This was accidentally committed without tests or review.

llvm-svn: 355254
2019-03-02 00:55:16 +00:00
Mandeep Singh Grang a14f20c5b3 [ProfileData] Sort FuncData before iteration to remove non-determinism
Reviewers: rsmith, bogner, dblaikie

Reviewed By: dblaikie

Subscribers: Hahnfeld, jdoerfert, vsk, dblaikie, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D57986

llvm-svn: 355252
2019-03-02 00:47:43 +00:00
Thomas Lively f5a8c28e7e [WebAssembly][WIP] Expand operations not supported by SIMD
llvm-svn: 355247
2019-03-02 00:18:07 +00:00
Mandeep Singh Grang ba4538708a [llvm] Fix typo: 's/analsyis/analysis/' [NFC]
llvm-svn: 355246
2019-03-02 00:14:10 +00:00
Daniel Sanders c365cee658 [tblgen] Track CodeInit origins when possible
Summary:
Add an SMLoc to CodeInit that records the source line it originated from.
This allows tablegen to point precisely at portions of code when reporting
errors within the CodeInit. For example, in the upcoming GlobalISel
combiner, it can report undefined expansions and point at the instance of
the expansion. This is achieved using something like:
  SMLoc::getFromPointer(SMLoc::getPointer() +
                        (StringRef - CodeInit::getValue()))

The location is lost when producing a CodeInit by string concatenation so
a fallback SMLoc is required (e.g. the Record::getLoc()) but that's pretty
rare for CodeInits.

There's a reasonable case for extending tracking of a couple other Init
objects, for example StringInit's are often parsed and it would be good to
point inside the string when reporting errors about that. However, location
tracking also harms de-duplication. This is fine for CodeInit where there's
only a few hundred of them (~160 for X86) and it may be worth it for
StringInit (~86k up to ~1.9M for roughly 15MB increase for X86).
However the origin tracking would be a _terrible_ idea for IntInit, BitInit,
and UnsetInit. I haven't measured either of those three but BitInit would
most likely be on the order of increasing the current 2 BitInit values up
to billions.

Reviewers: volkan, aditya_nandakumar, bogner, paquette, aemerson

Reviewed By: paquette

Subscribers: javed.absar, kristof.beyls, dexonsmith, llvm-commits, kristina

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58141

llvm-svn: 355245
2019-03-02 00:12:57 +00:00