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428 Commits

Author SHA1 Message Date
Eric Christopher 92db201e23 This should be TargetMaterializeConstant instead. 
llvm-svn: 112795
 2010-09-02 01:48:11 +00:00
Eric Christopher 6a0333c1ed One definition of isThumb is plenty, thanks. 
llvm-svn: 112793
 2010-09-02 01:39:14 +00:00
Eric Christopher 74487fcbe7 Rework arm fast-isel load and store handling. Move offset computation 
into the "address selection" routine and handle constant materialization
for stores.

llvm-svn: 112788
 2010-09-02 00:53:56 +00:00
Eric Christopher fde5a3d494 Some basic store support. 
llvm-svn: 112752
 2010-09-01 22:16:27 +00:00
Eric Christopher 3ce9c4a65f Add some more load types in. 
llvm-svn: 112721
 2010-09-01 18:01:32 +00:00
Eric Christopher 901176a755 Rewrite slightly so we can expand for floating point types easier. 
llvm-svn: 112568
 2010-08-31 01:28:42 +00:00
Eric Christopher bbd1098989 If we have an unhandled type then assert, we shouldn't get here for 
things we can't handle.

llvm-svn: 112559
 2010-08-30 23:48:26 +00:00
Eric Christopher 7a0d8c69cb Do type checks before we bother to do everything else. 
llvm-svn: 112039
 2010-08-25 08:43:57 +00:00
Eric Christopher 761e7fb605 Reorganize load mechanisms. Handle types in a little less fixed way. 
Fix some todos.  No functional change.

llvm-svn: 112031
 2010-08-25 07:23:49 +00:00
Eric Christopher 15b182f4d4 Fix predicate and add a comment. 
llvm-svn: 111981
 2010-08-24 22:34:11 +00:00
Eric Christopher 236ec8f3b5 Rework braindead conditionals I put in yesterday. 
llvm-svn: 111974
 2010-08-24 22:07:27 +00:00
Eric Christopher 6c99ebf5b0 Fix thumb2 mode loads to have the correct operand ordering. Add a todo 
to fix this in the port.

llvm-svn: 111973
 2010-08-24 22:03:02 +00:00
Eric Christopher 46d3a56e5d Update comment. 
llvm-svn: 111887
 2010-08-24 01:10:52 +00:00
Eric Christopher c0c00ca33f Fix the opcode and the operands for the load instruction. 
llvm-svn: 111885
 2010-08-24 01:10:04 +00:00
Eric Christopher eb47692c22 Add register class hack that needs to go away, but makes it more obvious 
that it needs to go away.  Use loadRegFromStackSlot where possible.

Also, remember to update the value map.

llvm-svn: 111883
 2010-08-24 00:50:47 +00:00
Eric Christopher 9d4e471cc2 Add some more debugging code, make it more obvious that RegOffset is 
getting an address for an object and select some default values.

llvm-svn: 111871
 2010-08-24 00:07:24 +00:00
Eric Christopher e3107d6283 Don't need the extra register here. 
llvm-svn: 111864
 2010-08-23 23:28:04 +00:00
Eric Christopher 414501c511 Add some more "get address into register" code and a more TODOs/FIXMEs. 
llvm-svn: 111860
 2010-08-23 23:14:31 +00:00
Eric Christopher 8d03b8a8ce Add an ARMFunctionInfo member and use it. 
llvm-svn: 111854
 2010-08-23 22:32:45 +00:00
Eric Christopher 00202ee329 Start getting ARM loads/address computation going. 
llvm-svn: 111850
 2010-08-23 21:44:12 +00:00
Eric Christopher 985d9e4ea8 Fix loop conditionals (MO.isDef() asserts that it's a reg) and 
move some constraints around.

llvm-svn: 111594
 2010-08-20 00:36:24 +00:00
Eric Christopher d8e8a2945e Add a couple of random comments. 
llvm-svn: 111592
 2010-08-20 00:20:31 +00:00
Eric Christopher a5d60c62b1 Silence warning. 
llvm-svn: 111518
 2010-08-19 15:35:27 +00:00
Eric Christopher 0d274a0258 Add an AddOptionalDefs method and use it. 
llvm-svn: 111489
 2010-08-19 00:37:05 +00:00
Eric Christopher 09f757d4bc Copy over some overridden MI wrappers for ARM fast-isel. This is where 
we're adding predicates and optional defs to the MachineInstrs.

llvm-svn: 111222
 2010-08-17 01:25:29 +00:00
Eric Christopher 663f49900d Make arm fast-isel possible to enable via command line. 
llvm-svn: 111219
 2010-08-17 00:46:57 +00:00
Evan Cheng 23b05d1cf5 ARM fastisel isn't ready. 
llvm-svn: 109421
 2010-07-26 18:32:55 +00:00
Eric Christopher 84bdfd80df Baby steps towards ARM fast-isel. 
llvm-svn: 109047
 2010-07-21 22:26:11 +00:00