llvm-project

Commit Graph

Author	SHA1	Message	Date
Matt Arsenault	8885910f8e	AMDGPU: Remove llvm.SI.tid intrinsic Mesa doesn't emit this for llvm >= 3.8 anymore. llvm-svn: 273050	2016-06-17 21:18:41 +00:00
Matt Arsenault	24692118ba	AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32) This can be done only with moves which theoretically will optimize better later. Although this transform increases the instruction count, it should be code size / cycle count neutral in the worst VALU case. It also seems to slightly improve a couple of testcases due to other DAG combines this exposes. This is probably slightly worse for the SALU case, so it might be better to handle this during moveToVALU, although then you lose some simplifications like the load width reducing in the simple testcase. llvm-svn: 242177	2015-07-14 18:20:33 +00:00
Tom Stellard	45bb48ea19	R600 -> AMDGPU rename llvm-svn: 239657	2015-06-13 03:28:10 +00:00

Author

SHA1

Message

Date

Matt Arsenault

8885910f8e

AMDGPU: Remove llvm.SI.tid intrinsic

Mesa doesn't emit this for llvm >= 3.8 anymore.

llvm-svn: 273050

2016-06-17 21:18:41 +00:00

Matt Arsenault

24692118ba

AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)

This can be done only with moves which theoretically
will optimize better later.

Although this transform increases the instruction count,
it should be code size / cycle count neutral in the worst
VALU case. It also seems to slightly improve a couple
of testcases due to other DAG combines this exposes.

This is probably slightly worse for the SALU case, so
it might be better to handle this during moveToVALU,
although then you lose some simplifications like
the load width reducing in the simple testcase.

llvm-svn: 242177

2015-07-14 18:20:33 +00:00

Tom Stellard

45bb48ea19

R600 -> AMDGPU rename

llvm-svn: 239657

2015-06-13 03:28:10 +00:00

3 Commits